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mega65-r2-max10.qsf
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mega65-r2-max10.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 2018 Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Intel Program License
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors. Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 21:23:43 June 22, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# mega65-r2-max10_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus Prime software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX 10"
set_global_assignment -name DEVICE 10M08SAU169C8G
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:23:43 JUNE 22, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON
set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name QSYS_FILE intclock.qsys
set_global_assignment -name VHDL_FILE top.vhd
set_global_assignment -name VHDL_FILE mk2_to_mk1.vhdl
set_global_assignment -name VHDL_FILE version.vhdl
set_global_assignment -name VHDL_FILE debugtools.vhdl
set_global_assignment -name CDF_FILE output_files/Chain4.cdf
set_location_assignment PIN_A5 -to te_uart_rx
set_location_assignment PIN_B4 -to te_uart_tx
set_location_assignment PIN_J10 -to dbg_uart_rx
set_location_assignment PIN_K10 -to dbg_uart_tx
set_location_assignment PIN_D2 -to CPLD_ADC1
set_location_assignment PIN_C2 -to CPLD_ADC2
set_location_assignment PIN_D1 -to CPLD_ADC3
set_location_assignment PIN_E5 -to RESET_BTN
set_location_assignment PIN_G2 -to M_TCK
set_location_assignment PIN_G1 -to M_TMS
set_location_assignment PIN_F6 -to M_TDO
set_location_assignment PIN_F5 -to M_TDI
set_location_assignment PIN_H6 -to CPLD_CLK
set_location_assignment PIN_M1 -to HDMI_PD
set_location_assignment PIN_N2 -to VDAC_PSAVE_N
set_location_assignment PIN_K11 -to XILINX_SYNC
set_location_assignment PIN_J9 -to XILINX_RX
set_location_assignment PIN_L11 -to XILINX_TX
set_location_assignment PIN_L12 -to K_TDO
set_location_assignment PIN_K12 -to K_IO2
set_location_assignment PIN_J12 -to K_IO3
set_location_assignment PIN_J13 -to BLUE_WIRE
set_location_assignment PIN_H13 -to EN_5V_JOY_N
set_location_assignment PIN_G12 -to FPGA_PROG_B
set_location_assignment PIN_L13 -to K_IO1
set_location_assignment PIN_M5 -to J21[10]
set_location_assignment PIN_J5 -to FPGA_TCK
set_location_assignment PIN_N5 -to J21[11]
set_location_assignment PIN_M7 -to J21[9]
set_location_assignment PIN_N6 -to J21[8]
set_location_assignment PIN_N8 -to J21[5]
set_location_assignment PIN_N7 -to J21[7]
set_location_assignment PIN_K6 -to FPGA_INIT
set_location_assignment PIN_J6 -to FPGA_DONE
set_location_assignment PIN_M9 -to J21[4]
set_location_assignment PIN_M8 -to J21[6]
set_location_assignment PIN_K7 -to FPGA_TDO
set_location_assignment PIN_J7 -to FPGA_TDI
set_location_assignment PIN_M12 -to K_TCK
set_location_assignment PIN_M13 -to K_TDI
set_location_assignment PIN_N9 -to J21[3]
set_location_assignment PIN_N10 -to J21[1]
set_location_assignment PIN_M11 -to K_JTAGEN
set_location_assignment PIN_K8 -to FPGA_TMS
set_location_assignment PIN_L10 -to J21[0]
set_location_assignment PIN_M10 -to J21[2]
set_location_assignment PIN_N12 -to K_TMS
set_location_assignment PIN_G9 -to KB_IO2
set_location_assignment PIN_G10 -to KB_TCK
set_location_assignment PIN_F13 -to KB_IO3
set_location_assignment PIN_F12 -to KB_TMS
set_location_assignment PIN_F9 -to KB_JTAGEN
set_location_assignment PIN_F10 -to KB_TDO
set_location_assignment PIN_E9 -to KB_IO1
set_location_assignment PIN_B12 -to LED_R
set_location_assignment PIN_B11 -to CPLD_CFG3
set_location_assignment PIN_C12 -to PMOD2_EN
set_location_assignment PIN_C11 -to CPLD_CFG1
set_location_assignment PIN_B13 -to LED_G
set_location_assignment PIN_A12 -to CPLD_CFG0
set_location_assignment PIN_D9 -to KB_TDI
set_location_assignment PIN_D12 -to PMOD1_FLG
set_location_assignment PIN_D11 -to PMOD1_EN
set_location_assignment PIN_C13 -to PMOD2_FLG
set_location_assignment PIN_A11 -to CPLD_CFG2
set_location_assignment PIN_B5 -to TE_TCK
set_location_assignment PIN_A4 -to TE_TDO
set_location_assignment PIN_A3 -to TE_TDI
set_location_assignment PIN_B3 -to TE_TMS
set_location_assignment PIN_A2 -to M_TX
set_location_assignment PIN_B2 -to M_RX
set_global_assignment -name TOP_LEVEL_ENTITY top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
set_global_assignment -name SDC_FILE mega65-r2-max10.sdc