Allow __vhdl__ literal to be combined with C code #249
JulianKemmerer
started this conversation in
Ideas
Replies: 0 comments
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
-
with surrounding pipelinec code some how
mix math in C and math in VHDL for ex.
Beta Was this translation helpful? Give feedback.
All reactions