From d8aa71bdcbcd3ebb3f51ffec4a4e6ea94b63ac91 Mon Sep 17 00:00:00 2001 From: enriquezgarc Date: Thu, 28 Nov 2024 11:16:03 +0100 Subject: [PATCH] tests/ports/psoc6/../pdm_pcm: Refactored to use interrupt synch. Signed-off-by: enriquezgarc --- .../psoc6/board_ext_hw/multi/pdm_pcm_rx.py | 4 ++-- .../psoc6/board_ext_hw/multi/pdm_pcm_tx.py | 24 +++++++------------ 2 files changed, 10 insertions(+), 18 deletions(-) diff --git a/tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_rx.py b/tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_rx.py index 95dcf0857c62..c5df153456e9 100644 --- a/tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_rx.py +++ b/tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_rx.py @@ -19,7 +19,6 @@ print("*** PDM_PCM tests - RX ***") send_signal = Pin(send_signal_to_tx_pin, mode=Pin.OUT, pull=Pin.PULL_DOWN, value=False) -send_signal.value(0) def generate_exp_seq(data): @@ -37,6 +36,7 @@ def generate_exp_seq(data): rounds = 2 for m in range(rounds): + send_signal.value(0) exp_seq = generate_exp_seq(exp_data[m]) if m == 0: print("*** Test for data high ***") @@ -94,7 +94,7 @@ def rx_complete_irq(obj): rx_done = True -machine.freq(machine.AUDIO_PDM_24_576_000_HZ) +machine.freq(machine.AUDIO_PDM_22_579_000_HZ) pdm_pcm = PDM_PCM( 0, sck=clk_pin, diff --git a/tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_tx.py b/tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_tx.py index 58fedd57f5a1..c1fa5aaa61e0 100644 --- a/tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_tx.py +++ b/tests/ports/psoc6/board_ext_hw/multi/pdm_pcm_tx.py @@ -15,21 +15,13 @@ print("SKIP") raise SystemExit -start_time = time.time() - -sig_val = 1 +sig_val = 0 test_done = False def signal_irq(event): global sig_val - sig_val = 0 - - -def blocking_delay_ms(delay_ms): - start = time.ticks_ms() - while time.ticks_diff(time.ticks_ms(), start) < delay_ms: - pass + sig_val += 1 data_out = Pin(data_out_pin, mode=Pin.OUT, pull=Pin.PULL_DOWN, value=False) @@ -38,12 +30,12 @@ def blocking_delay_ms(delay_ms): sync_data.irq(handler=signal_irq, trigger=Pin.IRQ_RISING) data_out.value(1) -while test_done == False: - while sig_val: - pass - data_out.value(0) - blocking_delay_ms(200000) - test_done = True +while sig_val == 0: + pass + +data_out.value(0) +while sig_val == 1: + pass data_out.deinit() clk_in.deinit()