From 68cd5a11ae9dac5a07a6468bdcae3d1b6341f459 Mon Sep 17 00:00:00 2001 From: Sina Karvandi Date: Mon, 6 May 2024 15:52:23 +0900 Subject: [PATCH] Change await RisingEdge to Timer --- .../test_DebuggerModuleTestingBRAM.py | 89 +++++++++---------- .../test_DebuggerPacketReceiver.py | 16 ++-- .../test_DebuggerPacketSender.py | 18 ++-- .../test_SendReceiveSynchronizer.py | 32 +++---- 4 files changed, 77 insertions(+), 78 deletions(-) diff --git a/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py b/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py index 47f7c0b..cc918cc 100644 --- a/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py +++ b/sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py @@ -18,7 +18,7 @@ import cocotb from cocotb.clock import Clock -from cocotb.triggers import RisingEdge, Timer +from cocotb.triggers import Timer from cocotb.types import LogicArray maximum_number_of_clock_cycles = 1000 @@ -231,43 +231,43 @@ async def DebuggerModuleTestingBRAM_test(dut): # # Assert initial output is unknown # - # assert LogicArray(dut.io_outputPin_0.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_1.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_2.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_3.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_4.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_5.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_6.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_7.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_8.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_9.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_10.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_11.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_12.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_13.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_14.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_15.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_16.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_17.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_18.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_19.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_20.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_21.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_22.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_23.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_24.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_25.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_26.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_27.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_28.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_29.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_30.value) == LogicArray("Z") - # assert LogicArray(dut.io_outputPin_31.value) == LogicArray("Z") - - # - # Create a 1ns period clock on port clock - # - clock = Clock(dut.clock, 1, units="ns") + assert LogicArray(dut.io_outputPin_0.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_1.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_2.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_3.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_4.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_5.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_6.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_7.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_8.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_9.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_10.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_11.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_12.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_13.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_14.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_15.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_16.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_17.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_18.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_19.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_20.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_21.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_22.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_23.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_24.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_25.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_26.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_27.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_28.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_29.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_30.value) == LogicArray("Z") + assert LogicArray(dut.io_outputPin_31.value) == LogicArray("Z") + + # + # Create a 10ns period clock on port clock + # + clock = Clock(dut.clock, 10, units="ns") # # Start the clock. Start it low to avoid issues on the first RisingEdge @@ -287,8 +287,7 @@ async def DebuggerModuleTestingBRAM_test(dut): # dut.reset.value = 1 for _ in range(10): - # await RisingEdge(dut.clock) - await Timer(1, units="ns") + await Timer(10, units="ns") dut.reset.value = 0 dut._log.info("Enabling an interrupting chip to receive commands from BRAM") @@ -338,13 +337,13 @@ async def DebuggerModuleTestingBRAM_test(dut): # Tell the hwdbg to receive BRAM results # dut.io_plInSignal.value = 1 - await Timer(1, units="ns") + await Timer(10, units="ns") dut.io_plInSignal.value = 0 # # Synchronize with the clock. This will regisiter the initial `inputPinX` value # - await Timer(1, units="ns") + await Timer(10, units="ns") # # Wait until the debuggee sends an interrupt to debugger @@ -360,7 +359,7 @@ async def DebuggerModuleTestingBRAM_test(dut): print("Number of clock cycles spent in debuggee (PL): " + str(clock_counter)) clock_counter = clock_counter + 1 - await Timer(1, units="ns") + await Timer(10, units="ns") # # Apply a limitation to the number of clock cycles that @@ -382,7 +381,7 @@ async def DebuggerModuleTestingBRAM_test(dut): # # Run one more clock cycle to apply the latest BRAM modifications # - await Timer(1, units="ns") + await Timer(10, units="ns") # # Print contents of BRAM @@ -394,4 +393,4 @@ async def DebuggerModuleTestingBRAM_test(dut): # of more clock cycles # for _ in range(10): - await Timer(1, units="ns") + await Timer(10, units="ns") diff --git a/sim/hwdbg/communication/DebuggerPacketReceiver/test_DebuggerPacketReceiver.py b/sim/hwdbg/communication/DebuggerPacketReceiver/test_DebuggerPacketReceiver.py index 0b4501c..a3d1530 100644 --- a/sim/hwdbg/communication/DebuggerPacketReceiver/test_DebuggerPacketReceiver.py +++ b/sim/hwdbg/communication/DebuggerPacketReceiver/test_DebuggerPacketReceiver.py @@ -18,7 +18,7 @@ import cocotb from cocotb.clock import Clock -from cocotb.triggers import RisingEdge +from cocotb.triggers import Timer from cocotb.types import LogicArray ''' @@ -73,7 +73,7 @@ async def DebuggerPacketReceiver_test(dut): # dut.reset.value = 1 for _ in range(10): - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.reset.value = 0 dut._log.info("Enabling chip") @@ -92,7 +92,7 @@ async def DebuggerPacketReceiver_test(dut): # a rising-edge detector, so we'll need to make it low) # dut.io_plInSignal.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_plInSignal.value = 0 # @@ -152,7 +152,7 @@ async def DebuggerPacketReceiver_test(dut): # if test_number % 3 == 0: dut.io_noNewDataReceiver.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_noNewDataReceiver.value = 0 else: # @@ -168,20 +168,20 @@ async def DebuggerPacketReceiver_test(dut): # # Go to the next clock cycle # - await RisingEdge(dut.clock) + await Timer(10, units="ns") if test_number % 3 != 0: dut.io_noNewDataReceiver.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_noNewDataReceiver.value = 0 # # Run extra waiting clocks # for _ in range(10): - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # Check the final input on the next clock # - await RisingEdge(dut.clock) + await Timer(10, units="ns") diff --git a/sim/hwdbg/communication/DebuggerPacketSender/test_DebuggerPacketSender.py b/sim/hwdbg/communication/DebuggerPacketSender/test_DebuggerPacketSender.py index 96bb544..c55516c 100644 --- a/sim/hwdbg/communication/DebuggerPacketSender/test_DebuggerPacketSender.py +++ b/sim/hwdbg/communication/DebuggerPacketSender/test_DebuggerPacketSender.py @@ -18,7 +18,7 @@ import cocotb from cocotb.clock import Clock -from cocotb.triggers import RisingEdge +from cocotb.triggers import Timer from cocotb.types import LogicArray ''' @@ -72,7 +72,7 @@ async def DebuggerPacketSender_test(dut): # dut.reset.value = 1 for _ in range(10): - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.reset.value = 0 dut._log.info("Enabling chip") @@ -96,7 +96,7 @@ async def DebuggerPacketSender_test(dut): # a rising-edge detector, so we'll need to make it low) # dut.io_beginSendingBuffer.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_beginSendingBuffer.value = 0 # @@ -113,7 +113,7 @@ async def DebuggerPacketSender_test(dut): # # Synchronize with the clock. This will apply the initial values # - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # This will change the behavior of the data producer to only @@ -138,7 +138,7 @@ async def DebuggerPacketSender_test(dut): # dut.io_sendingData.value = val - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # Now, tell the sender module that there is no longer needed to send data @@ -146,20 +146,20 @@ async def DebuggerPacketSender_test(dut): for i in range(100): if dut.io_sendWaitForBuffer.value == 1: dut.io_noNewDataSender.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_noNewDataSender.value = 0 break - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # Run extra waiting clocks # for _ in range(10): - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # Check the final input on the next clock # - await RisingEdge(dut.clock) + await Timer(10, units="ns") diff --git a/sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py b/sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py index 0273e46..d3a8507 100644 --- a/sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py +++ b/sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py @@ -18,7 +18,7 @@ import cocotb from cocotb.clock import Clock -from cocotb.triggers import RisingEdge +from cocotb.triggers import Timer from cocotb.types import LogicArray ''' @@ -91,7 +91,7 @@ async def SendReceiveSynchronizer_test(dut): # dut.reset.value = 1 for _ in range(10): - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.reset.value = 0 dut._log.info("Enabling chip") @@ -116,14 +116,14 @@ async def SendReceiveSynchronizer_test(dut): # a rising-edge detector, so we'll need to make it low) # dut.io_plInSignal.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_plInSignal.value = 0 # # Activate sending logic to test whether the chip fails synchronizing signals or not # dut.io_beginSendingBuffer.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_beginSendingBuffer.value = 0 # @@ -228,7 +228,7 @@ async def SendReceiveSynchronizer_test(dut): # if test_number % 3 == 0: dut.io_noNewDataReceiver.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_noNewDataReceiver.value = 0 else: # @@ -243,19 +243,19 @@ async def SendReceiveSynchronizer_test(dut): # # Go to the next clock cycle # - await RisingEdge(dut.clock) + await Timer(10, units="ns") if test_number % 3 != 0: dut.io_noNewDataReceiver.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_noNewDataReceiver.value = 0 # # Run extra waiting clocks # for _ in range(10): - await RisingEdge(dut.clock) + await Timer(10, units="ns") ############################################################### # # @@ -276,14 +276,14 @@ async def SendReceiveSynchronizer_test(dut): # a rising-edge detector, so we'll need to make it low) # dut.io_beginSendingBuffer.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_beginSendingBuffer.value = 0 # # Activate receiving logic to test whether the chip fails synchronizing signals or not # dut.io_plInSignal.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_plInSignal.value = 0 # @@ -300,7 +300,7 @@ async def SendReceiveSynchronizer_test(dut): # # Synchronize with the clock. This will apply the initial values # - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # This will change the behavior of the data producer to only @@ -325,7 +325,7 @@ async def SendReceiveSynchronizer_test(dut): # dut.io_sendingData.value = val - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # Now, tell the sender module that there is no longer needed to send data @@ -333,20 +333,20 @@ async def SendReceiveSynchronizer_test(dut): for i in range(100): if dut.io_sendWaitForBuffer.value == 1: dut.io_noNewDataSender.value = 1 - await RisingEdge(dut.clock) + await Timer(10, units="ns") dut.io_noNewDataSender.value = 0 break - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # Run extra waiting clocks # for _ in range(10): - await RisingEdge(dut.clock) + await Timer(10, units="ns") # # Check the final input on the next clock # - await RisingEdge(dut.clock) + await Timer(10, units="ns")