diff --git a/src/main/scala/hwdbg/interpreter/interpreter.scala b/src/main/scala/hwdbg/communication/interpreter.scala
similarity index 93%
rename from src/main/scala/hwdbg/interpreter/interpreter.scala
rename to src/main/scala/hwdbg/communication/interpreter.scala
index fd295bb..e6da160 100644
--- a/src/main/scala/hwdbg/interpreter/interpreter.scala
+++ b/src/main/scala/hwdbg/communication/interpreter.scala
@@ -12,7 +12,7 @@
   * @copyright
   *   This project is released under the GNU Public License v3.
   */
-package hwdbg.interpreter
+package hwdbg.communication
 
 import chisel3._
 import chisel3.util.{switch, is}
@@ -67,7 +67,9 @@ class DebuggerPacketInterpreter(
     //
     val interpretationDone = Output(Bool()) // interpretation done or not?
     val foundValidPacket = Output(Bool()) // packet was valid or not
-    val requestedActionOfThePacket = Output(UInt(32.W)) // the requested action
+    val requestedActionOfThePacket = Output(
+      UInt(new DebuggerRemotePacket().getWidth.W)
+    ) // the requested action
 
   })
 
@@ -301,7 +303,9 @@ object DebuggerPacketInterpreter {
     val rdWrAddr = Wire(UInt(bramAddrWidth.W))
     val interpretationDone = Wire(Bool())
     val foundValidPacket = Wire(Bool())
-    val requestedActionOfThePacket = Wire(UInt(32.W))
+    val requestedActionOfThePacket = Wire(
+      UInt(new DebuggerRemotePacket().getWidth.W)
+    )
 
     //
     // Configure the input signals
diff --git a/src/main/scala/hwdbg/communication/sender.scala b/src/main/scala/hwdbg/communication/sender.scala
new file mode 100644
index 0000000..2252f70
--- /dev/null
+++ b/src/main/scala/hwdbg/communication/sender.scala
@@ -0,0 +1,77 @@
+/** @file
+  *   sender.scala
+  * @author
+  *   Sina Karvandi (sina@hyperdbg.org)
+  * @brief
+  *   Remote debugger packet sender module
+  * @details
+  * @version 0.1
+  * @date
+  *   2024-04-16
+  *
+  * @copyright
+  *   This project is released under the GNU Public License v3.
+  */
+package hwdbg.communication
+
+import chisel3._
+import chisel3.util.{switch, is}
+import circt.stage.ChiselStage
+
+import hwdbg.configs._
+import hwdbg.types._
+import hwdbg.utils._
+import hwdbg.constants._
+
+object DebuggerPacketSenderEnums {
+  object State extends ChiselEnum {
+    val sIdle, sInit, sDone = Value
+  }
+}
+
+class DebuggerPacketSender(
+    debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
+    bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
+    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+) extends Module {
+
+  //
+  // Import state enum
+  //
+  import DebuggerPacketSenderEnums.State
+  import DebuggerPacketSenderEnums.State._
+
+  val io = IO(new Bundle {
+
+    //
+    // Chip signals
+    //
+    val en = Input(Bool()) // chip enable signal
+
+    //
+    // Interrupt signals (lines)
+    // Note: Only PS output signal is exported here,
+    // a separate module will control the PL signal
+    //
+    val psOutInterrupt = Output(Bool()) // PL to PS interrupt
+
+    //
+    // BRAM (Block RAM) ports
+    //
+    val rdWrAddr = Output(UInt(bramAddrWidth.W)) // read/write address
+    val wrEna = Output(Bool()) // enable writing
+    val wrData = Output(UInt(bramDataWidth.W)) // write data
+
+    //
+    // Sending signals
+    //
+    val sendingSignalDone = Output(Bool()) // sending signal done or not?
+    val foundValidPacket = Output(Bool()) // packet was valid or not
+    val requestedActionOfThePacket =
+      Output(
+        UInt(new DebuggerRemotePacket().getWidth.W)
+      ) // the requested action
+
+  })
+
+}
diff --git a/src/main/scala/hwdbg/configs/constants.scala b/src/main/scala/hwdbg/configs/constants.scala
index eb8f925..644122e 100644
--- a/src/main/scala/hwdbg/configs/constants.scala
+++ b/src/main/scala/hwdbg/configs/constants.scala
@@ -31,3 +31,36 @@ object HyperDbgSharedConstants {
     0x4859504552444247L // HYPERDBG = 0x4859504552444247
 
 }
+
+/** @brief
+  *   Enumeration for different packet types in HyperDbg packets
+  * @warning
+  *   Used in HyperDbg
+  */
+object DEBUGGER_REMOTE_PACKET_TYPE extends Enumeration {
+
+  //
+  // Debugger to debuggee (vmx-root)
+  //
+  val DEBUGGER_TO_DEBUGGEE_EXECUTE_ON_VMX_ROOT = Value(1)
+
+  //
+  // Debugger to debuggee (user-mode)
+  //
+  val DEBUGGER_TO_DEBUGGEE_EXECUTE_ON_USER_MODE = Value(2)
+
+  //
+  // Debuggee to debugger (user-mode and kernel-mode, vmx-root mode)
+  //
+  val DEBUGGEE_TO_DEBUGGER = Value(3)
+
+  //
+  // Debugger to debuggee (hardware), used in hwdbg
+  //
+  val DEBUGGER_TO_DEBUGGEE_HARDWARE_LEVEL = Value(4)
+
+  //
+  // Debuggee to debugger (hardware), used in hwdbg
+  //
+  val DEBUGGEE_TO_DEBUGGER_HARDWARE_LEVEL = Value(5)
+}
diff --git a/src/main/scala/hwdbg/main.scala b/src/main/scala/hwdbg/main.scala
index 14fb288..4211162 100644
--- a/src/main/scala/hwdbg/main.scala
+++ b/src/main/scala/hwdbg/main.scala
@@ -18,7 +18,7 @@ import chisel3._
 import circt.stage.ChiselStage
 
 import hwdbg.configs._
-import hwdbg.interpreter._
+import hwdbg.communication._
 
 class DebuggerMain(
     debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
diff --git a/src/main/scala/hwdbg/types/communication.scala b/src/main/scala/hwdbg/types/communication_types.scala
similarity index 100%
rename from src/main/scala/hwdbg/types/communication.scala
rename to src/main/scala/hwdbg/types/communication_types.scala