diff --git a/src/test/tb/.gitignore b/sim/.gitignore similarity index 100% rename from src/test/tb/.gitignore rename to sim/.gitignore diff --git a/src/test/tb/Makefile b/sim/Makefile similarity index 66% rename from src/test/tb/Makefile rename to sim/Makefile index 1c521a1..86a5b9d 100644 --- a/src/test/tb/Makefile +++ b/sim/Makefile @@ -1,7 +1,7 @@ # Makefile TOPLEVEL_LANG = verilog -VERILOG_SOURCES = $(shell pwd)/../../../generated/DebuggerModuleTestingBRAM.sv +VERILOG_SOURCES = $(shell pwd)/../generated/DebuggerModuleTestingBRAM.sv TOPLEVEL = DebuggerModuleTestingBRAM MODULE = test_DebuggerModuleTestingBRAM diff --git a/sim/modelsim.config b/sim/modelsim.config deleted file mode 100644 index 7ada313..0000000 --- a/sim/modelsim.config +++ /dev/null @@ -1,3 +0,0 @@ -module:OnlineMultipleComparatorTest -io_result -io_resultValid \ No newline at end of file diff --git a/sim/modelsim.tcl b/sim/modelsim.tcl deleted file mode 100644 index 7ae3b32..0000000 --- a/sim/modelsim.tcl +++ /dev/null @@ -1,2 +0,0 @@ -add wave -position insertpoint {*io_result*} -add wave -position insertpoint {*io_resultValid*} diff --git a/sim/README.md b/sim/modelsim/README.md similarity index 85% rename from sim/README.md rename to sim/modelsim/README.md index e45ff72..f511e03 100644 --- a/sim/README.md +++ b/sim/modelsim/README.md @@ -8,16 +8,16 @@ In the "modelsim.config" file, the first line that starts with "module:" is the For example: ``` -module:MinMaxParallelOnlineComparatorTest +module:DebuggerModuleTest clock -maxOutput_3 +inputPin ``` If you don't specify the signals to be filtered, then **ALL** signals will be shown. For example: ``` -module:MinMaxParallelOnlineComparatorTest +module:DebuggerModuleTest ``` At last, run it with the following command: diff --git a/sim/modelsim/modelsim.config b/sim/modelsim/modelsim.config new file mode 100644 index 0000000..cc537f5 --- /dev/null +++ b/sim/modelsim/modelsim.config @@ -0,0 +1,3 @@ +module:DebuggerModuleTest +io_inputPin +io_outputPin \ No newline at end of file diff --git a/sim/modelsim.py b/sim/modelsim/modelsim.py similarity index 100% rename from sim/modelsim.py rename to sim/modelsim/modelsim.py diff --git a/sim/modelsim/modelsim.tcl b/sim/modelsim/modelsim.tcl new file mode 100644 index 0000000..59c5335 --- /dev/null +++ b/sim/modelsim/modelsim.tcl @@ -0,0 +1,2 @@ +add wave -position insertpoint {*io_inputPin*} +add wave -position insertpoint {*io_outputPin*} diff --git a/src/test/tb/test_DebuggerModuleTestingBRAM.py b/sim/test_DebuggerModuleTestingBRAM.py similarity index 62% rename from src/test/tb/test_DebuggerModuleTestingBRAM.py rename to sim/test_DebuggerModuleTestingBRAM.py index b6508dd..d31a9d4 100644 --- a/src/test/tb/test_DebuggerModuleTestingBRAM.py +++ b/sim/test_DebuggerModuleTestingBRAM.py @@ -28,6 +28,22 @@ async def DebuggerModuleTestingBRAM_test(dut): assert LogicArray(dut.io_outputPin_13.value) == LogicArray("X") assert LogicArray(dut.io_outputPin_14.value) == LogicArray("X") assert LogicArray(dut.io_outputPin_15.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_16.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_17.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_18.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_19.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_20.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_21.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_22.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_23.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_24.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_25.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_26.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_27.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_28.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_29.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_30.value) == LogicArray("X") + assert LogicArray(dut.io_outputPin_31.value) == LogicArray("X") # Set initial input value to prevent it from floating dut.io_inputPin_0.value = 0 @@ -46,6 +62,22 @@ async def DebuggerModuleTestingBRAM_test(dut): dut.io_inputPin_13.value = 0 dut.io_inputPin_14.value = 0 dut.io_inputPin_15.value = 0 + dut.io_inputPin_16.value = 0 + dut.io_inputPin_17.value = 0 + dut.io_inputPin_18.value = 0 + dut.io_inputPin_19.value = 0 + dut.io_inputPin_20.value = 0 + dut.io_inputPin_21.value = 0 + dut.io_inputPin_22.value = 0 + dut.io_inputPin_23.value = 0 + dut.io_inputPin_24.value = 0 + dut.io_inputPin_25.value = 0 + dut.io_inputPin_26.value = 0 + dut.io_inputPin_27.value = 0 + dut.io_inputPin_28.value = 0 + dut.io_inputPin_29.value = 0 + dut.io_inputPin_30.value = 0 + dut.io_inputPin_31.value = 0 clock = Clock(dut.clock, 10, units="ns") # Create a 10ns period clock on port clock diff --git a/src/test/tb/run.sh b/sim/test_module.sh similarity index 100% rename from src/test/tb/run.sh rename to sim/test_module.sh diff --git a/src/main/scala/hwdbg/configs/configs.scala b/src/main/scala/hwdbg/configs/configs.scala index bcb1262..0abb9ec 100644 --- a/src/main/scala/hwdbg/configs/configs.scala +++ b/src/main/scala/hwdbg/configs/configs.scala @@ -25,7 +25,7 @@ object DebuggerPorts { // // The following constant shows the key value object of the mappings // of pins to ports (used for inputs) - // For example, + // For example, // port 0 (in) -> contains 12 pins // port 1 (in) -> contains 9 pins // port 2 (in) -> contains 11 pins @@ -35,7 +35,7 @@ object DebuggerPorts { // // The following constant shows the key value object of the mappings // of pins to ports (used for outputs) - // For example, + // For example, // port 0 (out) -> contains 12 pins // port 1 (out) -> contains 9 pins // port 2 (out) -> contains 11 pins diff --git a/src/main/scala/top_test.scala b/src/main/scala/top_test.scala index ddbc823..e486dde 100644 --- a/src/main/scala/top_test.scala +++ b/src/main/scala/top_test.scala @@ -134,10 +134,9 @@ object MainWithInitializedBRAM extends App { ), firtoolOpts = Array( "-disable-all-randomization", - "-strip-debug-info", - "--split-verilog", // The intention for this argument (and next argument) is to separate generated files. + // "--split-verilog", // The intention for this argument (and next argument) is to separate generated files. "-o", - "generated/" + "generated/DebuggerModuleTestingBRAM.sv" ) ) )