diff --git a/BLOCKFILE b/BLOCKFILE
index 8677077ed25710..2e07820dadba73 100644
--- a/BLOCKFILE
+++ b/BLOCKFILE
@@ -21,8 +21,6 @@ BLOCKFILE
 ci/scripts/check-pr-changes-allowed.py
 
 # Earlgrey related RTL
-hw/ip/*/rtl/*
-hw/ip_templates/*/rtl/*
 hw/top_earlgrey/ip/*/rtl/*
 hw/top_earlgrey/ip_autogen/*/rtl/*
 hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
@@ -33,6 +31,48 @@ hw/vendor/lowrisc_ibex/rtl/*
 hw/vendor/pulp_riscv_dbg/src/*
 hw/vendor/pulp_riscv_dbg/debug_rom/*
 
+# IP block RTL for blocks that require a higher scruitinty on changes to
+# maintain stablity (Ascon, DMA and Key Manager DPE are not blocked).
+hw/ip/adc_ctrl/rtl/*
+hw/ip/aes/rtl/*
+hw/ip/aon_timer/rtl/*
+hw/ip/csrng/rtl/*
+hw/ip/edn/rtl/*
+hw/ip/entropy_src/rtl/*
+hw/ip/gpio/rtl/*
+hw/ip/hmac/rtl/*
+hw/ip/i2c/rtl/*
+hw/ip/keymgr/rtl/*
+hw/ip/kmac/rtl/*
+hw/ip/lc_ctrl/rtl/*
+hw/ip/otbn/rtl/*
+hw/ip/otp_ctrl/rtl/*
+hw/ip/pattgen/rtl/*
+hw/ip/pinmux/rtl/*
+hw/ip/prim/rtl/*
+hw/ip/prim_generic/rtl/*
+hw/ip/prim_xilinx/rtl/*
+hw/ip/prim_xilinx_ultrascale/rtl/*
+hw/ip/pwm/rtl/*
+hw/ip/rom_ctrl/rtl/*
+hw/ip/rv_core_ibex/rtl/*
+hw/ip/rv_dm/rtl/*
+hw/ip/rv_timer/rtl/*
+hw/ip/spi_device/rtl/*
+hw/ip/spi_host/rtl/*
+hw/ip/sram_ctrl/rtl/*
+hw/ip/sysrst_ctrl/rtl/*
+hw/ip/tlul/rtl/*
+hw/ip/uart/rtl/*
+hw/ip/usbdev/rtl/*
+
+hw/ip_templates/alert_handler/rtl/*
+hw/ip_templates/clkmgr/rtl/*
+hw/ip_templates/flash_ctrl/rtl/*
+hw/ip_templates/pwrmgr/rtl/*
+hw/ip_templates/rstmgr/rtl/*
+hw/ip_templates/rv_plic/rtl/*
+
 # Individual HJSON files that effect RTL generation (no wildcard as it's
 # too broad and will also block DV-only files)
 hw/ip/lc_ctrl/data/lc_ctrl.hjson