From 794ccbfba4f7fb4614a8dc6fced9aabbbca2e016 Mon Sep 17 00:00:00 2001 From: Greg Chadwick Date: Wed, 4 Dec 2019 12:00:48 +0000 Subject: [PATCH] RISC-V compliance demo + misc changes --- sw/device/examples/hello_world/meson.build | 1 + sw/device/examples/hello_world/srcs.mk | 1 + sw/device/exts/common/_crt.c | 4 ++++ sw/device/exts/common/link.ld | 3 --- .../riscv-target/opentitan/compliance_test.h | 22 +++++++++++++++++++ .../opentitan/device/rv32imc/Makefile.include | 9 +++++--- 6 files changed, 34 insertions(+), 6 deletions(-) diff --git a/sw/device/examples/hello_world/meson.build b/sw/device/examples/hello_world/meson.build index 96ada83dc5acd..8ac2455a73a09 100644 --- a/sw/device/examples/hello_world/meson.build +++ b/sw/device/examples/hello_world/meson.build @@ -15,6 +15,7 @@ hello_world_elf = executable( sw_lib_oled_display, riscv_crt, ], + c_args : ['-DOLED_DRIVER_INC_FONT'] ) hello_world_embedded = custom_target( diff --git a/sw/device/examples/hello_world/srcs.mk b/sw/device/examples/hello_world/srcs.mk index 4cf4756ee719f..997fa21781869 100644 --- a/sw/device/examples/hello_world/srcs.mk +++ b/sw/device/examples/hello_world/srcs.mk @@ -2,4 +2,5 @@ # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 +SW_FLAGS += -DOLED_DRIVER_INC_FONT SW_SRCS += $(SW_DIR)/hello_world.c diff --git a/sw/device/exts/common/_crt.c b/sw/device/exts/common/_crt.c index 0af5c1e0c9884..15c984830dccc 100644 --- a/sw/device/exts/common/_crt.c +++ b/sw/device/exts/common/_crt.c @@ -21,4 +21,8 @@ void _crt(void) { memset(_bss_start, 0, _bss_end - _bss_start); main(); + + while(1) { + asm volatile("wfi"); + } } diff --git a/sw/device/exts/common/link.ld b/sw/device/exts/common/link.ld index b2ff3448157bd..51fd3d01c8ff2 100644 --- a/sw/device/exts/common/link.ld +++ b/sw/device/exts/common/link.ld @@ -106,9 +106,6 @@ SECTIONS { [ .stabstr ] } - - /* Discard the remaining sections */ - /DISCARD/ : { *(*) } } ENTRY(main) diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h index 5d56101ca7bc6..58f7b12aaffb4 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h @@ -20,16 +20,38 @@ j loop_forever; \ #define RV_COMPLIANCE_RV32M \ + .globl oled_clear; \ + .globl oled_write_str; \ + .globl oled_write_disp; \ RVTEST_RV32M \ #define RV_COMPLIANCE_CODE_BEGIN \ RVTEST_CODE_BEGIN \ + la sp, _stack_start; \ + li a0, 1; \ + jal oled_clear; \ + la a0, _rv_compliance_str; \ + la a1, 0; \ + la a2, 0; \ + jal oled_write_str; \ + la a0, _rv_test_name_str; \ + la a1, 2; \ + la a2, 0; \ + jal oled_write_str; \ + jal oled_write_disp; \ #define RV_COMPLIANCE_CODE_END \ RVTEST_CODE_END \ +#define Stringify(x) #x +#define Stringify2(x) Stringify(x) + #define RV_COMPLIANCE_DATA_BEGIN \ + _rv_test_name_str: \ + .asciz Stringify2(RISCV_TEST_NAME); \ + _rv_compliance_str: \ + .asciz "RISCV Compliance"; \ .section .test.output; \ RVTEST_DATA_BEGIN \ diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include index 6b32d297a2f8a..370ec9335cc20 100644 --- a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include +++ b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include @@ -4,6 +4,7 @@ OPENTITAN = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc OT_SW = $(ROOTDIR)/../../device +OT_BUILD = $(ROOTDIR)/../../../build/sw/device OT_ROOT = $(OT_SW)/../../ OT_TOOLS ?= /tools/riscv/bin OT_FPGA_UART ?= @@ -36,7 +37,8 @@ RUN_TARGET=\ --log $(work_dir_isa)/$<.uart.log; \ grep -o 'SIG: [a-zA-Z0-9_]*' $(work_dir_isa)/$<.uart.log | sed 's/SIG: //' \ > $(work_dir_isa)/$(*).signature.temp.output; \ - tr '[:upper:]' '[:lower:]' < $(work_dir_isa)/$(*).signature.temp.output > $(work_dir_isa)/$(*).signature.output; + tr '[:upper:]' '[:lower:]' < $(work_dir_isa)/$(*).signature.temp.output > $(work_dir_isa)/$(*).signature.output; \ + sleep 1s; RISCV_PREFIX ?= ${OT_TOOLS}/riscv32-unknown-elf- @@ -54,7 +56,7 @@ RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostart # After the libraries are built, the necessary collateral (vmem for verilator, bin # for fpga) are created COMPILE_TARGET=\ - make -C $$(OT_SW) SW_DIR=boot_rom $(MAKEARG) RV_TOOLS=$(OT_TOOLS) clean all; \ + make -C $$(OT_SW) SW_DIR=examples/hello_world $(MAKEARG) RV_TOOLS=$(OT_TOOLS) all; \ $$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \ -I$(ROOTDIR)/riscv-test-env/ \ -I$(ROOTDIR)/riscv-test-env/p/ \ @@ -62,9 +64,10 @@ COMPILE_TARGET=\ -I$(OT_SW)/lib \ -I$(TARGETDIR)/$(RISCV_TARGET)/ \ -I$(TARGETDIR)/$(RISCV_TARGET)/ \ + -DRISCV_TEST_NAME=$$(subst -01,,$$(*F)) \ $(DEFINES) -T$(LDSCRIPT) $$< \ $(OPENTITAN)/wrap.c \ - -L$(OT_SW)/boot_rom/lib \ + -L$(OT_BUILD)/examples/hello_world/lib \ -lot \ -o $(work_dir_isa)/$$@; \ $$(RISCV_OBJDUMP) -SD $(work_dir_isa)/$$@ > $(work_dir_isa)/$$@.objdump; \