From 3860cddb4dc745a9bc924b8491d482ee09174f46 Mon Sep 17 00:00:00 2001 From: Gary Guo Date: Thu, 2 Nov 2023 17:42:38 +0000 Subject: [PATCH] [opentitanlib] split `Jtag` into `JtagChain` and `Jtag` `JtagChain` is now the intermediate type where the adapter has been configured but the specific tap has not yet been selected. This serves as the type-state for the previous unconnected `Jtag`, and the new `Jtag` is the type-state for a connected `Jtag`. Signed-off-by: Gary Guo --- sw/host/opentitanlib/src/app/mod.rs | 6 +- sw/host/opentitanlib/src/io/jtag.rs | 18 +- .../src/test_utils/lc_transition.rs | 19 ++- .../src/transport/chip_whisperer/mod.rs | 6 +- .../src/transport/hyperdebug/mod.rs | 8 +- sw/host/opentitanlib/src/transport/mod.rs | 6 +- sw/host/opentitanlib/src/util/openocd.rs | 161 +++++++----------- sw/host/opentitantool/src/command/lc.rs | 42 +++-- sw/host/provisioning/cp_lib/src/lib.rs | 19 +-- sw/host/provisioning/ft_lib/src/lib.rs | 12 +- sw/host/tests/chip/jtag/src/openocd_test.rs | 14 +- sw/host/tests/chip/jtag/src/sram_load.rs | 7 +- .../manuf_cp_ast_test_execution/src/main.rs | 7 +- .../manuf_cp_device_info_flash_wr/src/main.rs | 14 +- .../manuf/manuf_cp_test_lock/src/main.rs | 21 ++- .../manuf/manuf_cp_unlock_raw/src/main.rs | 14 +- .../manuf_cp_volatile_unlock_raw/src/main.rs | 14 +- .../manuf/manuf_cp_yield_test/src/main.rs | 14 +- sw/host/tests/manuf/manuf_scrap/src/main.rs | 14 +- .../manuf_sram_program_crc_check/src/main.rs | 7 +- sw/host/tests/manuf/otp_ctrl/src/main.rs | 14 +- sw/host/tests/manuf/personalize/src/main.rs | 14 +- .../manuf/provisioning/cp_test/src/main.rs | 21 ++- .../tests/rom/e2e_bootstrap_rma/src/main.rs | 7 +- .../rom/e2e_openocd_debug_test/src/main.rs | 14 +- 25 files changed, 281 insertions(+), 212 deletions(-) diff --git a/sw/host/opentitanlib/src/app/mod.rs b/sw/host/opentitanlib/src/app/mod.rs index 6454885edc102..89247d293ca73 100644 --- a/sw/host/opentitanlib/src/app/mod.rs +++ b/sw/host/opentitanlib/src/app/mod.rs @@ -14,7 +14,7 @@ use crate::io::emu::Emulator; use crate::io::gpio::{GpioMonitoring, GpioPin, PinMode, PullMode}; use crate::io::i2c::Bus; use crate::io::ioexpander::IoExpander; -use crate::io::jtag::{Jtag, JtagParams}; +use crate::io::jtag::{JtagChain, JtagParams}; use crate::io::nonblocking_help::NonblockingHelp; use crate::io::spi::{Target, TransferMode}; use crate::io::uart::Uart; @@ -663,8 +663,8 @@ impl TransportWrapper { }) } - /// Returns a [`Jtag`] implementation. - pub fn jtag(&self, opts: &JtagParams) -> Result> { + /// Returns a [`JtagChain`] implementation. + pub fn jtag(&self, opts: &JtagParams) -> Result> { self.transport.jtag(opts) } diff --git a/sw/host/opentitanlib/src/io/jtag.rs b/sw/host/opentitanlib/src/io/jtag.rs index 1189f17118938..39b08f9068180 100644 --- a/sw/host/opentitanlib/src/io/jtag.rs +++ b/sw/host/opentitanlib/src/io/jtag.rs @@ -25,7 +25,7 @@ pub struct JtagParams { } impl JtagParams { - pub fn create<'t>(&self, transport: &'t TransportWrapper) -> Result> { + pub fn create<'t>(&self, transport: &'t TransportWrapper) -> Result> { let jtag = transport.jtag(self)?; Ok(jtag) } @@ -46,15 +46,21 @@ pub enum JtagError { impl_serializable_error!(JtagError); /// A trait which represents a JTAG interface. +/// +/// JTAG lines form a daisy-chained topology and can connect multiple TAPs together in a chain. +/// This trait represents an adaptor that has been configured to connect to a given JTAG chain, +/// but have not yet been configured to only access a particular TAP. +pub trait JtagChain { + /// Connect to the given JTAG TAP on this chain. + fn connect(self: Box, tap: JtagTap) -> Result>; +} + +/// A trait which represents a TAP on a JTAG chain. pub trait Jtag { - /// Connect to the given JTAG TAP. - fn connect(&mut self, tap: JtagTap) -> Result<()>; /// Disconnect from the TAP. fn disconnect(self: Box) -> Result<()>; /// Get TAP we are currently connected too. - fn tap(&self) -> Option; - - // Commands + fn tap(&self) -> JtagTap; /// Read a lifecycle controller register. fn read_lc_ctrl_reg(&mut self, reg: &LcCtrlReg) -> Result; diff --git a/sw/host/opentitanlib/src/test_utils/lc_transition.rs b/sw/host/opentitanlib/src/test_utils/lc_transition.rs index 98cac2cd05c3f..ed4d557b92ce0 100644 --- a/sw/host/opentitanlib/src/test_utils/lc_transition.rs +++ b/sw/host/opentitanlib/src/test_utils/lc_transition.rs @@ -128,8 +128,11 @@ fn setup_lc_transition( /// transport.reset_target(init.bootstrap.options.reset_delay, true).unwrap(); /// /// // Connect to the LC controller TAP. -/// let mut jtag = transport.jtag(jtag_opts).unwrap(); -/// jtag.connect(JtagTap::LcTap).expect("failed to connect to LC TAP"); +/// let mut jtag = transport +/// .jtag(jtag_opts) +/// .unwrap() +/// .connect(JtagTap::LcTap) +/// .expect("failed to connect to LC TAP"); /// /// let test_exit_token = DifLcCtrlToken::from([0xff; 16]); /// @@ -143,8 +146,11 @@ fn setup_lc_transition( /// Some(JtagTap::LcTap), /// ).expect("failed to trigger transition to prod"); /// -/// jtag = transport.jtag(jtag_opts).unwrap(); -/// jtag.connect(JtagTap::LcTap).expect("failed to reconnect to LC TAP"); +/// jtag = transport +/// .jtag(jtag_opts) +/// .unwrap() +/// .connect(JtagTap::LcTap) +/// .expect("failed to reconnect to LC TAP"); /// /// assert_eq!( /// jtag.read_lc_ctrl_reg(&LcCtrlReg::LCState).unwrap(), @@ -249,8 +255,7 @@ pub fn trigger_volatile_raw_unlock<'t>( // because a volatile unlock will trigger a TAP strap resampling immediately upon success. if post_transition_tap == JtagTap::RiscvTap { jtag.disconnect()?; - jtag = transport.jtag(jtag_params)?; - jtag.connect(JtagTap::RiscvTap)?; + jtag = transport.jtag(jtag_params)?.connect(JtagTap::RiscvTap)?; } wait_for_status( @@ -264,7 +269,7 @@ pub fn trigger_volatile_raw_unlock<'t>( } pub fn wait_for_status(jtag: &mut dyn Jtag, timeout: Duration, status: LcCtrlStatus) -> Result<()> { - let jtag_tap = jtag.tap().unwrap(); + let jtag_tap = jtag.tap(); // Wait for LC controller to be ready. poll::poll_until(timeout, Duration::from_millis(50), || { diff --git a/sw/host/opentitanlib/src/transport/chip_whisperer/mod.rs b/sw/host/opentitanlib/src/transport/chip_whisperer/mod.rs index c5fd83563ef76..d50d634959496 100644 --- a/sw/host/opentitanlib/src/transport/chip_whisperer/mod.rs +++ b/sw/host/opentitanlib/src/transport/chip_whisperer/mod.rs @@ -13,7 +13,7 @@ use std::path::PathBuf; use std::rc::Rc; use crate::io::gpio::GpioPin; -use crate::io::jtag::{Jtag, JtagParams}; +use crate::io::jtag::{JtagChain, JtagParams}; use crate::io::spi::Target; use crate::io::uart::{Uart, UartError}; use crate::transport::common::fpga::{ClearBitstream, FpgaProgram}; @@ -181,9 +181,9 @@ impl Transport for ChipWhisperer { } } - fn jtag(&self, opts: &JtagParams) -> Result> { + fn jtag(&self, opts: &JtagParams) -> Result> { Ok(Box::new(OpenOcdJtagChain::new( - match self.openocd_adapter_config { + &match self.openocd_adapter_config { Some(ref path) => std::fs::read_to_string(path)?, None => String::new(), }, diff --git a/sw/host/opentitanlib/src/transport/hyperdebug/mod.rs b/sw/host/opentitanlib/src/transport/hyperdebug/mod.rs index 90e6c71168cb2..422096949d1e8 100644 --- a/sw/host/opentitanlib/src/transport/hyperdebug/mod.rs +++ b/sw/host/opentitanlib/src/transport/hyperdebug/mod.rs @@ -21,7 +21,7 @@ use std::rc::Rc; use crate::io::gpio::{GpioMonitoring, GpioPin}; use crate::io::i2c::Bus; -use crate::io::jtag::{Jtag, JtagParams}; +use crate::io::jtag::{JtagChain, JtagParams}; use crate::io::spi::Target; use crate::io::uart::Uart; use crate::transport::chip_whisperer::board::Board; @@ -623,7 +623,7 @@ impl Transport for Hyperdebug { } } - fn jtag(&self, opts: &JtagParams) -> Result> { + fn jtag(&self, opts: &JtagParams) -> Result> { ensure!( self.cmsis_interface.is_some(), TransportError::InvalidInterface(TransportInterfaceType::Jtag), @@ -631,8 +631,8 @@ impl Transport for Hyperdebug { // Tell OpenOCD to use its CMSIS-DAP driver, and to connect to the same exact USB // HyperDebug device that we are. let usb_device = self.inner.usb_device.borrow(); - let new_jtag: Box = Box::new(OpenOcdJtagChain::new( - format!( + let new_jtag = Box::new(OpenOcdJtagChain::new( + &format!( "{}; cmsis_dap_vid_pid 0x{:04x} 0x{:04x}; adapter serial \"{}\";", include_str!(env!("openocd_cmsis_dap_adapter_cfg")), usb_device.get_vendor_id(), diff --git a/sw/host/opentitanlib/src/transport/mod.rs b/sw/host/opentitanlib/src/transport/mod.rs index c56f649ac8968..959305884a6ec 100644 --- a/sw/host/opentitanlib/src/transport/mod.rs +++ b/sw/host/opentitanlib/src/transport/mod.rs @@ -14,7 +14,7 @@ use crate::bootstrap::BootstrapOptions; use crate::io::emu::Emulator; use crate::io::gpio::{GpioMonitoring, GpioPin}; use crate::io::i2c::Bus; -use crate::io::jtag::{Jtag, JtagParams}; +use crate::io::jtag::{JtagChain, JtagParams}; use crate::io::nonblocking_help::{NoNonblockingHelp, NonblockingHelp}; use crate::io::spi::Target; use crate::io::uart::Uart; @@ -111,8 +111,8 @@ pub trait Transport { Ok(()) } - /// Returns a [`Jtag`] implementation. - fn jtag(&self, _opts: &JtagParams) -> Result> { + /// Returns a [`JtagChain`] implementation. + fn jtag(&self, _opts: &JtagParams) -> Result> { Err(TransportError::InvalidInterface(TransportInterfaceType::Jtag).into()) } /// Returns a SPI [`Target`] implementation. diff --git a/sw/host/opentitanlib/src/util/openocd.rs b/sw/host/opentitanlib/src/util/openocd.rs index bfcb3c3af4469..18b9613607149 100644 --- a/sw/host/opentitanlib/src/util/openocd.rs +++ b/sw/host/opentitanlib/src/util/openocd.rs @@ -18,7 +18,7 @@ use thiserror::Error; use crate::dif::lc_ctrl::LcCtrlReg; use crate::impl_serializable_error; -use crate::io::jtag::{Jtag, JtagError, JtagParams, JtagTap, RiscvReg}; +use crate::io::jtag::{Jtag, JtagChain, JtagError, JtagParams, JtagTap, RiscvReg}; use crate::util::parse_int::ParseInt; use crate::util::printer; @@ -208,14 +208,8 @@ impl OpenOcd { /// An JTAG interface driver over OpenOCD. pub struct OpenOcdJtagChain { - /// Connection command for the particular adapter. - adapter_command: String, - /// JTAG parameters. - opts: JtagParams, /// OpenOCD server instance. - openocd_server: Option, - /// JTAG TAP OpenOCD is connected to. - jtag_tap: Option, + openocd: OpenOcd, } /// Errors related to the OpenOCD server. @@ -231,73 +225,48 @@ pub enum OpenOcdError { impl_serializable_error!(OpenOcdError); impl OpenOcdJtagChain { - /// Create a new OpenOcdJtagChain with the given JTAG options without starting OpenOCD. - pub fn new(adapter_command: String, opts: &JtagParams) -> Result { - Ok(OpenOcdJtagChain { - adapter_command, - opts: opts.clone(), - openocd_server: Default::default(), - jtag_tap: Default::default(), - }) - } + /// Start OpenOCD with given JTAG options but do not connect any TAP. + pub fn new(adapter_command: &str, opts: &JtagParams) -> Result { + let mut openocd = OpenOcd::spawn(&opts.openocd)?; - /// Spawn the OpenOCD server and connect to it. - fn start(&mut self, tap: JtagTap) -> Result<()> { - // Check if a server was already started. - if self.openocd_server.is_some() { - bail!("OpenOCD server already running"); - } - - let mut openocd = OpenOcd::spawn(&self.opts.openocd)?; - - openocd.execute(&self.adapter_command)?; - openocd.execute(&format!("adapter speed {}", self.opts.adapter_speed_khz))?; + openocd.execute(adapter_command)?; + openocd.execute(&format!("adapter speed {}", opts.adapter_speed_khz))?; openocd.execute("transport select jtag")?; openocd.execute("scan_chain")?; + Ok(OpenOcdJtagChain { openocd }) + } +} + +impl JtagChain for OpenOcdJtagChain { + fn connect(mut self: Box, tap: JtagTap) -> Result> { // Pass through the config for the chosen TAP. let target = match tap { JtagTap::RiscvTap => include_str!(env!("openocd_riscv_target_cfg")), JtagTap::LcTap => include_str!(env!("openocd_lc_target_cfg")), }; - self.jtag_tap = Some(tap); - openocd.execute(target)?; - - // Finish initialisation. - openocd.execute("init")?; - - self.openocd_server = Some(openocd); + self.openocd.execute(target)?; + self.openocd.execute("init")?; - Ok(()) + Ok(Box::new(OpenOcdJtagTap { + openocd: self.openocd, + jtag_tap: tap, + })) } +} - fn stop(&mut self) -> Result<()> { - log::info!("Stopping OpenOCD..."); - - let Some(server) = self.openocd_server.take() else { - // OpenOCD wasn't started, do nothing. - return Ok(()); - }; - - // Cleanup TAP selection. - self.jtag_tap = None; - - server.shutdown()?; - - Ok(()) - } +/// An JTAG interface driver over OpenOCD. +pub struct OpenOcdJtagTap { + /// OpenOCD server instance. + openocd: OpenOcd, + /// JTAG TAP OpenOCD is connected to. + jtag_tap: JtagTap, +} +impl OpenOcdJtagTap { /// Send a TCL command to OpenOCD and wait for its response. fn send_tcl_cmd(&mut self, cmd: &str) -> Result { - // Take the server. The server will not be replaced on communication - // errors, causing future commands to also fail. - let Some(mut server) = self.openocd_server.take() else { - return Err(OpenOcdError::OpenOcdNotRunning.into()); - }; - - let ret = server.execute(cmd)?; - self.openocd_server = Some(server); - Ok(ret) + self.openocd.execute(cmd) } fn read_memory_impl(&mut self, addr: u32, buf: &mut [T]) -> Result { @@ -377,23 +346,19 @@ impl OpenOcdJtagChain { } } -impl Jtag for OpenOcdJtagChain { - fn connect(&mut self, tap: JtagTap) -> Result<()> { - self.start(tap) - } - - fn disconnect(mut self: Box) -> Result<()> { - self.stop() +impl Jtag for OpenOcdJtagTap { + fn disconnect(self: Box) -> Result<()> { + self.openocd.shutdown() } - fn tap(&self) -> Option { + fn tap(&self) -> JtagTap { self.jtag_tap } fn read_lc_ctrl_reg(&mut self, reg: &LcCtrlReg) -> Result { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::LcTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::LcTap), + JtagError::Tap(self.jtag_tap) ); let reg_offset = reg.word_offset(); let cmd = format!("riscv dmi_read 0x{reg_offset:x}"); @@ -408,8 +373,8 @@ impl Jtag for OpenOcdJtagChain { fn write_lc_ctrl_reg(&mut self, reg: &LcCtrlReg, value: u32) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::LcTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::LcTap), + JtagError::Tap(self.jtag_tap) ); let reg_offset = reg.word_offset(); let cmd = format!("riscv dmi_write 0x{reg_offset:x} 0x{value:x}"); @@ -424,40 +389,40 @@ impl Jtag for OpenOcdJtagChain { fn read_memory(&mut self, addr: u32, buf: &mut [u8]) -> Result { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); self.read_memory_impl(addr, buf) } fn read_memory32(&mut self, addr: u32, buf: &mut [u32]) -> Result { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); self.read_memory_impl(addr, buf) } fn write_memory(&mut self, addr: u32, buf: &[u8]) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); self.write_memory_impl(addr, buf) } fn write_memory32(&mut self, addr: u32, buf: &[u32]) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); self.write_memory_impl(addr, buf) } fn halt(&mut self) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); let response = self.send_tcl_cmd("halt")?; if !response.is_empty() { @@ -469,8 +434,8 @@ impl Jtag for OpenOcdJtagChain { fn wait_halt(&mut self, timeout: Duration) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); let cmd = format!("wait_halt {}", timeout.as_millis()); let response = self.send_tcl_cmd(cmd.as_str())?; @@ -482,8 +447,8 @@ impl Jtag for OpenOcdJtagChain { fn resume(&mut self) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); let response = self.send_tcl_cmd("resume")?; if !response.is_empty() { @@ -495,8 +460,8 @@ impl Jtag for OpenOcdJtagChain { fn resume_at(&mut self, addr: u32) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); let cmd = format!("resume 0x{:x}", addr); let response = self.send_tcl_cmd(&cmd)?; @@ -509,8 +474,8 @@ impl Jtag for OpenOcdJtagChain { fn reset(&mut self, run: bool) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); let cmd = format!("reset {}", if run { "run" } else { "halt" }); let response = self.send_tcl_cmd(&cmd)?; @@ -523,8 +488,8 @@ impl Jtag for OpenOcdJtagChain { fn step(&mut self) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); let response = self.send_tcl_cmd("step")?; if !response.is_empty() { @@ -536,8 +501,8 @@ impl Jtag for OpenOcdJtagChain { fn step_at(&mut self, addr: u32) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); let cmd = format!("step 0x{:x}", addr); let response = self.send_tcl_cmd(&cmd)?; @@ -550,16 +515,16 @@ impl Jtag for OpenOcdJtagChain { fn read_riscv_reg(&mut self, reg: &RiscvReg) -> Result { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); self.read_register::(reg.name(), true) } fn write_riscv_reg(&mut self, reg: &RiscvReg, val: u32) -> Result<()> { ensure!( - matches!(self.jtag_tap.unwrap(), JtagTap::RiscvTap), - JtagError::Tap(self.jtag_tap.unwrap()) + matches!(self.jtag_tap, JtagTap::RiscvTap), + JtagError::Tap(self.jtag_tap) ); self.write_register(reg.name(), val) } diff --git a/sw/host/opentitantool/src/command/lc.rs b/sw/host/opentitantool/src/command/lc.rs index b50c499cf883b..b2c98dd3c9c71 100644 --- a/sw/host/opentitantool/src/command/lc.rs +++ b/sw/host/opentitantool/src/command/lc.rs @@ -78,8 +78,10 @@ impl CommandDispatch for LcStateRead { transport.reset_target(self.reset_delay, true)?; // Spawn an OpenOCD process and connect to the LC JTAG TAP. - let mut jtag = self.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = self + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Read and decode the LC state. let lc_state = @@ -116,8 +118,10 @@ impl CommandDispatch for RawUnlock { transport.reset_target(self.reset_delay, true)?; // Spawn an OpenOCD process and connect to the LC JTAG TAP. - let mut jtag = self.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = self + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; check_lc_state_is_raw(&mut *jtag)?; let token_words = parse_unlock_token_str(self.token.as_str())?; @@ -134,8 +138,10 @@ impl CommandDispatch for RawUnlock { /*reset_tap_straps=*/ Some(JtagTap::LcTap), )?; - jtag = self.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = self + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Read and decode the LC state. let lc_state = @@ -184,8 +190,10 @@ impl CommandDispatch for Status { transport.reset_target(self.reset_delay, true)?; // Spawn an OpenOCD process, connect to the LC JTAG TAP, read register, and shutdown OpenOCD. - let mut jtag = self.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = self + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; let status = jtag.read_lc_ctrl_reg(&LcCtrlReg::Status)?; jtag.disconnect()?; @@ -233,8 +241,10 @@ impl CommandDispatch for TransitionCount { transport.reset_target(self.reset_delay, true)?; // Spawn an OpenOCD process, connect to the LC JTAG TAP, read register, and shutdown OpenOCD. - let mut jtag = self.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = self + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; let transition_count = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcTransitionCnt)?; jtag.disconnect()?; @@ -268,8 +278,10 @@ impl CommandDispatch for VolatileRawUnlock { transport.reset_target(self.reset_delay, true)?; // Spawn an OpenOCD process and connect to the LC JTAG TAP. - let mut jtag = self.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = self + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; check_lc_state_is_raw(&mut *jtag)?; let token_words = parse_unlock_token_str(self.token.as_str())?; @@ -286,8 +298,10 @@ impl CommandDispatch for VolatileRawUnlock { &self.jtag_params, )?; - jtag = self.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = self + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Read and decode the LC state. let lc_state = diff --git a/sw/host/provisioning/cp_lib/src/lib.rs b/sw/host/provisioning/cp_lib/src/lib.rs index 578699a225e01..f9d6a4b1d0f48 100644 --- a/sw/host/provisioning/cp_lib/src/lib.rs +++ b/sw/host/provisioning/cp_lib/src/lib.rs @@ -70,8 +70,9 @@ pub fn unlock_raw( .context("failed to reset")?; // Connect to the LC TAP via JTAG. - let mut jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap) + let mut jtag = jtag_params + .create(transport)? + .connect(JtagTap::LcTap) .context("failed to connect to LC TAP over JTAG")?; // Provide the `RAW_UNLOCK` token @@ -92,8 +93,7 @@ pub fn unlock_raw( ) .context("failed to transition to TEST_UNLOCKED0.")?; - jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = jtag_params.create(transport)?.connect(JtagTap::LcTap)?; // Check that LC state is `TEST_UNLOCKED0`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; @@ -115,8 +115,7 @@ pub fn run_sram_cp_provision( // Set CPU TAP straps, reset, and connect to the JTAG interface. transport.pin_strapping("PINMUX_TAP_RISCV")?.apply()?; transport.reset_target(reset_delay, true)?; - let mut jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = jtag_params.create(transport)?.connect(JtagTap::RiscvTap)?; // Reset and halt the CPU to ensure we are in a known state, and clear out any ROM messages // printed over the console. @@ -162,8 +161,9 @@ pub fn reset_and_lock( .context("failed to reset")?; // Connect to the LC TAP via JTAG. - let mut jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap) + let mut jtag = jtag_params + .create(transport)? + .connect(JtagTap::LcTap) .context("failed to connect to LC TAP over JTAG")?; // CPU execution is not enabled in TEST_LOCKED0 so we can safely reconnect to the LC TAP @@ -180,8 +180,7 @@ pub fn reset_and_lock( ) .context("failed to transition to TEST_LOCKED0.")?; - jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = jtag_params.create(transport)?.connect(JtagTap::LcTap)?; // Check that LC state is `TEST_LOCKED0`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; diff --git a/sw/host/provisioning/ft_lib/src/lib.rs b/sw/host/provisioning/ft_lib/src/lib.rs index 6b7e0255accac..ef5237fcfa01d 100644 --- a/sw/host/provisioning/ft_lib/src/lib.rs +++ b/sw/host/provisioning/ft_lib/src/lib.rs @@ -32,8 +32,7 @@ pub fn test_unlock( // Connect to LC TAP. transport.pin_strapping("PINMUX_TAP_LC")?.apply()?; transport.reset_target(reset_delay, true)?; - let mut jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = jtag_params.create(transport)?.connect(JtagTap::LcTap)?; // Check that LC state is currently `TEST_LOCKED0`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; @@ -52,8 +51,7 @@ pub fn test_unlock( /*reset_tap_straps=*/ Some(JtagTap::LcTap), )?; - jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = jtag_params.create(transport)?.connect(JtagTap::LcTap)?; // Check that LC state has transitioned to `TestUnlocked1`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; @@ -75,8 +73,7 @@ pub fn run_sram_ft_individualize( // Set CPU TAP straps, reset, and connect to the JTAG interface. transport.pin_strapping("PINMUX_TAP_RISCV")?.apply()?; transport.reset_target(reset_delay, true)?; - let mut jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = jtag_params.create(transport)?.connect(JtagTap::RiscvTap)?; // Reset and halt the CPU to ensure we are in a known state, and clear out any ROM messages // printed over the console. @@ -116,8 +113,7 @@ pub fn test_exit( // transition to a mission mode state. We do not need to reset the chip to switch TAPs because // TAP straps are continuously sampled in TEST_UNLOCKED* LC state. transport.pin_strapping("PINMUX_TAP_LC")?.apply()?; - let mut jtag = jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = jtag_params.create(transport)?.connect(JtagTap::LcTap)?; // Check that LC state is currently `TEST_UNLOCKED1`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; diff --git a/sw/host/tests/chip/jtag/src/openocd_test.rs b/sw/host/tests/chip/jtag/src/openocd_test.rs index f3eef04498526..75fef46e18cdb 100644 --- a/sw/host/tests/chip/jtag/src/openocd_test.rs +++ b/sw/host/tests/chip/jtag/src/openocd_test.rs @@ -59,8 +59,11 @@ fn test_openocd(opts: &Opts, transport: &TransportWrapper) -> Result<()> { opts.init.bootstrap.options.reset_delay, )?; - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap)?; jtag.halt()?; // Definitions for hardware registers let lc_ctrl_base_addr = top_earlgrey::LC_CTRL_BASE_ADDR as u32; @@ -184,8 +187,11 @@ fn test_openocd(opts: &Opts, transport: &TransportWrapper) -> Result<()> { opts.init.bootstrap.options.reset_delay, )?; - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Test reads by checking the LC_STATE register assert_eq!( diff --git a/sw/host/tests/chip/jtag/src/sram_load.rs b/sw/host/tests/chip/jtag/src/sram_load.rs index 1f0090af8ed26..9f4d1a9342750 100644 --- a/sw/host/tests/chip/jtag/src/sram_load.rs +++ b/sw/host/tests/chip/jtag/src/sram_load.rs @@ -34,9 +34,12 @@ fn test_sram_load(opts: &Opts, transport: &TransportWrapper) -> Result<()> { transport.pin_strapping("PINMUX_TAP_RISCV")?.apply()?; transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; - let mut jtag = opts.init.jtag_params.create(transport)?; log::info!("Connecting to RISC-V TAP"); - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap)?; log::info!("Halting core"); jtag.halt()?; diff --git a/sw/host/tests/manuf/manuf_cp_ast_test_execution/src/main.rs b/sw/host/tests/manuf/manuf_cp_ast_test_execution/src/main.rs index 5508157e6133f..a5ef0f4c59395 100644 --- a/sw/host/tests/manuf/manuf_cp_ast_test_execution/src/main.rs +++ b/sw/host/tests/manuf/manuf_cp_ast_test_execution/src/main.rs @@ -50,9 +50,12 @@ fn connect_riscv_jtag<'t>( .reset_target(opts.init.bootstrap.options.reset_delay, true) .context("failed to reset")?; - let mut jtag = opts.init.jtag_params.create(transport)?; log::info!("Connecting to RISC-V TAP"); - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap)?; // This test is supposed to be run with ROM execution disabled but just in case // we reset the core to make sure we are in a known state. This disables the watchdog. diff --git a/sw/host/tests/manuf/manuf_cp_device_info_flash_wr/src/main.rs b/sw/host/tests/manuf/manuf_cp_device_info_flash_wr/src/main.rs index 4d4bec383fc17..5ddd9d8e493d3 100644 --- a/sw/host/tests/manuf/manuf_cp_device_info_flash_wr/src/main.rs +++ b/sw/host/tests/manuf/manuf_cp_device_info_flash_wr/src/main.rs @@ -41,8 +41,11 @@ fn manuf_cp_device_info_flash_wr(opts: &Opts, transport: &TransportWrapper) -> R // Set CPU TAP straps, reset, and connect to the JTAG interface. transport.pin_strapping("PINMUX_TAP_RISCV")?.apply()?; transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap)?; // Reset and halt the CPU to ensure we are in a known state, and clear out any ROM messages // printed over the console. @@ -75,8 +78,11 @@ fn manuf_cp_device_info_flash_wr(opts: &Opts, transport: &TransportWrapper) -> R jtag.disconnect()?; transport.pin_strapping("PINMUX_TAP_RISCV")?.remove()?; transport.pin_strapping("PINMUX_TAP_LC")?.apply()?; - jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Issue an LC transition. const TEST_EXIT_TOKEN: [u32; 4] = [0x11111111, 0x11111111, 0x11111111, 0x11111111]; diff --git a/sw/host/tests/manuf/manuf_cp_test_lock/src/main.rs b/sw/host/tests/manuf/manuf_cp_test_lock/src/main.rs index f490c1e087592..230eee4f1e631 100644 --- a/sw/host/tests/manuf/manuf_cp_test_lock/src/main.rs +++ b/sw/host/tests/manuf/manuf_cp_test_lock/src/main.rs @@ -110,8 +110,11 @@ fn test_lock(opts: &Opts, transport: &TransportWrapper) -> anyhow::Result<()> { ) .context("failed to trigger transition to TEST_LOCKED0")?; - jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check that LC state has transitioned to `TEST_LOCKED0`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; @@ -144,8 +147,11 @@ fn test_unlock(opts: &Opts, transport: &TransportWrapper) -> anyhow::Result<()> ) .context("failed to trigger transition to TEST_UNLOCKED1")?; - jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check that LC state has transitioned to `TEST_UNLOCKED0`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; @@ -178,8 +184,11 @@ fn reset_to_tap<'t>( .reset_target(opts.init.bootstrap.options.reset_delay, true) .context("failed to reset")?; - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(tap) + let jtag = opts + .init + .jtag_params + .create(transport)? + .connect(tap) .with_context(|| format!("failed to connect to {tap:?} over JTAG"))?; Ok(jtag) diff --git a/sw/host/tests/manuf/manuf_cp_unlock_raw/src/main.rs b/sw/host/tests/manuf/manuf_cp_unlock_raw/src/main.rs index 7c5f49224075f..d11ee85ac413f 100644 --- a/sw/host/tests/manuf/manuf_cp_unlock_raw/src/main.rs +++ b/sw/host/tests/manuf/manuf_cp_unlock_raw/src/main.rs @@ -34,8 +34,11 @@ fn manuf_cp_unlock_raw(opts: &Opts, transport: &TransportWrapper) -> Result<()> .context("failed to reset")?; // Connect to the LC TAP via JTAG. - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap) + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap) .context("failed to connect to LC TAP over JTAG")?; // Provide the `RAW_UNLOCK` token @@ -55,8 +58,11 @@ fn manuf_cp_unlock_raw(opts: &Opts, transport: &TransportWrapper) -> Result<()> ) .context("failed to transition to TEST_UNLOCKED0")?; - jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check that LC state is `TEST_UNLOCKED0`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; diff --git a/sw/host/tests/manuf/manuf_cp_volatile_unlock_raw/src/main.rs b/sw/host/tests/manuf/manuf_cp_volatile_unlock_raw/src/main.rs index ef19c59772ced..bc44c027b4e56 100644 --- a/sw/host/tests/manuf/manuf_cp_volatile_unlock_raw/src/main.rs +++ b/sw/host/tests/manuf/manuf_cp_volatile_unlock_raw/src/main.rs @@ -40,8 +40,11 @@ fn volatile_raw_unlock_with_reconnection_to_lc_tap( .context("failed to reset")?; // Connect to the LC TAP via JTAG. - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap) + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap) .context("failed to connect to LC TAP over JTAG")?; // ROM execution is not enabled in the OTP so we can safely reconnect to the LC TAP after @@ -82,8 +85,11 @@ fn volatile_raw_unlock_with_reconnection_to_rv_tap( .context("failed to reset")?; // Connect to the LC TAP via JTAG. - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap) + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap) .context("failed to connect to LC TAP over JTAG")?; // ROM execution is not enabled in the OTP so we can safely reconnect to the LC TAP after diff --git a/sw/host/tests/manuf/manuf_cp_yield_test/src/main.rs b/sw/host/tests/manuf/manuf_cp_yield_test/src/main.rs index 4c0f06a122a5b..8d4b49ba6d36b 100644 --- a/sw/host/tests/manuf/manuf_cp_yield_test/src/main.rs +++ b/sw/host/tests/manuf/manuf_cp_yield_test/src/main.rs @@ -43,8 +43,11 @@ fn manuf_cp_yield_test(opts: &Opts, transport: &TransportWrapper) -> Result<()> .apply() .context("failed to apply RISCV TAP strapping")?; transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap) + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap) .context("failed to connect to RISCV TAP over JTAG")?; ExternalClock::enable(&mut *jtag, ClockSpeed::High) @@ -75,8 +78,11 @@ fn manuf_cp_yield_test(opts: &Opts, transport: &TransportWrapper) -> Result<()> .pin_strapping("PINMUX_TAP_LC")? .apply() .context("failed to apply LC TAP strapping")?; - jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap) + jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap) .context("failed to connect to LC TAP over JTAG")?; // Read and write LC state register to verify connection. diff --git a/sw/host/tests/manuf/manuf_scrap/src/main.rs b/sw/host/tests/manuf/manuf_scrap/src/main.rs index 0a80ce35134df..a307e44db1a3c 100644 --- a/sw/host/tests/manuf/manuf_scrap/src/main.rs +++ b/sw/host/tests/manuf/manuf_scrap/src/main.rs @@ -30,8 +30,11 @@ fn manuf_scrap(opts: &Opts, transport: &TransportWrapper) -> Result<()> { // Reset the chip, select the LC TAP, and connect to it. transport.pin_strapping("PINMUX_TAP_LC")?.apply()?; transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check the initial LC state. assert_eq!( @@ -52,8 +55,11 @@ fn manuf_scrap(opts: &Opts, transport: &TransportWrapper) -> Result<()> { Some(JtagTap::LcTap), )?; - jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check the LC state is SCRAP. assert_eq!( diff --git a/sw/host/tests/manuf/manuf_sram_program_crc_check/src/main.rs b/sw/host/tests/manuf/manuf_sram_program_crc_check/src/main.rs index 89224236670ce..783c7acb19b85 100644 --- a/sw/host/tests/manuf/manuf_sram_program_crc_check/src/main.rs +++ b/sw/host/tests/manuf/manuf_sram_program_crc_check/src/main.rs @@ -35,9 +35,12 @@ fn test_sram_load(opts: &Opts, transport: &TransportWrapper, corrupt: bool) -> R transport.pin_strapping("PINMUX_TAP_RISCV")?.apply()?; transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; - let mut jtag = opts.init.jtag_params.create(transport)?; log::info!("Connecting to RISC-V TAP"); - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap)?; log::info!("Halting core"); jtag.halt()?; diff --git a/sw/host/tests/manuf/otp_ctrl/src/main.rs b/sw/host/tests/manuf/otp_ctrl/src/main.rs index 2743791b61ce8..1226459f69d27 100644 --- a/sw/host/tests/manuf/otp_ctrl/src/main.rs +++ b/sw/host/tests/manuf/otp_ctrl/src/main.rs @@ -45,8 +45,11 @@ fn program_readback(opts: &Opts, transport: &TransportWrapper) -> anyhow::Result .context("failed to reset")?; // Connect to the RISCV TAP via JTAG. - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap) + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap) .context("failed to connect to RISCV TAP over JTAG")?; // Program and then read back `MANUF_STATE`. @@ -77,8 +80,11 @@ fn lock_partition(opts: &Opts, transport: &TransportWrapper) -> anyhow::Result<( .context("failed to reset")?; // Connect to the RISCV TAP via JTAG. - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap) + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap) .context("failed to connect to RISCV TAP over JTAG")?; // Read the HW_CFG partition's digest, which should be 0 (unlocked): diff --git a/sw/host/tests/manuf/personalize/src/main.rs b/sw/host/tests/manuf/personalize/src/main.rs index f32269c656e68..5238781a2a3f4 100644 --- a/sw/host/tests/manuf/personalize/src/main.rs +++ b/sw/host/tests/manuf/personalize/src/main.rs @@ -122,8 +122,11 @@ fn rma_unlock_token_export(opts: &Opts, transport: &TransportWrapper) -> Result< } // Connect to JTAG LC TAP. - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check the current LC state is Dev or Prod. // We must wait for the lc_ctrl to initialize before the LC state is exposed. @@ -155,8 +158,11 @@ fn rma_unlock_token_export(opts: &Opts, transport: &TransportWrapper) -> Result< Some(JtagTap::LcTap), )?; - jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check the LC state is RMA. // We must wait for the lc_ctrl to initialize before the LC state is exposed. diff --git a/sw/host/tests/manuf/provisioning/cp_test/src/main.rs b/sw/host/tests/manuf/provisioning/cp_test/src/main.rs index d65afa4f9edb0..ecbcc1dc32a2d 100644 --- a/sw/host/tests/manuf/provisioning/cp_test/src/main.rs +++ b/sw/host/tests/manuf/provisioning/cp_test/src/main.rs @@ -80,8 +80,11 @@ fn test_unlock( // Connect to LC TAP. transport.pin_strapping("PINMUX_TAP_LC")?.apply()?; transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check that LC state is currently `TEST_LOCKED0`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; @@ -105,8 +108,11 @@ fn test_unlock( /*reset_tap_straps=*/ Some(JtagTap::LcTap), )?; - jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap)?; + jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap)?; // Check that LC state has transitioned to `TestUnlocked1`. let state = jtag.read_lc_ctrl_reg(&LcCtrlReg::LcState)?; @@ -133,8 +139,11 @@ fn check_cp_provisioning( transport.reset_target(opts.init.bootstrap.options.reset_delay, true)?; // Connect to the RISCV TAP via JTAG. - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap)?; // Reset and halt the CPU to ensure we are in a known state, and clear out any ROM messages // printed over the console. diff --git a/sw/host/tests/rom/e2e_bootstrap_rma/src/main.rs b/sw/host/tests/rom/e2e_bootstrap_rma/src/main.rs index 252f1c7f9058b..7bdf46e0a02b1 100644 --- a/sw/host/tests/rom/e2e_bootstrap_rma/src/main.rs +++ b/sw/host/tests/rom/e2e_bootstrap_rma/src/main.rs @@ -131,8 +131,11 @@ fn test_rma_command(opts: &Opts, transport: &TransportWrapper) -> anyhow::Result log::info!("Connecting to JTAG interface"); - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::LcTap) + let mut jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::LcTap) .context("failed to connect to JTAG")?; // Wait for the lifecycle controller to enter the `READY` state from diff --git a/sw/host/tests/rom/e2e_openocd_debug_test/src/main.rs b/sw/host/tests/rom/e2e_openocd_debug_test/src/main.rs index e13dd139357e4..a12c3682dad5e 100644 --- a/sw/host/tests/rom/e2e_openocd_debug_test/src/main.rs +++ b/sw/host/tests/rom/e2e_openocd_debug_test/src/main.rs @@ -151,8 +151,11 @@ fn asm_watchdog_bite<'t>( // Disconnect JTAG, wait for a sufficiently long period to allow reset to complete and reconnect. dbg.disconnect()?; std::thread::sleep(BP_TIMEOUT); - let mut jtag = opts.init.jtag_params.create(transport)?; - jtag.connect(JtagTap::RiscvTap)?; + let jtag = opts + .init + .jtag_params + .create(transport)? + .connect(JtagTap::RiscvTap)?; dbg = sym.attach(jtag); // Check that the execution has stuck after reset at the given known location. @@ -480,8 +483,11 @@ fn main() -> Result<()> { opts.init.bootstrap.options.reset_delay, )?; - let mut jtag = opts.init.jtag_params.create(&transport)?; - jtag.connect(JtagTap::RiscvTap)?; + let mut jtag = opts + .init + .jtag_params + .create(&transport)? + .connect(JtagTap::RiscvTap)?; let result = jtag.reset(false); assert_eq!(result.is_err(), opts.expect_fail); if opts.expect_fail {