From 2c002c78dbeafcea96ca799e76f2e81c6f1eb361 Mon Sep 17 00:00:00 2001 From: "Jonas K." Date: Mon, 6 May 2024 12:42:34 +0200 Subject: [PATCH 1/5] Move sources to FABulous subfolder In preparation for packaging FABulous with setuptools, we migrate FABulous to a so-called "flat-layout". This means we add a subfolder FABulous and move all code sources there. Signed-off-by: Jonas K. --- FABulous.py => FABulous/FABulous.py | 0 FABulous_API.py => FABulous/FABulous_API.py | 0 {fabric_cad => FABulous/fabric_cad}/README.md | 0 {fabric_cad => FABulous/fabric_cad}/bit_gen.py | 0 {fabric_cad => FABulous/fabric_cad}/synth/cells_map.v | 0 {fabric_cad => FABulous/fabric_cad}/synth/cells_map_ff.v | 0 {fabric_cad => FABulous/fabric_cad}/synth/ff_map.v | 0 {fabric_cad => FABulous/fabric_cad}/synth/latches_map.v | 0 {fabric_cad => FABulous/fabric_cad}/synth/prims.v | 0 {fabric_cad => FABulous/fabric_cad}/synth/prims_ff.v | 0 {fabric_cad => FABulous/fabric_cad}/synth/synth_fabulous.tcl | 0 .../fabric_cad}/synth/synth_fabulous_dffesr.tcl | 0 .../fabric_files}/FABulous_project_template_verilog/FABulous.tcl | 0 .../FABulous_project_template_verilog/Fabric/BlockRAM_1KB.v | 0 .../FABulous_project_template_verilog/Fabric/ConfigFSM.v | 0 .../FABulous_project_template_verilog/Fabric/Frame_Data_Reg.v | 0 .../FABulous_project_template_verilog/Fabric/Frame_Select.v | 0 .../FABulous_project_template_verilog/Fabric/bitbang.v | 0 .../FABulous_project_template_verilog/Fabric/config_UART.v | 0 .../FABulous_project_template_verilog/Fabric/eFPGA_Config.v | 0 .../FABulous_project_template_verilog/Fabric/models_pack.v | 0 .../FABulous_project_template_verilog/Test/.gitignore | 0 .../FABulous_project_template_verilog/Test/README.md | 0 .../FABulous_project_template_verilog/Test/build_test_design.sh | 0 .../FABulous_project_template_verilog/Test/fabulous_tb.v | 0 .../FABulous_project_template_verilog/Test/makehex.py | 0 .../FABulous_project_template_verilog/Test/run_emulation_sim.sh | 0 .../FABulous_project_template_verilog/Test/run_simulation.sh | 0 .../Test/sequential_16bit_en_tb.v | 0 .../FABulous_project_template_verilog/Test/test_design/.gitignore | 0 .../FABulous_project_template_verilog/Test/test_design/counter.v | 0 .../Test/test_design/right_shift.v | 0 .../Test/test_design/top_wrapper.v | 0 .../FABulous_project_template_verilog/Tile/DSP/DSP.csv | 0 .../Tile/DSP/DSP_bot/DSP_bot.csv | 0 .../Tile/DSP/DSP_bot/DSP_bot_switch_matrix.list | 0 .../FABulous_project_template_verilog/Tile/DSP/DSP_bot/MULADD.v | 0 .../Tile/DSP/DSP_top/DSP_top.csv | 0 .../Tile/DSP/DSP_top/DSP_top_switch_matrix.list | 0 .../FABulous_project_template_verilog/Tile/LUT4AB/LUT4AB.csv | 0 .../Tile/LUT4AB/LUT4AB_ConfigMem.csv | 0 .../Tile/LUT4AB/LUT4AB_switch_matrix.list | 0 .../Tile/LUT4AB/LUT4c_frame_config_dffesr.v | 0 .../Tile/LUT4AB/MUX8LUT_frame_config_mux.v | 0 .../Tile/N_term_DSP/N_term_DSP.csv | 0 .../Tile/N_term_DSP/N_term_DSP_switch_matrix.list | 0 .../Tile/N_term_RAM_IO/N_term_RAM_IO.csv | 0 .../Tile/N_term_RAM_IO/N_term_RAM_IO_switch_matrix.list | 0 .../Tile/N_term_single/N_term_single.csv | 0 .../Tile/N_term_single/N_term_single_switch_matrix.list | 0 .../Tile/N_term_single2/N_term_single2.csv | 0 .../Tile/N_term_single2/N_term_single2_switch_matrix.list | 0 .../FABulous_project_template_verilog/Tile/RAM_IO/Config_access.v | 0 .../Tile/RAM_IO/InPass4_frame_config_mux.v | 0 .../Tile/RAM_IO/OutPass4_frame_config_mux.v | 0 .../FABulous_project_template_verilog/Tile/RAM_IO/RAM_IO.csv | 0 .../Tile/RAM_IO/RAM_IO_switch_matrix.list | 0 .../FABulous_project_template_verilog/Tile/RegFile/RegFile.csv | 0 .../FABulous_project_template_verilog/Tile/RegFile/RegFile_32x4.v | 0 .../Tile/RegFile/RegFile_switch_matrix.list | 0 .../Tile/S_term_DSP/S_term_DSP.csv | 0 .../Tile/S_term_DSP/S_term_DSP_switch_matrix.list | 0 .../Tile/S_term_RAM_IO/S_term_RAM_IO.csv | 0 .../Tile/S_term_RAM_IO/S_term_RAM_IO_switch_matrix.list | 0 .../Tile/S_term_single/S_term_single.csv | 0 .../Tile/S_term_single/S_term_single_switch_matrix.list | 0 .../Tile/S_term_single2/S_term_single2.csv | 0 .../Tile/S_term_single2/S_term_single2_switch_matrix.list | 0 .../FABulous_project_template_verilog/Tile/W_IO/Config_access.v | 0 .../Tile/W_IO/IO_1_bidirectional_frame_config_pass.v | 0 .../FABulous_project_template_verilog/Tile/W_IO/W_IO.csv | 0 .../Tile/W_IO/W_IO_switch_matrix.list | 0 .../FABulous_project_template_verilog/custom_info.xml | 0 .../fabric_files}/FABulous_project_template_verilog/debug.list | 0 .../fabric_files}/FABulous_project_template_verilog/fabric.csv | 0 .../user_design/sequential_16bit_en.v | 0 .../FABulous_project_template_verilog/user_design/top_wrapper.v | 0 .../FABulous_project_template_vhdl/Fabric/BlockRAM_1KB.vhdl | 0 .../FABulous_project_template_vhdl/Fabric/ConfigFSM.vhdl | 0 .../FABulous_project_template_vhdl/Fabric/Frame_Data_Reg.vhdl | 0 .../FABulous_project_template_vhdl/Fabric/Frame_Select.vhdl | 0 .../FABulous_project_template_vhdl/Fabric/bitbang.vhdl | 0 .../FABulous_project_template_vhdl/Fabric/config_UART.vhdl | 0 .../FABulous_project_template_vhdl/Fabric/eFPGA_Config.vhdl | 0 .../FABulous_project_template_vhdl/Fabric/my_lib.vhdl | 0 .../fabric_files}/FABulous_project_template_vhdl/Test/.gitignore | 0 .../FABulous_project_template_vhdl/Test/build_test_design.sh | 0 .../FABulous_project_template_vhdl/Test/fabulous_tb.vhdl | 0 .../fabric_files}/FABulous_project_template_vhdl/Test/makehex.py | 0 .../FABulous_project_template_vhdl/Test/run_simulation_vhdl.sh | 0 .../FABulous_project_template_vhdl/Test/test_design/.gitignore | 0 .../FABulous_project_template_vhdl/Test/test_design/counter.v | 0 .../FABulous_project_template_vhdl/Test/test_design/counter.vhdl | 0 .../FABulous_project_template_vhdl/Test/test_design/right_shift.v | 0 .../Test/test_design/right_shift.vhdl | 0 .../FABulous_project_template_vhdl/Test/test_design/top_wrapper.v | 0 .../Test/test_design/top_wrapper.vhdl | 0 .../Tile/CPU_IO/InPass4_frame_config.vhdl | 0 .../Tile/CPU_IO/OutPass4_frame_config.vhdl | 0 .../fabric_files}/FABulous_project_template_vhdl/Tile/DSP/DSP.csv | 0 .../FABulous_project_template_vhdl/Tile/DSP/DSP_bot/DSP_bot.csv | 0 .../Tile/DSP/DSP_bot/DSP_bot_switch_matrix.list | 0 .../FABulous_project_template_vhdl/Tile/DSP/DSP_bot/MULADD.vhdl | 0 .../FABulous_project_template_vhdl/Tile/DSP/DSP_top/DSP_top.csv | 0 .../Tile/DSP/DSP_top/DSP_top_switch_matrix.list | 0 .../FABulous_project_template_vhdl/Tile/LUT4AB/LUT4AB.csv | 0 .../Tile/LUT4AB/LUT4AB_ConfigMem.csv | 0 .../Tile/LUT4AB/LUT4AB_switch_matrix.list | 0 .../Tile/LUT4AB/LUT4c_frame_config.vhdl | 0 .../Tile/LUT4AB/MUX8LUT_frame_config.vhdl | 0 .../FABulous_project_template_vhdl/Tile/N_term_DSP/N_term_DSP.csv | 0 .../Tile/N_term_DSP/N_term_DSP_switch_matrix.list | 0 .../Tile/N_term_RAM_IO/N_term_RAM_IO.csv | 0 .../Tile/N_term_RAM_IO/N_term_RAM_IO_switch_matrix.list | 0 .../Tile/N_term_single/N_term_single.csv | 0 .../Tile/N_term_single/N_term_single_switch_matrix.list | 0 .../Tile/N_term_single2/N_term_single2.csv | 0 .../Tile/N_term_single2/N_term_single2_switch_matrix.list | 0 .../FABulous_project_template_vhdl/Tile/RAM_IO/Config_access.vhdl | 0 .../Tile/RAM_IO/InPass4_frame_config.vhdl | 0 .../Tile/RAM_IO/OutPass4_frame_config.vhdl | 0 .../FABulous_project_template_vhdl/Tile/RAM_IO/RAM_IO.csv | 0 .../Tile/RAM_IO/RAM_IO_switch_matrix.list | 0 .../FABulous_project_template_vhdl/Tile/RegFile/RegFile.csv | 0 .../FABulous_project_template_vhdl/Tile/RegFile/RegFile_32x4.vhdl | 0 .../Tile/RegFile/RegFile_switch_matrix.list | 0 .../FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP.csv | 0 .../Tile/S_term_DSP/S_term_DSP_switch_matrix.list | 0 .../Tile/S_term_RAM_IO/S_term_RAM_IO.csv | 0 .../Tile/S_term_RAM_IO/S_term_RAM_IO_switch_matrix.list | 0 .../Tile/S_term_single/S_term_single.csv | 0 .../Tile/S_term_single/S_term_single_switch_matrix.list | 0 .../Tile/S_term_single2/S_term_single2.csv | 0 .../Tile/S_term_single2/S_term_single2_switch_matrix.list | 0 .../FABulous_project_template_vhdl/Tile/W_IO/Config_access.vhdl | 0 .../Tile/W_IO/IO_1_bidirectional_frame_config_pass.vhdl | 0 .../FABulous_project_template_vhdl/Tile/W_IO/W_IO.csv | 0 .../Tile/W_IO/W_IO_switch_matrix.list | 0 .../fabric_files}/FABulous_project_template_vhdl/custom_info.xml | 0 .../fabric_files}/FABulous_project_template_vhdl/debug.list | 0 .../fabric_files}/FABulous_project_template_vhdl/fabric.csv | 0 .../FABulous_project_template_vhdl/user_design/AND_gate.vhdl | 0 {fabric_files => FABulous/fabric_files}/README.md | 0 {fabric_files => FABulous/fabric_files}/generic/BlockRAM_1KB.v | 0 {fabric_files => FABulous/fabric_files}/generic/Config.v | 0 {fabric_files => FABulous/fabric_files}/generic/ConfigFSM.v | 0 {fabric_files => FABulous/fabric_files}/generic/Config_access.v | 0 .../fabric_files}/generic/Config_access.vhdl | 0 .../fabric_files}/generic/DSP_bot_switch_matrix.list | 0 .../fabric_files}/generic/DSP_top_switch_matrix.list | 0 {fabric_files => FABulous/fabric_files}/generic/Frame_Data_Reg.v | 0 .../fabric_files}/generic/Frame_Data_Reg.vhdl | 0 {fabric_files => FABulous/fabric_files}/generic/Frame_Select.v | 0 {fabric_files => FABulous/fabric_files}/generic/Frame_Select.vhdl | 0 .../fabric_files}/generic/IO_1_bidirectional_frame_config_pass.v | 0 .../generic/IO_1_bidirectional_frame_config_pass.vhdl | 0 .../fabric_files}/generic/InPass4_frame_config.vhdl | 0 .../fabric_files}/generic/InPass4_frame_config_mux.v | 0 .../fabric_files}/generic/LUT4AB_ConfigMem.csv | 0 .../fabric_files}/generic/LUT4AB_switch_matrix.list | 0 .../fabric_files}/generic/LUT4c_frame_config.vhdl | 0 .../fabric_files}/generic/LUT4c_frame_config_dffesr.v | 0 {fabric_files => FABulous/fabric_files}/generic/MULADD.v | 0 {fabric_files => FABulous/fabric_files}/generic/MULADD.vhdl | 0 .../fabric_files}/generic/MUX8LUT_frame_config.vhdl | 0 .../fabric_files}/generic/MUX8LUT_frame_config_mux.v | 0 .../fabric_files}/generic/N_term_DSP_switch_matrix.list | 0 .../fabric_files}/generic/N_term_RAM_IO_switch_matrix.list | 0 .../fabric_files}/generic/N_term_single2_switch_matrix.list | 0 .../fabric_files}/generic/N_term_single_switch_matrix.list | 0 .../fabric_files}/generic/OutPass4_frame_config.vhdl | 0 .../fabric_files}/generic/OutPass4_frame_config_mux.v | 0 .../fabric_files}/generic/RAM_IO_switch_matrix.list | 0 {fabric_files => FABulous/fabric_files}/generic/RegFile_32x4.v | 0 {fabric_files => FABulous/fabric_files}/generic/RegFile_32x4.vhdl | 0 .../fabric_files}/generic/RegFile_switch_matrix.list | 0 .../fabric_files}/generic/S_term_DSP_switch_matrix.list | 0 .../fabric_files}/generic/S_term_RAM_IO_switch_matrix.list | 0 .../fabric_files}/generic/S_term_single2_switch_matrix.list | 0 .../fabric_files}/generic/S_term_single_switch_matrix.list | 0 .../fabric_files}/generic/W_IO_switch_matrix.list | 0 {fabric_files => FABulous/fabric_files}/generic/bitbang.v | 0 {fabric_files => FABulous/fabric_files}/generic/bitbang.vhdl | 0 {fabric_files => FABulous/fabric_files}/generic/config_UART.v | 0 {fabric_files => FABulous/fabric_files}/generic/config_UART.vhdl | 0 {fabric_files => FABulous/fabric_files}/generic/custom_info.xml | 0 {fabric_files => FABulous/fabric_files}/generic/debug.list | 0 {fabric_files => FABulous/fabric_files}/generic/fabric.csv | 0 {fabric_files => FABulous/fabric_files}/generic/models_pack.v | 0 {fabric_files => FABulous/fabric_files}/generic/my_lib.vhdl | 0 {fabric_generator => FABulous/fabric_generator}/.gitignore | 0 {fabric_generator => FABulous/fabric_generator}/__init__.py | 0 .../fabric_generator}/code_generation_VHDL.py | 0 .../fabric_generator}/code_generation_Verilog.py | 0 {fabric_generator => FABulous/fabric_generator}/code_generator.py | 0 {fabric_generator => FABulous/fabric_generator}/fabric.py | 0 {fabric_generator => FABulous/fabric_generator}/fabric_gen.py | 0 .../fabric_generator}/fabulous_top_wrapper_temp/BlockRAM_1KB.v | 0 .../fabulous_top_wrapper_temp/ConfigFSM_template.v | 0 .../fabulous_top_wrapper_temp/ConfigFSM_template.vhdl | 0 .../fabric_generator}/fabulous_top_wrapper_temp/Config_template.v | 0 .../fabulous_top_wrapper_temp/Config_template.vhdl | 0 .../fabulous_top_wrapper_temp/Frame_Data_Reg_template.v | 0 .../fabulous_top_wrapper_temp/Frame_Select_template.v | 0 .../fabric_generator}/fabulous_top_wrapper_temp/README.md | 0 .../fabric_generator}/fabulous_top_wrapper_temp/bitbang.v | 0 .../fabric_generator}/fabulous_top_wrapper_temp/bitbang.vhdl | 0 .../fabric_generator}/fabulous_top_wrapper_temp/config_UART.v | 0 .../fabulous_top_wrapper_temp/eFPGA_top_template.v | 0 .../eFPGA_v3_top_sky130_with_BRAM_template.v | 0 .../eFPGA_v3_top_sky130_with_BRAM_template.vhdl | 0 .../fabulous_top_wrapper_temp/tb_bitbang_template.vhd | 0 .../fabulous_top_wrapper_temp/top_wrapper_generator.py | 0 .../fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py | 0 .../top_wrapper_generator_with_BRAM_vhdl.py | 0 {fabric_generator => FABulous/fabric_generator}/file_parser.py | 0 .../fabric_generator}/model_generation_npnr.py | 0 .../fabric_generator}/model_generation_vpr.py | 0 {fabric_generator => FABulous/fabric_generator}/utilities.py | 0 {geometry_generator => FABulous/geometry_generator}/__init__.py | 0 .../geometry_generator}/bel_geometry.py | 0 .../geometry_generator}/fabric_geometry.py | 0 .../geometry_generator}/geometry_gen.py | 0 .../geometry_generator}/geometry_obj.py | 0 .../geometry_generator}/port_geometry.py | 0 .../geometry_generator}/sm_geometry.py | 0 .../geometry_generator}/tile_geometry.py | 0 .../geometry_generator}/wire_geometry.py | 0 228 files changed, 0 insertions(+), 0 deletions(-) rename FABulous.py => FABulous/FABulous.py (100%) rename FABulous_API.py => FABulous/FABulous_API.py (100%) rename {fabric_cad => FABulous/fabric_cad}/README.md (100%) rename {fabric_cad => FABulous/fabric_cad}/bit_gen.py (100%) rename {fabric_cad => FABulous/fabric_cad}/synth/cells_map.v (100%) rename {fabric_cad => FABulous/fabric_cad}/synth/cells_map_ff.v (100%) rename {fabric_cad => FABulous/fabric_cad}/synth/ff_map.v (100%) rename {fabric_cad => FABulous/fabric_cad}/synth/latches_map.v (100%) rename {fabric_cad => FABulous/fabric_cad}/synth/prims.v (100%) rename {fabric_cad => FABulous/fabric_cad}/synth/prims_ff.v (100%) rename {fabric_cad => FABulous/fabric_cad}/synth/synth_fabulous.tcl (100%) rename {fabric_cad => FABulous/fabric_cad}/synth/synth_fabulous_dffesr.tcl (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/FABulous.tcl (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Fabric/BlockRAM_1KB.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Fabric/ConfigFSM.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Fabric/Frame_Data_Reg.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Fabric/Frame_Select.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Fabric/bitbang.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Fabric/config_UART.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Fabric/eFPGA_Config.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Fabric/models_pack.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/.gitignore (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/README.md (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/build_test_design.sh (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/fabulous_tb.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/makehex.py (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/run_emulation_sim.sh (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/run_simulation.sh (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/sequential_16bit_en_tb.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/test_design/.gitignore (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/test_design/counter.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/test_design/right_shift.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Test/test_design/top_wrapper.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/DSP/DSP.csv (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/DSP/DSP_bot/DSP_bot.csv (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/DSP/DSP_bot/DSP_bot_switch_matrix.list (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/DSP/DSP_bot/MULADD.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/DSP/DSP_top/DSP_top.csv (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/DSP/DSP_top/DSP_top_switch_matrix.list (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/LUT4AB/LUT4AB.csv (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/LUT4AB/LUT4AB_ConfigMem.csv (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/LUT4AB/LUT4AB_switch_matrix.list (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/LUT4AB/LUT4c_frame_config_dffesr.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/LUT4AB/MUX8LUT_frame_config_mux.v (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/N_term_DSP/N_term_DSP.csv (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/N_term_DSP/N_term_DSP_switch_matrix.list (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/N_term_RAM_IO/N_term_RAM_IO.csv (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/N_term_RAM_IO/N_term_RAM_IO_switch_matrix.list (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/N_term_single/N_term_single.csv (100%) rename {fabric_files => FABulous/fabric_files}/FABulous_project_template_verilog/Tile/N_term_single/N_term_single_switch_matrix.list (100%) rename {fabric_files => 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a/fabric_files/FABulous_project_template_verilog/Tile/S_term_single/S_term_single.csv b/FABulous/fabric_files/FABulous_project_template_verilog/Tile/S_term_single/S_term_single.csv similarity index 100% rename from fabric_files/FABulous_project_template_verilog/Tile/S_term_single/S_term_single.csv rename to FABulous/fabric_files/FABulous_project_template_verilog/Tile/S_term_single/S_term_single.csv diff --git a/fabric_files/FABulous_project_template_verilog/Tile/S_term_single/S_term_single_switch_matrix.list b/FABulous/fabric_files/FABulous_project_template_verilog/Tile/S_term_single/S_term_single_switch_matrix.list similarity index 100% rename from fabric_files/FABulous_project_template_verilog/Tile/S_term_single/S_term_single_switch_matrix.list rename to FABulous/fabric_files/FABulous_project_template_verilog/Tile/S_term_single/S_term_single_switch_matrix.list diff --git a/fabric_files/FABulous_project_template_verilog/Tile/S_term_single2/S_term_single2.csv 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FABulous/fabric_files/FABulous_project_template_vhdl/Tile/RegFile/RegFile_32x4.vhdl diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/RegFile/RegFile_switch_matrix.list b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/RegFile/RegFile_switch_matrix.list similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/RegFile/RegFile_switch_matrix.list rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/RegFile/RegFile_switch_matrix.list diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP.csv b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP.csv similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP.csv rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP.csv diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP_switch_matrix.list b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP_switch_matrix.list similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP_switch_matrix.list rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_DSP/S_term_DSP_switch_matrix.list diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/S_term_RAM_IO/S_term_RAM_IO.csv b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_RAM_IO/S_term_RAM_IO.csv similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/S_term_RAM_IO/S_term_RAM_IO.csv rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_RAM_IO/S_term_RAM_IO.csv diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/S_term_RAM_IO/S_term_RAM_IO_switch_matrix.list b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_RAM_IO/S_term_RAM_IO_switch_matrix.list similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/S_term_RAM_IO/S_term_RAM_IO_switch_matrix.list rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_RAM_IO/S_term_RAM_IO_switch_matrix.list diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single/S_term_single.csv b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single/S_term_single.csv similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/S_term_single/S_term_single.csv rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single/S_term_single.csv diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single/S_term_single_switch_matrix.list b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single/S_term_single_switch_matrix.list similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/S_term_single/S_term_single_switch_matrix.list rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single/S_term_single_switch_matrix.list diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single2/S_term_single2.csv b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single2/S_term_single2.csv similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/S_term_single2/S_term_single2.csv rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single2/S_term_single2.csv diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single2/S_term_single2_switch_matrix.list b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single2/S_term_single2_switch_matrix.list similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/S_term_single2/S_term_single2_switch_matrix.list rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/S_term_single2/S_term_single2_switch_matrix.list diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/Config_access.vhdl b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/Config_access.vhdl similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/W_IO/Config_access.vhdl rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/Config_access.vhdl diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/IO_1_bidirectional_frame_config_pass.vhdl b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/IO_1_bidirectional_frame_config_pass.vhdl similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/W_IO/IO_1_bidirectional_frame_config_pass.vhdl rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/IO_1_bidirectional_frame_config_pass.vhdl diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/W_IO.csv b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/W_IO.csv similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/W_IO/W_IO.csv rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/W_IO.csv diff --git a/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/W_IO_switch_matrix.list b/FABulous/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/W_IO_switch_matrix.list similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/Tile/W_IO/W_IO_switch_matrix.list rename to FABulous/fabric_files/FABulous_project_template_vhdl/Tile/W_IO/W_IO_switch_matrix.list diff --git a/fabric_files/FABulous_project_template_vhdl/custom_info.xml b/FABulous/fabric_files/FABulous_project_template_vhdl/custom_info.xml similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/custom_info.xml rename to FABulous/fabric_files/FABulous_project_template_vhdl/custom_info.xml diff --git a/fabric_files/FABulous_project_template_vhdl/debug.list b/FABulous/fabric_files/FABulous_project_template_vhdl/debug.list similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/debug.list rename to FABulous/fabric_files/FABulous_project_template_vhdl/debug.list diff --git a/fabric_files/FABulous_project_template_vhdl/fabric.csv b/FABulous/fabric_files/FABulous_project_template_vhdl/fabric.csv similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/fabric.csv rename to FABulous/fabric_files/FABulous_project_template_vhdl/fabric.csv diff --git a/fabric_files/FABulous_project_template_vhdl/user_design/AND_gate.vhdl b/FABulous/fabric_files/FABulous_project_template_vhdl/user_design/AND_gate.vhdl similarity index 100% rename from fabric_files/FABulous_project_template_vhdl/user_design/AND_gate.vhdl rename to FABulous/fabric_files/FABulous_project_template_vhdl/user_design/AND_gate.vhdl diff --git a/fabric_files/README.md b/FABulous/fabric_files/README.md similarity index 100% rename from fabric_files/README.md rename to FABulous/fabric_files/README.md diff --git a/fabric_files/generic/BlockRAM_1KB.v b/FABulous/fabric_files/generic/BlockRAM_1KB.v similarity index 100% rename from fabric_files/generic/BlockRAM_1KB.v rename to FABulous/fabric_files/generic/BlockRAM_1KB.v diff --git a/fabric_files/generic/Config.v b/FABulous/fabric_files/generic/Config.v similarity index 100% rename from fabric_files/generic/Config.v rename to FABulous/fabric_files/generic/Config.v diff --git a/fabric_files/generic/ConfigFSM.v b/FABulous/fabric_files/generic/ConfigFSM.v similarity index 100% rename from fabric_files/generic/ConfigFSM.v rename to FABulous/fabric_files/generic/ConfigFSM.v diff --git a/fabric_files/generic/Config_access.v b/FABulous/fabric_files/generic/Config_access.v similarity index 100% rename from fabric_files/generic/Config_access.v rename to FABulous/fabric_files/generic/Config_access.v diff --git a/fabric_files/generic/Config_access.vhdl b/FABulous/fabric_files/generic/Config_access.vhdl similarity index 100% rename from fabric_files/generic/Config_access.vhdl rename to FABulous/fabric_files/generic/Config_access.vhdl diff --git a/fabric_files/generic/DSP_bot_switch_matrix.list b/FABulous/fabric_files/generic/DSP_bot_switch_matrix.list similarity index 100% rename from fabric_files/generic/DSP_bot_switch_matrix.list rename to FABulous/fabric_files/generic/DSP_bot_switch_matrix.list diff --git a/fabric_files/generic/DSP_top_switch_matrix.list b/FABulous/fabric_files/generic/DSP_top_switch_matrix.list similarity index 100% rename from fabric_files/generic/DSP_top_switch_matrix.list rename to FABulous/fabric_files/generic/DSP_top_switch_matrix.list diff --git a/fabric_files/generic/Frame_Data_Reg.v b/FABulous/fabric_files/generic/Frame_Data_Reg.v similarity index 100% rename from fabric_files/generic/Frame_Data_Reg.v rename to FABulous/fabric_files/generic/Frame_Data_Reg.v diff --git a/fabric_files/generic/Frame_Data_Reg.vhdl b/FABulous/fabric_files/generic/Frame_Data_Reg.vhdl similarity index 100% rename from fabric_files/generic/Frame_Data_Reg.vhdl rename to FABulous/fabric_files/generic/Frame_Data_Reg.vhdl diff --git a/fabric_files/generic/Frame_Select.v b/FABulous/fabric_files/generic/Frame_Select.v similarity index 100% rename from fabric_files/generic/Frame_Select.v rename to FABulous/fabric_files/generic/Frame_Select.v diff --git a/fabric_files/generic/Frame_Select.vhdl b/FABulous/fabric_files/generic/Frame_Select.vhdl similarity index 100% rename from fabric_files/generic/Frame_Select.vhdl rename to FABulous/fabric_files/generic/Frame_Select.vhdl diff --git a/fabric_files/generic/IO_1_bidirectional_frame_config_pass.v b/FABulous/fabric_files/generic/IO_1_bidirectional_frame_config_pass.v similarity index 100% rename from fabric_files/generic/IO_1_bidirectional_frame_config_pass.v rename to FABulous/fabric_files/generic/IO_1_bidirectional_frame_config_pass.v diff --git a/fabric_files/generic/IO_1_bidirectional_frame_config_pass.vhdl b/FABulous/fabric_files/generic/IO_1_bidirectional_frame_config_pass.vhdl similarity index 100% rename from fabric_files/generic/IO_1_bidirectional_frame_config_pass.vhdl rename to FABulous/fabric_files/generic/IO_1_bidirectional_frame_config_pass.vhdl diff --git a/fabric_files/generic/InPass4_frame_config.vhdl b/FABulous/fabric_files/generic/InPass4_frame_config.vhdl similarity index 100% rename from fabric_files/generic/InPass4_frame_config.vhdl rename to FABulous/fabric_files/generic/InPass4_frame_config.vhdl diff --git a/fabric_files/generic/InPass4_frame_config_mux.v b/FABulous/fabric_files/generic/InPass4_frame_config_mux.v similarity index 100% rename from fabric_files/generic/InPass4_frame_config_mux.v rename to FABulous/fabric_files/generic/InPass4_frame_config_mux.v diff --git a/fabric_files/generic/LUT4AB_ConfigMem.csv b/FABulous/fabric_files/generic/LUT4AB_ConfigMem.csv similarity index 100% rename from fabric_files/generic/LUT4AB_ConfigMem.csv rename to FABulous/fabric_files/generic/LUT4AB_ConfigMem.csv diff --git a/fabric_files/generic/LUT4AB_switch_matrix.list b/FABulous/fabric_files/generic/LUT4AB_switch_matrix.list similarity index 100% rename from fabric_files/generic/LUT4AB_switch_matrix.list rename to FABulous/fabric_files/generic/LUT4AB_switch_matrix.list diff --git a/fabric_files/generic/LUT4c_frame_config.vhdl b/FABulous/fabric_files/generic/LUT4c_frame_config.vhdl similarity index 100% rename from fabric_files/generic/LUT4c_frame_config.vhdl rename to FABulous/fabric_files/generic/LUT4c_frame_config.vhdl diff --git a/fabric_files/generic/LUT4c_frame_config_dffesr.v b/FABulous/fabric_files/generic/LUT4c_frame_config_dffesr.v similarity index 100% rename from fabric_files/generic/LUT4c_frame_config_dffesr.v rename to FABulous/fabric_files/generic/LUT4c_frame_config_dffesr.v diff --git a/fabric_files/generic/MULADD.v b/FABulous/fabric_files/generic/MULADD.v similarity index 100% rename from fabric_files/generic/MULADD.v rename to FABulous/fabric_files/generic/MULADD.v diff --git a/fabric_files/generic/MULADD.vhdl b/FABulous/fabric_files/generic/MULADD.vhdl similarity index 100% rename from fabric_files/generic/MULADD.vhdl rename to FABulous/fabric_files/generic/MULADD.vhdl diff --git a/fabric_files/generic/MUX8LUT_frame_config.vhdl b/FABulous/fabric_files/generic/MUX8LUT_frame_config.vhdl similarity index 100% rename from fabric_files/generic/MUX8LUT_frame_config.vhdl rename to FABulous/fabric_files/generic/MUX8LUT_frame_config.vhdl diff --git a/fabric_files/generic/MUX8LUT_frame_config_mux.v b/FABulous/fabric_files/generic/MUX8LUT_frame_config_mux.v similarity index 100% rename from fabric_files/generic/MUX8LUT_frame_config_mux.v rename to FABulous/fabric_files/generic/MUX8LUT_frame_config_mux.v diff --git a/fabric_files/generic/N_term_DSP_switch_matrix.list b/FABulous/fabric_files/generic/N_term_DSP_switch_matrix.list similarity index 100% rename from fabric_files/generic/N_term_DSP_switch_matrix.list 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a/fabric_files/generic/OutPass4_frame_config.vhdl b/FABulous/fabric_files/generic/OutPass4_frame_config.vhdl similarity index 100% rename from fabric_files/generic/OutPass4_frame_config.vhdl rename to FABulous/fabric_files/generic/OutPass4_frame_config.vhdl diff --git a/fabric_files/generic/OutPass4_frame_config_mux.v b/FABulous/fabric_files/generic/OutPass4_frame_config_mux.v similarity index 100% rename from fabric_files/generic/OutPass4_frame_config_mux.v rename to FABulous/fabric_files/generic/OutPass4_frame_config_mux.v diff --git a/fabric_files/generic/RAM_IO_switch_matrix.list b/FABulous/fabric_files/generic/RAM_IO_switch_matrix.list similarity index 100% rename from fabric_files/generic/RAM_IO_switch_matrix.list rename to FABulous/fabric_files/generic/RAM_IO_switch_matrix.list diff --git a/fabric_files/generic/RegFile_32x4.v b/FABulous/fabric_files/generic/RegFile_32x4.v similarity index 100% rename from fabric_files/generic/RegFile_32x4.v rename to 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a/fabric_files/generic/bitbang.v b/FABulous/fabric_files/generic/bitbang.v similarity index 100% rename from fabric_files/generic/bitbang.v rename to FABulous/fabric_files/generic/bitbang.v diff --git a/fabric_files/generic/bitbang.vhdl b/FABulous/fabric_files/generic/bitbang.vhdl similarity index 100% rename from fabric_files/generic/bitbang.vhdl rename to FABulous/fabric_files/generic/bitbang.vhdl diff --git a/fabric_files/generic/config_UART.v b/FABulous/fabric_files/generic/config_UART.v similarity index 100% rename from fabric_files/generic/config_UART.v rename to FABulous/fabric_files/generic/config_UART.v diff --git a/fabric_files/generic/config_UART.vhdl b/FABulous/fabric_files/generic/config_UART.vhdl similarity index 100% rename from fabric_files/generic/config_UART.vhdl rename to FABulous/fabric_files/generic/config_UART.vhdl diff --git a/fabric_files/generic/custom_info.xml b/FABulous/fabric_files/generic/custom_info.xml similarity index 100% rename from fabric_files/generic/custom_info.xml rename to FABulous/fabric_files/generic/custom_info.xml diff --git a/fabric_files/generic/debug.list b/FABulous/fabric_files/generic/debug.list similarity index 100% rename from fabric_files/generic/debug.list rename to FABulous/fabric_files/generic/debug.list diff --git a/fabric_files/generic/fabric.csv b/FABulous/fabric_files/generic/fabric.csv similarity index 100% rename from fabric_files/generic/fabric.csv rename to FABulous/fabric_files/generic/fabric.csv diff --git a/fabric_files/generic/models_pack.v b/FABulous/fabric_files/generic/models_pack.v similarity index 100% rename from fabric_files/generic/models_pack.v rename to FABulous/fabric_files/generic/models_pack.v diff --git a/fabric_files/generic/my_lib.vhdl b/FABulous/fabric_files/generic/my_lib.vhdl similarity index 100% rename from fabric_files/generic/my_lib.vhdl rename to FABulous/fabric_files/generic/my_lib.vhdl diff --git a/fabric_generator/.gitignore b/FABulous/fabric_generator/.gitignore similarity index 100% rename from fabric_generator/.gitignore rename to FABulous/fabric_generator/.gitignore diff --git a/fabric_generator/__init__.py b/FABulous/fabric_generator/__init__.py similarity index 100% rename from fabric_generator/__init__.py rename to FABulous/fabric_generator/__init__.py diff --git a/fabric_generator/code_generation_VHDL.py b/FABulous/fabric_generator/code_generation_VHDL.py similarity index 100% rename from fabric_generator/code_generation_VHDL.py rename to FABulous/fabric_generator/code_generation_VHDL.py diff --git a/fabric_generator/code_generation_Verilog.py b/FABulous/fabric_generator/code_generation_Verilog.py similarity index 100% rename from fabric_generator/code_generation_Verilog.py rename to FABulous/fabric_generator/code_generation_Verilog.py diff --git a/fabric_generator/code_generator.py b/FABulous/fabric_generator/code_generator.py similarity index 100% rename from fabric_generator/code_generator.py rename to FABulous/fabric_generator/code_generator.py diff --git a/fabric_generator/fabric.py b/FABulous/fabric_generator/fabric.py similarity index 100% rename from fabric_generator/fabric.py rename to FABulous/fabric_generator/fabric.py diff --git a/fabric_generator/fabric_gen.py b/FABulous/fabric_generator/fabric_gen.py similarity index 100% rename from fabric_generator/fabric_gen.py rename to FABulous/fabric_generator/fabric_gen.py diff --git a/fabric_generator/fabulous_top_wrapper_temp/BlockRAM_1KB.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/BlockRAM_1KB.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/BlockRAM_1KB.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/BlockRAM_1KB.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.vhdl b/FABulous/fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.vhdl similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.vhdl rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/ConfigFSM_template.vhdl diff --git a/fabric_generator/fabulous_top_wrapper_temp/Config_template.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/Config_template.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/Config_template.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/Config_template.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/Config_template.vhdl b/FABulous/fabric_generator/fabulous_top_wrapper_temp/Config_template.vhdl similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/Config_template.vhdl rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/Config_template.vhdl diff --git a/fabric_generator/fabulous_top_wrapper_temp/Frame_Data_Reg_template.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/Frame_Data_Reg_template.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/Frame_Data_Reg_template.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/Frame_Data_Reg_template.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/Frame_Select_template.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/Frame_Select_template.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/Frame_Select_template.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/Frame_Select_template.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/README.md b/FABulous/fabric_generator/fabulous_top_wrapper_temp/README.md similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/README.md rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/README.md diff --git a/fabric_generator/fabulous_top_wrapper_temp/bitbang.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/bitbang.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/bitbang.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/bitbang.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/bitbang.vhdl b/FABulous/fabric_generator/fabulous_top_wrapper_temp/bitbang.vhdl similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/bitbang.vhdl rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/bitbang.vhdl diff --git a/fabric_generator/fabulous_top_wrapper_temp/config_UART.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/config_UART.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/config_UART.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/config_UART.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/eFPGA_top_template.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/eFPGA_top_template.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/eFPGA_top_template.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/eFPGA_top_template.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.v b/FABulous/fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.v similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.v rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.v diff --git a/fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.vhdl b/FABulous/fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.vhdl similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.vhdl rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/eFPGA_v3_top_sky130_with_BRAM_template.vhdl diff --git a/fabric_generator/fabulous_top_wrapper_temp/tb_bitbang_template.vhd b/FABulous/fabric_generator/fabulous_top_wrapper_temp/tb_bitbang_template.vhd similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/tb_bitbang_template.vhd rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/tb_bitbang_template.vhd diff --git a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator.py b/FABulous/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator.py similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator.py rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator.py diff --git a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py b/FABulous/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM.py diff --git a/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM_vhdl.py b/FABulous/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM_vhdl.py similarity index 100% rename from fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM_vhdl.py rename to FABulous/fabric_generator/fabulous_top_wrapper_temp/top_wrapper_generator_with_BRAM_vhdl.py diff --git a/fabric_generator/file_parser.py b/FABulous/fabric_generator/file_parser.py similarity index 100% rename from fabric_generator/file_parser.py rename to FABulous/fabric_generator/file_parser.py diff --git a/fabric_generator/model_generation_npnr.py b/FABulous/fabric_generator/model_generation_npnr.py similarity index 100% rename from fabric_generator/model_generation_npnr.py rename to FABulous/fabric_generator/model_generation_npnr.py diff --git a/fabric_generator/model_generation_vpr.py b/FABulous/fabric_generator/model_generation_vpr.py similarity index 100% rename from fabric_generator/model_generation_vpr.py rename to FABulous/fabric_generator/model_generation_vpr.py diff --git a/fabric_generator/utilities.py b/FABulous/fabric_generator/utilities.py similarity index 100% rename from fabric_generator/utilities.py rename to FABulous/fabric_generator/utilities.py diff --git a/geometry_generator/__init__.py b/FABulous/geometry_generator/__init__.py similarity index 100% rename from geometry_generator/__init__.py rename to FABulous/geometry_generator/__init__.py diff --git a/geometry_generator/bel_geometry.py b/FABulous/geometry_generator/bel_geometry.py similarity index 100% rename from geometry_generator/bel_geometry.py rename to FABulous/geometry_generator/bel_geometry.py diff --git a/geometry_generator/fabric_geometry.py b/FABulous/geometry_generator/fabric_geometry.py similarity index 100% rename from geometry_generator/fabric_geometry.py rename to FABulous/geometry_generator/fabric_geometry.py diff --git a/geometry_generator/geometry_gen.py b/FABulous/geometry_generator/geometry_gen.py similarity index 100% rename from geometry_generator/geometry_gen.py rename to FABulous/geometry_generator/geometry_gen.py diff --git a/geometry_generator/geometry_obj.py b/FABulous/geometry_generator/geometry_obj.py similarity index 100% rename from geometry_generator/geometry_obj.py rename to FABulous/geometry_generator/geometry_obj.py diff --git a/geometry_generator/port_geometry.py b/FABulous/geometry_generator/port_geometry.py similarity index 100% rename from geometry_generator/port_geometry.py rename to FABulous/geometry_generator/port_geometry.py diff --git a/geometry_generator/sm_geometry.py b/FABulous/geometry_generator/sm_geometry.py similarity index 100% rename from geometry_generator/sm_geometry.py rename to FABulous/geometry_generator/sm_geometry.py diff --git a/geometry_generator/tile_geometry.py b/FABulous/geometry_generator/tile_geometry.py similarity index 100% rename from geometry_generator/tile_geometry.py rename to FABulous/geometry_generator/tile_geometry.py diff --git a/geometry_generator/wire_geometry.py b/FABulous/geometry_generator/wire_geometry.py similarity index 100% rename from geometry_generator/wire_geometry.py rename to FABulous/geometry_generator/wire_geometry.py From 6c386e2a9a8ddacbe2f2480c648fa79c2d41fc80 Mon Sep 17 00:00:00 2001 From: "Jonas K." Date: Mon, 6 May 2024 14:18:40 +0200 Subject: [PATCH 2/5] Fix some filepathes Signed-off-by: Jonas K. --- .github/workflows/fabric_gen.yml | 8 ++++---- .../FABulous_project_template_verilog/Test/README.md | 2 +- .../Test/build_test_design.sh | 4 ++-- .../Test/run_emulation_sim.sh | 9 +++------ .../Test/run_simulation.sh | 7 +++---- 5 files changed, 13 insertions(+), 17 deletions(-) diff --git a/.github/workflows/fabric_gen.yml b/.github/workflows/fabric_gen.yml index f9eb24ce..2394e4b3 100644 --- a/.github/workflows/fabric_gen.yml +++ b/.github/workflows/fabric_gen.yml @@ -31,14 +31,14 @@ jobs: - name: Lint with flake8 run: | # stop the build if there are Python syntax errors or undefined names - flake8 fabric_generator/ --count --select=E9,F63,F7,F82 --show-source --statistics + flake8 FABulous/fabric_generator/ --count --select=E9,F63,F7,F82 --show-source --statistics # exit-zero treats all errors as warnings. The GitHub editor is 127 chars wide - flake8 fabric_generator --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics + flake8 FABulous/fabric_generator --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics - name: Run fabric generator flow run: | export FAB_ROOT=. - python3.9 FABulous.py -c demo - python3.9 FABulous.py demo --script ./demo/FABulous.tcl + python3.9 FABulous/FABulous.py -c demo + python3.9 FABulous/FABulous.py demo --script ./demo/FABulous.tcl - name: Run simulation smoketest run: | diff --git a/FABulous/fabric_files/FABulous_project_template_verilog/Test/README.md b/FABulous/fabric_files/FABulous_project_template_verilog/Test/README.md index 001d7d3a..4ebbc56c 100644 --- a/FABulous/fabric_files/FABulous_project_template_verilog/Test/README.md +++ b/FABulous/fabric_files/FABulous_project_template_verilog/Test/README.md @@ -1,4 +1,4 @@ -This assumes the default instructions were followed to build a 8x14 fabric in `../fabric_generator`. +This assumes the default instructions were followed to build a 8x14 fabric in `../../fabric_generator`. Latest Yosys and `nextpnr-generic` from upstream (_not_ the old FABulous nextpnr fork) are used to build the test design. diff --git a/FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh b/FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh index 5b905735..90b18fd4 100755 --- a/FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh +++ b/FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash -SYNTH_TCL=../../fabric_cad/synth/synth_fabulous.tcl -BIT_GEN=../../fabric_cad/bit_gen.py +SYNTH_TCL=../../FABulous/fabric_cad/synth/synth_fabulous.tcl +BIT_GEN=../../FABulous/fabric_cad/bit_gen.py DESIGN=counter diff --git a/FABulous/fabric_files/FABulous_project_template_verilog/Test/run_emulation_sim.sh b/FABulous/fabric_files/FABulous_project_template_verilog/Test/run_emulation_sim.sh index f0e02da3..11c6935e 100755 --- a/FABulous/fabric_files/FABulous_project_template_verilog/Test/run_emulation_sim.sh +++ b/FABulous/fabric_files/FABulous_project_template_verilog/Test/run_emulation_sim.sh @@ -1,17 +1,14 @@ #!/usr/bin/env bash set -ex DESIGN=counter -BITSTREAM=test_design/${DESIGN}.bin -VERILOG=../../fabric_generator/verilog_output -MAX_BITBYTES=16384 rm -rf tmp mkdir tmp for i in $(find ../Tile -type f -name "*.v") $(find ../Fabric -type f -name "*.v") -do +do cp $i tmp/ done -iverilog -D EMULATION -s fab_tb -o fab_tb.vvp test_design/${DESIGN}.vh tmp/* test_design/${DESIGN}.v fabulous_tb.v +iverilog -D EMULATION -s fab_tb -o fab_tb.vvp test_design/${DESIGN}.vh tmp/* test_design/${DESIGN}.v fabulous_tb.v vvp fab_tb.vvp -rm -rf tmp \ No newline at end of file +rm -rf tmp diff --git a/FABulous/fabric_files/FABulous_project_template_verilog/Test/run_simulation.sh b/FABulous/fabric_files/FABulous_project_template_verilog/Test/run_simulation.sh index 980bb601..960a6037 100755 --- a/FABulous/fabric_files/FABulous_project_template_verilog/Test/run_simulation.sh +++ b/FABulous/fabric_files/FABulous_project_template_verilog/Test/run_simulation.sh @@ -2,17 +2,16 @@ set -ex DESIGN=counter BITSTREAM=test_design/${DESIGN}.bin -VERILOG=../../fabric_generator/verilog_output MAX_BITBYTES=16384 rm -rf tmp mkdir tmp for i in $(find ../Tile -type f -name "*.v") $(find ../Fabric -type f -name "*.v") -do +do cp $i tmp/ done -iverilog -s fab_tb -o fab_tb.vvp tmp/* test_design/${DESIGN}.v fabulous_tb.v +iverilog -s fab_tb -o fab_tb.vvp tmp/* test_design/${DESIGN}.v fabulous_tb.v python3 makehex.py $BITSTREAM $MAX_BITBYTES bitstream.hex vvp fab_tb.vvp -rm -rf tmp \ No newline at end of file +rm -rf tmp From 1539ec347561cb316d7f2b91d185d21d1edc1a6a Mon Sep 17 00:00:00 2001 From: "Jonas K." Date: Sun, 23 Jul 2023 16:06:12 +0200 Subject: [PATCH 3/5] FABulous: Add auto set for FAB_ROOT env var and add main() Automatically sets the fabulousRoot path if no FAB_ROOT env var is specified. Add Python interpreter path in file header. Add main() function. Signed-off-by: Jonas K. --- FABulous/FABulous.py | 40 ++++++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 12 deletions(-) diff --git a/FABulous/FABulous.py b/FABulous/FABulous.py index dae12e4a..bfb03302 100644 --- a/FABulous/FABulous.py +++ b/FABulous/FABulous.py @@ -1,3 +1,5 @@ +#!/usr/bin/env python + # Copyright 2021 University of Manchester # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -45,17 +47,29 @@ MAX_BITBYTES = 16384 -fabulousRoot = os.getenv("FAB_ROOT") -if fabulousRoot is None: - print("FAB_ROOT environment variable not set!") - print("Use 'export FAB_ROOT='") - sys.exit(-1) - logger = logging.getLogger(__name__) logging.basicConfig( format="[%(levelname)s]-%(asctime)s - %(message)s", level=logging.INFO ) +metaDataDir = ".FABulous" + +fabulousRoot = os.getenv('FAB_ROOT') +if fabulousRoot is None: + fabulousRoot = os.path.dirname(os.path.realpath(__file__)) + logger.warning("FAB_ROOT environment variable not set!") + logger.warning(f"Using {fabulousRoot} as FAB_ROOT") +else: + if not os.path.exists(fabulousRoot): + logger.error( + f"FAB_ROOT environment variable set to {fabulousRoot} but the directory does not exist") + sys.exit() + else: + if os.path.exists(f"{fabulousRoot}/FABulous"): + fabulousRoot = f"{fabulousRoot}/FABulous" + + logger.info(f"FAB_ROOT set to {fabulousRoot}") + # Create a FABulous Verilog project that contains all the required files def create_project(project_dir, type: Literal["verilog", "vhdl"] = "verilog"): @@ -161,8 +175,8 @@ class FABulousShell(cmd.Cmd): Type help or ? to list commands To see documentation for a command type: - help -or + help +or ? To execute a shell command type: @@ -230,8 +244,7 @@ def inter(*args, **varargs): if fun.startswith("do_"): name = fun.strip("do_") tcl.createcommand( - name, wrap_with_except_handling(getattr(self, fun)) - ) + name, wrap_with_except_handling(getattr(self, fun))) # os.chdir(args.project_dir) tcl.eval(script) @@ -1179,7 +1192,7 @@ def complete_tcl(self, text, *ignored): return self._complete_path(text) -if __name__ == "__main__": +def main(): if sys.version_info < (3, 9, 0): print("Need Python 3.9 or above to run FABulous") exit(-1) @@ -1232,7 +1245,6 @@ def complete_tcl(self, text, *ignored): args = parser.parse_args() args.top = args.project_dir.split("/")[-1] - metaDataDir = ".FABulous" if args.createProject: create_project(args.project_dir, args.writer) @@ -1267,3 +1279,7 @@ def complete_tcl(self, text, *ignored): fabShell.cmdloop() else: fabShell.cmdloop() + + +if __name__ == "__main__": + main() From 9d5ea4917eaaf66da5d15cdadfc3349897f94c46 Mon Sep 17 00:00:00 2001 From: "Jonas K." Date: Mon, 6 May 2024 15:19:14 +0200 Subject: [PATCH 4/5] Build FABulous package with setuptools Update pyproject.toml to build FABulous package with setuptools. Use setuptools-scm for autoamtic project version generation. Add FABulous as package script to make it callable directlty from shell. Add bit_gen as package script and add main function to it. Update "fabric_gen" github workflow: - Use new FABulous structure - Update external actions Update import statements in all python modules to absolue imports of FABulous modules and and remove unused imports. Update gitignore. Signed-off-by: Jonas K. --- .github/workflows/fabric_gen.yml | 19 ++--- .gitignore | 1 + FABulous/FABulous.py | 55 +++++++------ FABulous/FABulous_API.py | 18 ++--- FABulous/fabric_cad/__init__.py | 0 FABulous/fabric_cad/bit_gen.py | 80 +++++++++---------- .../Test/build_test_design.sh | 6 +- .../fabric_generator/code_generation_VHDL.py | 9 +-- .../code_generation_Verilog.py | 6 +- FABulous/fabric_generator/code_generator.py | 3 +- FABulous/fabric_generator/fabric.py | 6 +- FABulous/fabric_generator/fabric_gen.py | 32 +++++--- FABulous/fabric_generator/file_parser.py | 19 ++++- .../fabric_generator/model_generation_npnr.py | 7 +- .../fabric_generator/model_generation_vpr.py | 15 ++-- FABulous/geometry_generator/bel_geometry.py | 7 +- .../geometry_generator/fabric_geometry.py | 9 ++- FABulous/geometry_generator/geometry_gen.py | 4 +- FABulous/geometry_generator/port_geometry.py | 3 +- FABulous/geometry_generator/sm_geometry.py | 13 +-- FABulous/geometry_generator/tile_geometry.py | 15 ++-- FABulous/geometry_generator/wire_geometry.py | 7 +- pyproject.toml | 44 +++++++++- 23 files changed, 221 insertions(+), 157 deletions(-) create mode 100644 FABulous/fabric_cad/__init__.py diff --git a/.github/workflows/fabric_gen.yml b/.github/workflows/fabric_gen.yml index 2394e4b3..df1647de 100644 --- a/.github/workflows/fabric_gen.yml +++ b/.github/workflows/fabric_gen.yml @@ -11,15 +11,15 @@ jobs: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v2 + - uses: actions/checkout@v4 with: submodules: recursive - name: Set up Python 3.9 - uses: actions/setup-python@v2 + uses: actions/setup-python@v4 with: python-version: 3.9 - name: Set up OSS CAD suite - uses: YosysHQ/setup-oss-cad-suite@v1 + uses: YosysHQ/setup-oss-cad-suite@v2 - name: Install dependencies run: | python3 -m pip install --upgrade pip @@ -31,15 +31,16 @@ jobs: - name: Lint with flake8 run: | # stop the build if there are Python syntax errors or undefined names - flake8 FABulous/fabric_generator/ --count --select=E9,F63,F7,F82 --show-source --statistics + flake8 FABulous/**/*.py --count --select=E9,F63,F7,F82 --show-source --statistics # exit-zero treats all errors as warnings. The GitHub editor is 127 chars wide - flake8 FABulous/fabric_generator --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics + flake8 FABulous/**/*.py --count --exit-zero --max-complexity=10 --max-line-length=127 --statistics + - name: Install FABulous + run: | + pip3 install -e . - name: Run fabric generator flow run: | - export FAB_ROOT=. - python3.9 FABulous/FABulous.py -c demo - python3.9 FABulous/FABulous.py demo --script ./demo/FABulous.tcl - + FABulous -c demo + FABulous demo --script ./demo/FABulous.tcl - name: Run simulation smoketest run: | cd ./demo/Test diff --git a/.gitignore b/.gitignore index bd2f4374..0b8559fd 100755 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,3 @@ demo/ **/__pycache__ +*.egg-info/ diff --git a/FABulous/FABulous.py b/FABulous/FABulous.py index bfb03302..d2c0af9a 100644 --- a/FABulous/FABulous.py +++ b/FABulous/FABulous.py @@ -16,30 +16,31 @@ # # SPDX-License-Identifier: Apache-2.0 -from contextlib import redirect_stdout -from fabric_generator.utilities import genFabricObject, GetFabric -import fabric_generator.model_generation_npnr as model_gen_npnr -from fabric_generator.code_generation_VHDL import VHDLWriter -from fabric_generator.code_generation_Verilog import VerilogWriter -from FABulous_API import FABulous +import argparse +import cmd import csv -from glob import glob +import logging import os -import argparse import pickle +import platform import re -import sys -import subprocess as sp -import shutil -from typing import List, Literal -import docker -import cmd import readline -import logging +import shutil +import subprocess as sp +import sys import tkinter as tk -from pathlib import PurePosixPath, PureWindowsPath -import platform import traceback +from contextlib import redirect_stdout +from glob import glob +from pathlib import PurePosixPath, PureWindowsPath +from typing import List, Literal + +import docker +import FABulous.fabric_generator.model_generation_npnr as model_gen_npnr +from FABulous.fabric_generator.code_generation_Verilog import VerilogWriter +from FABulous.fabric_generator.code_generation_VHDL import VHDLWriter +from FABulous.fabric_generator.utilities import GetFabric, genFabricObject +from FABulous.FABulous_API import FABulous readline.set_completer_delims(" \t\n") histfile = "" @@ -54,7 +55,7 @@ metaDataDir = ".FABulous" -fabulousRoot = os.getenv('FAB_ROOT') +fabulousRoot = os.getenv("FAB_ROOT") if fabulousRoot is None: fabulousRoot = os.path.dirname(os.path.realpath(__file__)) logger.warning("FAB_ROOT environment variable not set!") @@ -62,7 +63,8 @@ else: if not os.path.exists(fabulousRoot): logger.error( - f"FAB_ROOT environment variable set to {fabulousRoot} but the directory does not exist") + f"FAB_ROOT environment variable set to {fabulousRoot} but the directory does not exist" + ) sys.exit() else: if os.path.exists(f"{fabulousRoot}/FABulous"): @@ -86,6 +88,11 @@ def create_project(project_dir, type: Literal["verilog", "vhdl"] = "verilog"): f"{project_dir}/", dirs_exist_ok=True, ) + shutil.copytree( + f"{fabulousRoot}/fabric_cad/synth", + f"{project_dir}/Test/synth", + dirs_exist_ok=True, + ) adjust_directory_in_verilog_tb(project_dir) @@ -128,9 +135,7 @@ def adjust_directory_in_verilog_tb(project_dir): f"{fabulousRoot}/fabric_files/FABulous_project_template_verilog/Test/sequential_16bit_en_tb.v", "rt", ) as fin: - with open( - f"{fabulousRoot}/{project_dir}/Test/sequential_16bit_en_tb.v", "wt" - ) as fout: + with open(f"{project_dir}/Test/sequential_16bit_en_tb.v", "wt") as fout: for line in fin: fout.write(line.replace("PROJECT_DIR", f"{project_dir}")) @@ -244,7 +249,8 @@ def inter(*args, **varargs): if fun.startswith("do_"): name = fun.strip("do_") tcl.createcommand( - name, wrap_with_except_handling(getattr(self, fun))) + name, wrap_with_except_handling(getattr(self, fun)) + ) # os.chdir(args.project_dir) tcl.eval(script) @@ -987,8 +993,7 @@ def do_gen_bitStream_binary(self, args): logger.info(f"Generating Bitstream for design {self.projectDir}/{path}") logger.info(f"Outputting to {self.projectDir}/{parent}/{bitstream_file}") runCmd = [ - "python3", - f"{fabulousRoot}/fabric_cad/bit_gen.py", + "bit_gen", "-genBitstream", f"{self.projectDir}/{parent}/{fasm_file}", f"{self.projectDir}/.FABulous/bitStreamSpec.bin", diff --git a/FABulous/FABulous_API.py b/FABulous/FABulous_API.py index 6171107c..066a0eb5 100644 --- a/FABulous/FABulous_API.py +++ b/FABulous/FABulous_API.py @@ -1,14 +1,14 @@ -import fabric_generator.model_generation_vpr as model_gen_vpr -import fabric_generator.model_generation_npnr as model_gen_npnr -from fabric_generator.code_generation_VHDL import VHDLWriter -import fabric_generator.code_generator as codeGen -import fabric_generator.file_parser as fileParser -from fabric_generator.fabric import Fabric, Tile -from fabric_generator.fabric_gen import FabricGenerator -from geometry_generator.geometry_gen import GeometryGenerator - import logging +import FABulous.fabric_generator.code_generator as codeGen +import FABulous.fabric_generator.file_parser as fileParser +import FABulous.fabric_generator.model_generation_npnr as model_gen_npnr +import FABulous.fabric_generator.model_generation_vpr as model_gen_vpr +from FABulous.fabric_generator.code_generation_VHDL import VHDLWriter +from FABulous.fabric_generator.fabric import Fabric, Tile +from FABulous.fabric_generator.fabric_gen import FabricGenerator +from FABulous.geometry_generator.geometry_gen import GeometryGenerator + logger = logging.getLogger(__name__) logging.basicConfig( format="[%(levelname)s]-%(asctime)s - %(message)s", level=logging.INFO diff --git a/FABulous/fabric_cad/__init__.py b/FABulous/fabric_cad/__init__.py new file mode 100644 index 00000000..e69de29b diff --git a/FABulous/fabric_cad/bit_gen.py b/FABulous/fabric_cad/bit_gen.py index d5dda196..abd9012e 100644 --- a/FABulous/fabric_cad/bit_gen.py +++ b/FABulous/fabric_cad/bit_gen.py @@ -1,14 +1,9 @@ -# Python 3 -from array import array +#!/usr/bin/env python + +import pickle import re import sys -from contextlib import redirect_stdout -from io import StringIO -import math -import os -import numpy -import pickle -import csv + from fasm import * # Remove this line if you do not have the fasm library installed and will not be generating a bitstream @@ -260,39 +255,40 @@ def getTileAndWireByWireDest(self, loc: str, dest: str, jumps: bool = True): ##################################################################################### # Main ##################################################################################### - -# Strip arguments -caseProcessedArguments = list(map(lambda x: x.strip(), sys.argv)) -processedArguments = list(map(lambda x: x.lower(), caseProcessedArguments)) -flagRE = re.compile("-\S*") - -if "-genBitstream".lower() in str(sys.argv).lower(): - argIndex = processedArguments.index("-genBitstream".lower()) - - if len(processedArguments) <= argIndex + 3: - raise ValueError( - "\nError: -genBitstream expect three file names - the fasm file, the spec file and the output file" - ) - elif ( - flagRE.match(caseProcessedArguments[argIndex + 1]) - or flagRE.match(caseProcessedArguments[argIndex + 2]) - or flagRE.match(caseProcessedArguments[argIndex + 3]) - ): - raise ValueError( - "\nError: -genBitstream expect three file names, but found a flag in the arguments:" - f" {caseProcessedArguments[argIndex + 1]}, {caseProcessedArguments[argIndex + 2]}, {caseProcessedArguments[argIndex + 3]}\n" +def bit_gen(): + # Strip arguments + caseProcessedArguments = list(map(lambda x: x.strip(), sys.argv)) + processedArguments = list(map(lambda x: x.lower(), caseProcessedArguments)) + flagRE = re.compile("-\S*") + if "-genBitstream".lower() in str(sys.argv).lower(): + argIndex = processedArguments.index("-genBitstream".lower()) + if len(processedArguments) <= argIndex + 3: + raise ValueError( + "\nError: -genBitstream expect three file names - the fasm file, the spec file and the output file" + ) + elif ( + flagRE.match(caseProcessedArguments[argIndex + 1]) + or flagRE.match(caseProcessedArguments[argIndex + 2]) + or flagRE.match(caseProcessedArguments[argIndex + 3]) + ): + raise ValueError( + "\nError: -genBitstream expect three file names, but found a flag in the arguments:" + f" {caseProcessedArguments[argIndex + 1]}, {caseProcessedArguments[argIndex + 2]}, {caseProcessedArguments[argIndex + 3]}\n" + ) + + FasmFileName = caseProcessedArguments[argIndex + 1] + SpecFileName = caseProcessedArguments[argIndex + 2] + OutFileName = caseProcessedArguments[argIndex + 3] + + genBitstream(FasmFileName, SpecFileName, OutFileName) + + if ("-help".lower() in str(sys.argv).lower()) or ("-h" in str(sys.argv).lower()): + print("") + print("Options/Switches") + print( + " -genBitstream foo.fasm spec.txt bitstream.txt - generates a bitstream - the first file is the fasm file, the second is the bitstream spec and the third is the fasm file to write to" ) - FasmFileName = caseProcessedArguments[argIndex + 1] - SpecFileName = caseProcessedArguments[argIndex + 2] - OutFileName = caseProcessedArguments[argIndex + 3] - genBitstream(FasmFileName, SpecFileName, OutFileName) - - -if ("-help".lower() in str(sys.argv).lower()) or ("-h" in str(sys.argv).lower()): - print("") - print("Options/Switches") - print( - " -genBitstream foo.fasm spec.txt bitstream.txt - generates a bitstream - the first file is the fasm file, the second is the bitstream spec and the third is the fasm file to write to" - ) +if __name__ == "__main__": + bit_gen() diff --git a/FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh b/FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh index 90b18fd4..dc4b85dd 100755 --- a/FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh +++ b/FABulous/fabric_files/FABulous_project_template_verilog/Test/build_test_design.sh @@ -1,6 +1,6 @@ #!/usr/bin/env bash -SYNTH_TCL=../../FABulous/fabric_cad/synth/synth_fabulous.tcl -BIT_GEN=../../FABulous/fabric_cad/bit_gen.py +SYNTH_TCL=./synth/synth_fabulous.tcl +BIT_GEN=bit_gen DESIGN=counter @@ -8,4 +8,4 @@ set -ex yosys -qp "tcl $SYNTH_TCL 4 top_wrapper test_design/${DESIGN}.json" test_design/${DESIGN}.v test_design/top_wrapper.v FAB_ROOT=.. nextpnr-generic --uarch fabulous --json test_design/${DESIGN}.json -o fasm=test_design/${DESIGN}_des.fasm -python3 ${BIT_GEN} -genBitstream test_design/${DESIGN}_des.fasm ../.FABulous/bitStreamSpec.bin test_design/${DESIGN}.bin +${BIT_GEN} -genBitstream test_design/${DESIGN}_des.fasm ../.FABulous/bitStreamSpec.bin test_design/${DESIGN}.bin diff --git a/FABulous/fabric_generator/code_generation_VHDL.py b/FABulous/fabric_generator/code_generation_VHDL.py index 6cad3c1f..f28450fa 100644 --- a/FABulous/fabric_generator/code_generation_VHDL.py +++ b/FABulous/fabric_generator/code_generation_VHDL.py @@ -1,11 +1,10 @@ -from typing import Literal, Tuple -import os import math +import os import re +from typing import Literal, Tuple -from fabric_generator.fabric import Fabric, Tile, Port, Bel, IO -from fabric_generator.code_generator import codeGenerator -from fabric_generator.fabric import ConfigBitMode +from FABulous.fabric_generator.code_generator import codeGenerator +from FABulous.fabric_generator.fabric import IO, Bel, ConfigBitMode, Fabric, Port, Tile class VHDLWriter(codeGenerator): diff --git a/FABulous/fabric_generator/code_generation_Verilog.py b/FABulous/fabric_generator/code_generation_Verilog.py index 5f465f6e..cb696393 100644 --- a/FABulous/fabric_generator/code_generation_Verilog.py +++ b/FABulous/fabric_generator/code_generation_Verilog.py @@ -1,9 +1,9 @@ -from typing import Literal import math import re +from typing import Literal -from fabric_generator.fabric import Tile, Bel, ConfigBitMode, IO -from fabric_generator.code_generator import codeGenerator +from FABulous.fabric_generator.code_generator import codeGenerator +from FABulous.fabric_generator.fabric import IO, Bel, ConfigBitMode, Tile class VerilogWriter(codeGenerator): diff --git a/FABulous/fabric_generator/code_generator.py b/FABulous/fabric_generator/code_generator.py index 3f4dcc8e..88e2b0c1 100644 --- a/FABulous/fabric_generator/code_generator.py +++ b/FABulous/fabric_generator/code_generator.py @@ -1,6 +1,7 @@ import abc from typing import List, Tuple -from fabric_generator.fabric import Bel, IO, ConfigBitMode + +from FABulous.fabric_generator.fabric import IO, Bel, ConfigBitMode class codeGenerator(abc.ABC): diff --git a/FABulous/fabric_generator/fabric.py b/FABulous/fabric_generator/fabric.py index dda545a2..a63aa725 100644 --- a/FABulous/fabric_generator/fabric.py +++ b/FABulous/fabric_generator/fabric.py @@ -1,8 +1,8 @@ -from dataclasses import dataclass, field -from typing import Any, Literal, List, Dict, Tuple import math -from enum import Enum import os +from dataclasses import dataclass, field +from enum import Enum +from typing import Any, Dict, List, Literal, Tuple class IO(Enum): diff --git a/FABulous/fabric_generator/fabric_gen.py b/FABulous/fabric_generator/fabric_gen.py index f2e72b95..80dce0ef 100644 --- a/FABulous/fabric_generator/fabric_gen.py +++ b/FABulous/fabric_generator/fabric_gen.py @@ -16,26 +16,32 @@ # SPDX-License-Identifier: Apache-2.0 -import re +import csv +import logging import math import os +import re import string -import csv -from typing import Dict, List, Tuple -import logging from pathlib import Path +from typing import Dict, List, Tuple - +from FABulous.fabric_generator.code_generation_Verilog import VerilogWriter +from FABulous.fabric_generator.code_generation_VHDL import VHDLWriter +from FABulous.fabric_generator.code_generator import codeGenerator +from FABulous.fabric_generator.fabric import ( + IO, + ConfigBitMode, + ConfigMem, + Direction, + Fabric, + MultiplexerStyle, + Port, + SuperTile, + Tile, +) +from FABulous.fabric_generator.file_parser import parseConfigMem, parseList, parseMatrix from fasm import * # Remove this line if you do not have the fasm library installed and will not be generating a bitstream - -from fabric_generator.file_parser import parseMatrix, parseConfigMem, parseList -from fabric_generator.fabric import IO, Direction, MultiplexerStyle, ConfigBitMode -from fabric_generator.fabric import Fabric, Tile, Port, SuperTile, ConfigMem -from fabric_generator.code_generation_VHDL import VHDLWriter -from fabric_generator.code_generation_Verilog import VerilogWriter -from fabric_generator.code_generator import codeGenerator - SWITCH_MATRIX_DEBUG_SIGNAL = True logger = logging.getLogger(__name__) diff --git a/FABulous/fabric_generator/file_parser.py b/FABulous/fabric_generator/file_parser.py index 04f891c7..63ce002b 100644 --- a/FABulous/fabric_generator/file_parser.py +++ b/FABulous/fabric_generator/file_parser.py @@ -1,11 +1,22 @@ +import csv +import os import re from copy import deepcopy from typing import Dict, List, Literal, Tuple, Union, overload -import csv -import os -from fabric_generator.fabric import Fabric, Port, Bel, Tile, SuperTile, ConfigMem -from fabric_generator.fabric import IO, Direction, Side, MultiplexerStyle, ConfigBitMode +from FABulous.fabric_generator.fabric import ( + IO, + Bel, + ConfigBitMode, + ConfigMem, + Direction, + Fabric, + MultiplexerStyle, + Port, + Side, + SuperTile, + Tile, +) # from fabric import Fabric, Port, Bel, Tile, SuperTile, ConfigMem # from fabric import IO, Direction, Side, MultiplexerStyle, ConfigBitMode diff --git a/FABulous/fabric_generator/model_generation_npnr.py b/FABulous/fabric_generator/model_generation_npnr.py index 61102d79..57d015a4 100644 --- a/FABulous/fabric_generator/model_generation_npnr.py +++ b/FABulous/fabric_generator/model_generation_npnr.py @@ -1,8 +1,9 @@ import string from typing import Tuple -from fabric_generator.utilities import * -from fabric_generator.fabric import Fabric, Tile -from fabric_generator.file_parser import parseMatrix, parseList + +from FABulous.fabric_generator.fabric import Fabric, Tile +from FABulous.fabric_generator.file_parser import parseList, parseMatrix +from FABulous.fabric_generator.utilities import * def genNextpnrModel(fabric: Fabric): diff --git a/FABulous/fabric_generator/model_generation_vpr.py b/FABulous/fabric_generator/model_generation_vpr.py index ea24e6f9..c091bd59 100644 --- a/FABulous/fabric_generator/model_generation_vpr.py +++ b/FABulous/fabric_generator/model_generation_vpr.py @@ -1,14 +1,15 @@ +import logging +import os import string +import xml.etree.ElementTree as ET from sys import prefix from typing import List -from fabric_generator.fabric_gen import FabricGenerator -from fabric_generator.utilities import * -from fabric_generator.fabric import IO, Bel, Fabric -import xml.etree.ElementTree as ET -import os from xml.dom import minidom -from fabric_generator.file_parser import parseMatrix, parseList -import logging + +from FABulous.fabric_generator.fabric import IO, Bel, Fabric +from FABulous.fabric_generator.fabric_gen import FabricGenerator +from FABulous.fabric_generator.file_parser import parseList, parseMatrix +from FABulous.fabric_generator.utilities import * logger = logging.getLogger(__name__) diff --git a/FABulous/geometry_generator/bel_geometry.py b/FABulous/geometry_generator/bel_geometry.py index 32c2ba33..986e35de 100644 --- a/FABulous/geometry_generator/bel_geometry.py +++ b/FABulous/geometry_generator/bel_geometry.py @@ -1,7 +1,8 @@ -from typing import List -from fabric_generator.fabric import Bel, IO -from geometry_generator.port_geometry import PortGeometry, PortType from csv import writer as csvWriter +from typing import List + +from FABulous.fabric_generator.fabric import IO, Bel +from FABulous.geometry_generator.port_geometry import PortGeometry, PortType class BelGeometry: diff --git a/FABulous/geometry_generator/fabric_geometry.py b/FABulous/geometry_generator/fabric_geometry.py index ec3b0d04..e62bc09a 100644 --- a/FABulous/geometry_generator/fabric_geometry.py +++ b/FABulous/geometry_generator/fabric_geometry.py @@ -1,9 +1,10 @@ -from typing import List, Dict, Set import logging from csv import writer as csvWriter -from fabric_generator.fabric import Fabric -from geometry_generator.geometry_obj import Location, Border -from geometry_generator.tile_geometry import TileGeometry +from typing import Dict, List, Set + +from FABulous.fabric_generator.fabric import Fabric +from FABulous.geometry_generator.geometry_obj import Border, Location +from FABulous.geometry_generator.tile_geometry import TileGeometry logger = logging.getLogger(__name__) diff --git a/FABulous/geometry_generator/geometry_gen.py b/FABulous/geometry_generator/geometry_gen.py index 24a2ab32..4ddd6e0e 100644 --- a/FABulous/geometry_generator/geometry_gen.py +++ b/FABulous/geometry_generator/geometry_gen.py @@ -15,8 +15,8 @@ # SPDX-License-Identifier: Apache-2.0 -from fabric_generator.fabric import Fabric -from geometry_generator.fabric_geometry import FabricGeometry +from FABulous.fabric_generator.fabric import Fabric +from FABulous.geometry_generator.fabric_geometry import FabricGeometry class GeometryGenerator: diff --git a/FABulous/geometry_generator/port_geometry.py b/FABulous/geometry_generator/port_geometry.py index 2429f802..a61e47b5 100644 --- a/FABulous/geometry_generator/port_geometry.py +++ b/FABulous/geometry_generator/port_geometry.py @@ -1,7 +1,8 @@ from csv import writer as csvWriter -from fabric_generator.fabric import Side, IO from enum import Enum +from FABulous.fabric_generator.fabric import IO, Side + class PortType(Enum): SWITCH_MATRIX = "PORT" diff --git a/FABulous/geometry_generator/sm_geometry.py b/FABulous/geometry_generator/sm_geometry.py index 9b83ebd8..49d8340f 100644 --- a/FABulous/geometry_generator/sm_geometry.py +++ b/FABulous/geometry_generator/sm_geometry.py @@ -1,10 +1,11 @@ -from typing import List -from fabric_generator.fabric import Port, Tile, Direction, Side, IO -from geometry_generator.geometry_obj import Border -from geometry_generator.bel_geometry import BelGeometry -from geometry_generator.port_geometry import PortGeometry, PortType -from csv import writer as csvWriter import logging +from csv import writer as csvWriter +from typing import List + +from FABulous.fabric_generator.fabric import IO, Direction, Port, Side, Tile +from FABulous.geometry_generator.bel_geometry import BelGeometry +from FABulous.geometry_generator.geometry_obj import Border +from FABulous.geometry_generator.port_geometry import PortGeometry, PortType logger = logging.getLogger(__name__) diff --git a/FABulous/geometry_generator/tile_geometry.py b/FABulous/geometry_generator/tile_geometry.py index 118e5231..726ac675 100644 --- a/FABulous/geometry_generator/tile_geometry.py +++ b/FABulous/geometry_generator/tile_geometry.py @@ -1,11 +1,12 @@ -from typing import List -from fabric_generator.fabric import Tile, Side, Direction -from geometry_generator.geometry_obj import Border, Location -from geometry_generator.sm_geometry import SmGeometry -from geometry_generator.bel_geometry import BelGeometry -from geometry_generator.wire_geometry import WireGeometry, StairWires -from geometry_generator.port_geometry import PortGeometry from csv import writer as csvWriter +from typing import List + +from FABulous.fabric_generator.fabric import Direction, Side, Tile +from FABulous.geometry_generator.bel_geometry import BelGeometry +from FABulous.geometry_generator.geometry_obj import Border, Location +from FABulous.geometry_generator.port_geometry import PortGeometry +from FABulous.geometry_generator.sm_geometry import SmGeometry +from FABulous.geometry_generator.wire_geometry import StairWires, WireGeometry class TileGeometry: diff --git a/FABulous/geometry_generator/wire_geometry.py b/FABulous/geometry_generator/wire_geometry.py index ae366d7c..9cc14724 100644 --- a/FABulous/geometry_generator/wire_geometry.py +++ b/FABulous/geometry_generator/wire_geometry.py @@ -1,7 +1,8 @@ -from typing import List -from fabric_generator.fabric import Direction -from geometry_generator.geometry_obj import Location from csv import writer as csvWriter +from typing import List + +from FABulous.fabric_generator.fabric import Direction +from FABulous.geometry_generator.geometry_obj import Location class WireGeometry: diff --git a/pyproject.toml b/pyproject.toml index b4f1b18b..272d830b 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -1,8 +1,44 @@ [build-system] -requires = ["flit_core >=3.2,<4"] -build-backend = "flit_core.buildapi" +requires = ["setuptools>=45", "setuptools_scm[toml]>=6.2"] +build-backend = "setuptools.build_meta" [project] -name = "FABulous Documentation" +name = "FABulous-FPGA" authors = [{name = "Jing, Nguyen, Bea, Bardia, Dirk", email = "dirk.koch@manchester.ac.uk"}] -dynamic = ["version", "description"] +description = "FABulous FPGA Fabric generator" +readme = "README.md" +requires-python = ">=3.9" +dynamic = ["version"] + +classifiers = [ + "Programming Language :: Python :: 3", + "License :: OSI Approved :: Apache Software License", + "Operating System :: OS Independent", +] + + +dependencies = [ + 'numpy', + 'fasm', + 'docker', +] + +[project.urls] +"Homepage" = "https://github.com/FPGA-Research-Manchester/FABulous" +"Bug Tracker" = "https://github.com/FPGA-Research-Manchester/FABulous/issues" + + +[project.scripts] +FABulous = "FABulous.FABulous:main" +bit_gen = "FABulous.fabric_cad.bit_gen:bit_gen" + +[tool.setuptools_scm] +version_scheme = "post-release" +local_scheme = "dirty-tag" + + +[tool.setuptools.packages.find] +exclude = ["docs, demo"] # exclude packages matching these glob patterns (empty by default) + +[tool.setuptools.package-data] +mypkg = ["FABulous/**/*"] From 5f6465917447e5c8ea1422b9abdc2592a2893b8f Mon Sep 17 00:00:00 2001 From: "Jonas K." Date: Fri, 8 Sep 2023 11:42:11 +0200 Subject: [PATCH 5/5] docs: Update docs for new project setup Update documentation to install and use FABulous with the new setup. Signed-off-by: Jonas K. --- README.md | 11 +++--- docs/source/Building fabric.rst | 36 +++++++++---------- .../Bitstream generation.rst | 20 +++++------ docs/source/Usage.rst | 22 +++++++----- docs/source/simulation/emulation.rst | 6 ++-- 5 files changed, 50 insertions(+), 45 deletions(-) diff --git a/README.md b/README.md index 23ae4e80..4c8df270 100644 --- a/README.md +++ b/README.md @@ -61,14 +61,14 @@ To set up FABulous: ``` git clone https://github.com/FPGA-Research-Manchester/FABulous cd FABulous -export FAB_ROOT=`pwd` +pip install -e . ``` We have provided a Python Command Line Interface (CLI) as well as a project structure for easy access of the FABulous toolchain. The `Tile` folder contains all the definitions of the fabric primitive as well as the fabric matrix configuration. `fabric.csv` is what defining the architecture of the fabric. The FABulous project folder also contains a `.FABulous` folder which contains all the metadata during the generation of the fabric. -We can initiate the FABulous shell with `python3 FABulous.py `. After that you will see a shell interface which allow for interactive fabric generation. To generate a fabric we first need to run `load_fabric [fabric_CSV]` to load in the fabric definition. Then we can call `run_FABulous_fabric` to generate a fabric. +We can initiate the FABulous shell with `FABulous `. After that you will see a shell interface which allow for interactive fabric generation. To generate a fabric we first need to run `load_fabric [fabric_CSV]` to load in the fabric definition. Then we can call `run_FABulous_fabric` to generate a fabric. To generate a model and bitstream for a specific design call `run_FABulous_bitstream npnr ` which will generate a bitstream for the provided design in the same folder as the design. @@ -78,8 +78,9 @@ To exit the shell simply type `exit` and this will terminate the shell. A demo of the whole flow: ``` -python3 FABulous.py -c demo -# In the FABulous shell (python3 FABulous.py demo) +FABulous -c demo # Create a demo project +FABulous demo # Run Fabulous interactive shell for demo project +# In the FABulous shell load_fabric run_FABulous_fabric run_FABulous_bitstream npnr ./user_design/sequential_16bit_en.v @@ -95,7 +96,7 @@ cd demo/Test ``` The tool also supports using TCL script to drive the build process. Assuming you have created a demo project using -`python3 FABulous.py -c demo`, you can call `python3 FABulous.py demo -s ./demo/FABulous.tcl` to run the demo flow with the TCL interface. +`FABulous -c demo`, you can call `FABulous demo -s ./demo/FABulous.tcl` to run the demo flow with the TCL interface. More details on bitstream generation can be found [here](https://fabulous.readthedocs.io/en/latest/FPGA-to-bitstream/Bitstream%20generation.html). diff --git a/docs/source/Building fabric.rst b/docs/source/Building fabric.rst index d5a3f800..f5c1021e 100644 --- a/docs/source/Building fabric.rst +++ b/docs/source/Building fabric.rst @@ -7,16 +7,16 @@ The user can run the flow step by step as well (see below for instructions on bu :width: 80% :align: center -Other than building the fabric with the ``run_FABulous_fabric`` command as shown in the :ref:`Quick start`, the user can -also build the fabric step by step to suit what they need. We will demonstrate this in the following section from +Other than building the fabric with the ``run_FABulous_fabric`` command as shown in the :ref:`Quick start`, the user can +also build the fabric step by step to suit what they need. We will demonstrate this in the following section from creating scratch. The following is assuming your current directory is in `$FAB_ROOT` and all the pre-request set up are -completed. +completed. #. Create a new project .. prompt:: bash FABulous> - python3 FABulous.py -c demo + FABulous -c demo This will create a new project named ``demo`` in the current directory. @@ -24,19 +24,19 @@ This will create a new project named ``demo`` in the current directory. .. prompt:: bash FABulous> - python3 FABulous.py demo + FABulous demo And now, we will be in the FABulous shell. After running the above command, the current working directory will be moved into the project directory, which is ``demo`` in this case. #. Load the fabric CSV definition file - + .. prompt:: bash FABulous> - + load_fabric -This command will load in the fabric definition file with the name ``fabric.csv`` in the current directory. If the -definition file is in another directory or named differently, the user can specify the path as an argument to the +This command will load in the fabric definition file with the name ``fabric.csv`` in the current directory. If the +definition file is in another directory or named differently, the user can specify the path as an argument to the command. For example: ``load_fabric fabric2.csv``. From this point onwards, all the files read and write commands, will be relative to where the specified directory of the ``.csv`` is located. For example, if the definition file located at ``some_path/.csv``, then all the file's read and write commands will be relative to ``some_path``. @@ -47,15 +47,15 @@ located at ``some_path/.csv``, then all the file's read and write co gen_switch_matrix LUT4AB RAM_IO -The above command will generate the switch matrix for the ``LUT4AB`` tile and the ``RAM_IO`` tile. The switch matrix -generated will be based on the ``MATRIX`` entry of the tile definition in the fabric definition file. If the provided -directory is a ``.list`` file, then we will generate a switch matrix for the tile, based on the fabric definition file +The above command will generate the switch matrix for the ``LUT4AB`` tile and the ``RAM_IO`` tile. The switch matrix +generated will be based on the ``MATRIX`` entry of the tile definition in the fabric definition file. If the provided +directory is a ``.list`` file, then we will generate a switch matrix for the tile, based on the fabric definition file and add the content in the ``list`` file to the matrix. If the provided file is a ``.csv`` file, the tool will just load the data in, and generate a switch base on the data. Finally, if providing a ``.v`` or ``.vhdl`` file, the tool will skip -matrix generation for the tile, and will use the provided file as the switch matrix. +matrix generation for the tile, and will use the provided file as the switch matrix. .. note:: - During model generation, the given file for ``MATRIX`` entry needs to be either a ``.list`` or ``.csv`` + During model generation, the given file for ``MATRIX`` entry needs to be either a ``.list`` or ``.csv`` file. @@ -80,8 +80,8 @@ The above command will generate the actual tiles for the ``LUT4AB`` tile and the All the files generated will be located in the respective tile directory. i.e RTL for ``LUT4AB`` will be in ``Tile/LUT4AB/`` -We will need to run the above commands for all the tiles to get all the RTL of all the tiles, which is quite tedious to -do. As a result, the following command will generate all the RTL for all the tiles in the fabric including all the super +We will need to run the above commands for all the tiles to get all the RTL of all the tiles, which is quite tedious to +do. As a result, the following command will generate all the RTL for all the tiles in the fabric including all the super tiles within the fabric. .. prompt:: bash FABulous> @@ -95,7 +95,7 @@ tiles within the fabric. gen_fabric -#. Generate Verilog top wrapper. +#. Generate Verilog top wrapper. .. prompt:: bash FABulous> @@ -105,7 +105,7 @@ tiles within the fabric. #. Generate the nextpnr model. .. prompt:: bash FABulous> - + gen_model_npnr #. Generate the VPR model. diff --git a/docs/source/FPGA-to-bitstream/Bitstream generation.rst b/docs/source/FPGA-to-bitstream/Bitstream generation.rst index b0244423..1a1a9aad 100644 --- a/docs/source/FPGA-to-bitstream/Bitstream generation.rst +++ b/docs/source/FPGA-to-bitstream/Bitstream generation.rst @@ -9,21 +9,21 @@ Generate Bitstream <-- Meta Data User guide ---------- -We have provided two methods for the user to generate bitstreams. The first method is done using the CLI provided and +We have provided two methods for the user to generate bitstreams. The first method is done using the CLI provided and the second method which the user calls the script manually. The first method is recommended, as it provides all the necessary information to generate the bitstream. The second method is provided for cases where the user has decided not to work with the FABulous project structure. Generate bitstream using CLI ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -To generate a bitstream using the CLI, the user must first generate the bitstream specification using the CLI. To +To generate a bitstream using the CLI, the user must first generate the bitstream specification using the CLI. To generate the bitstream specification, we can call the ``gen_bitstream_spec`` command from the CLI. It is expected that the user had also run synthesis and place and route for the design, which generates the ``.fasm`` file of the design. To generate the bitstream, the user can call the ``gen_bitstream_binary `` command from the CLI, where the ``design.fasm`` is the ``.fasm`` file generated by synthesis and place and route. -The resulting bitstream is placed in the same directory as where the ``fasm`` file is located and named as +The resulting bitstream is placed in the same directory as where the ``fasm`` file is located and named as ``design.bin``. Manually generate bitstream @@ -35,7 +35,7 @@ With the FASM file generated by Nextpnr or VPR, you can run this command for bit .. code-block:: console - python3 $FAB_ROOT/fabric_cad/bit_gen.py -genBitstream bitStreamSpec.bin + bit_gen -genBitstream meta_data.txt +------------------+-----------------------------------------------------------------------+ | | the FASM file generated by Nextpnr or VPR in previous compilation | @@ -50,16 +50,16 @@ The following command lowers the FASM representation of the placed and routed `` .. code-block:: console - python3 $FAB_ROOT/fabric_cad/bit_gen.py -genBitstream 16bit_sequential_en.fasm bitStreamSpec.bin 16bit_sequential_en_output.bin + bit_gen -genBitstream 16bit_sequential_en.fasm meta_data.txt 16bit_sequential_en_output.bin Changes in the primitives or adding new primitives -------------------------------------------------- -For a change in the primitives or adding new primitives, you can simply add them within the primitive file. As an -example, in the ``LUT4c_frame_config`` primitive description below there are 16 configuration bits for INIT values, +For a change in the primitives or adding new primitives, you can simply add them within the primitive file. As an +example, in the ``LUT4c_frame_config`` primitive description below there are 16 configuration bits for INIT values, 1 configuration bit ``FF`` for the flip-flop bypass switch, 1 configuration bit ``IOmux`` for the carry input switch and -1 configuration bit ``SET_NORESET`` for the SET or RESET switch, which means there are 19 configuration bits for each -LUT4 parameters setting. The number of entries in the mapping needs to match the ``NoConfigBits`` otherwise, the tool +1 configuration bit ``SET_NORESET`` for the SET or RESET switch, which means there are 19 configuration bits for each +LUT4 parameters setting. The number of entries in the mapping needs to match the ``NoConfigBits`` otherwise, the tool will give an error. .. code-block:: verilog @@ -90,7 +90,7 @@ will give an error. ... endmodule - + (to do) diff --git a/docs/source/Usage.rst b/docs/source/Usage.rst index 47d125df..cb61e6af 100644 --- a/docs/source/Usage.rst +++ b/docs/source/Usage.rst @@ -15,7 +15,7 @@ The following packages need to be installed for generating fabric HDLs git clone https://github.com/FPGA-Research-Manchester/FABulous -:Python: +:Python: version >= 3.9 :python dependencies: @@ -38,6 +38,10 @@ The following packages need to be installed for the CAD toolchain :`Nextpnr-generic `_: version > 0.4-28-gac17c36b +Install FABulous with "editable" option: +.. code-block:: console + + pip3 install -e . Building Fabric and Bitstream ----------------------------- @@ -45,20 +49,20 @@ Building Fabric and Bitstream .. code-block:: console - python3 FABulous.py -c - python3 FABulous.py + FABulous -c + FABulous # inside the FABulous shell load_fabric run_FABulous_fabric run_FABulous_bitstream npnr user_design/sequential_16bit_en.v - -After a successful call with the command ``run_FABulous_fabric`` the RTL file of each of the tiles can be found in the ``Tile`` folder and the fabric RTL file can be found in the ``Fabric`` folder. -After a successful call with the command ``run_FABulous_bitstream npnr user_design/sequential_16bit_en.v``. -The bitstream and all the log files generated during synthesis and place and route can be found under -the ``user_design`` folder. The bitstream will be named as ``sequential_16bit_en.bin`` The above command is using -the ``npnr`` options which suggest we are using Yosys for synthesis and Nextpnr for placement and routing. Another +After a successful call with the command ``run_FABulous_fabric`` the RTL file of each of the tiles can be found in the ``Tile`` folder and the fabric RTL file can be found in the ``Fabric`` folder. + +After a successful call with the command ``run_FABulous_bitstream npnr user_design/sequential_16bit_en.v``. +The bitstream and all the log files generated during synthesis and place and route can be found under +the ``user_design`` folder. The bitstream will be named as ``sequential_16bit_en.bin`` The above command is using +the ``npnr`` options which suggest we are using Yosys for synthesis and Nextpnr for placement and routing. Another option would be using ``vpr``, which will allow for using Yosys for synthesis and VPR for placement and routing. (currently, the VPR flow is not working after the refactoring) diff --git a/docs/source/simulation/emulation.rst b/docs/source/simulation/emulation.rst index f0232d0c..08071f4e 100644 --- a/docs/source/simulation/emulation.rst +++ b/docs/source/simulation/emulation.rst @@ -3,7 +3,7 @@ Emulation setup (Emulation function is under built) -The script ``bit_gen.py`` in +The script ``bit_gen.py`` in :ref:`bitstream generation` not only generates the binary bitstream for simulation, but also the bitstream files for Verilog and VHDL emulation. @@ -23,8 +23,8 @@ not only generates the binary bitstream for simulation, but also the bitstream f .. code-block:: vhdl :emphasize-lines: 5 - entity eFPGA is - Generic ( + entity eFPGA is + Generic ( MaxFramesPerCol : integer := 20; FrameBitsPerRow : integer := 32; Mode : string := "EMULATE"; -- "ASIC" will use the normal configuration port and "EMULATE" will hardwire a bitstream from emulate_bitstream.vhd