diff --git a/Failed_subcircuits/CD4013/CD4013-cache.lib b/Failed_subcircuits/CD4013/CD4013-cache.lib new file mode 100644 index 000000000..767eb8a0b --- /dev/null +++ b/Failed_subcircuits/CD4013/CD4013-cache.lib @@ -0,0 +1,156 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# buf +# +DEF buf X 0 40 N N 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "buf" -50 50 60 H V C CNN +F2 "" -50 -50 60 H I C CNN +F3 "" -50 -50 60 H I C CNN +DRAW +T 0 -200 50 60 0 0 0 in Normal 0 C C +T 0 200 50 60 0 0 0 out Normal 0 C C +T 900 -50 150 60 0 0 0 v+ Normal 0 C C +T 900 -50 -150 60 0 0 0 v- Normal 0 C C +P 4 0 1 0 -100 100 -100 -100 100 0 -100 100 N +X in 1 -300 0 200 R 50 50 1 1 I +X v+ 2 0 250 200 D 50 50 1 1 I +X v- 3 0 -250 200 U 50 50 1 1 I +X out 4 300 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# inv +# +DEF inv X 0 40 N N 1 F N +F0 "X" -50 -50 60 H V C CNN +F1 "inv" 0 50 60 H V C CNN +F2 "" -50 50 60 H I C CNN +F3 "" -50 50 60 H I C CNN +DRAW +T 0 -200 50 60 0 0 0 in Normal 0 C C +T 0 250 50 60 0 0 0 out Normal 0 C C +T 900 -50 150 60 0 0 0 v+ Normal 0 C C +T 900 -50 -150 60 0 1 0 v- Normal 0 C C +A 125 0 25 1 1799 0 1 0 N 150 0 100 0 +A 125 0 25 -1799 -1 0 1 0 N 100 0 150 0 +P 4 0 1 0 -100 100 -100 -100 100 0 -100 100 N +X in 1 -300 0 200 R 50 50 1 1 I +X V+ 2 0 250 200 D 50 50 1 1 I +X V- 3 0 -250 200 U 50 50 1 1 I +X out 4 350 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# nand +# +DEF nand X 0 40 N N 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "nand" 0 50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +T 0 -200 100 60 0 0 0 in1 Normal 0 C C +T 0 -200 0 60 0 0 0 in2 Normal 0 C C +T 0 250 50 60 0 0 0 out Normal 0 C C +T 900 -50 200 60 0 0 0 V+ Normal 0 C C +T 900 -50 -200 60 0 0 0 V- Normal 0 C C +A 0 0 112 634 -634 0 1 0 N 50 100 50 -100 +A 125 0 25 1 1799 0 1 0 N 150 0 100 0 +A 125 0 25 -1799 -1 0 1 0 N 100 0 150 0 +P 2 0 1 0 -100 100 50 100 N +P 3 0 1 0 -100 100 -100 -100 50 -100 N +X in1 1 -300 50 200 R 50 50 1 1 I +X V+ 2 0 300 200 D 50 50 1 1 I +X V- 3 0 -300 200 U 50 50 1 1 I +X out 4 350 0 200 L 50 50 1 1 O +X in2 5 -300 -50 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# tg +# +DEF tg X 0 40 N N 1 F N +F0 "X" -50 50 60 H V C CNN +F1 "tg" 0 0 60 H V C CNN +F2 "" 550 150 60 H I C CNN +F3 "" 550 150 60 H I C CNN +DRAW +C 0 100 50 0 1 0 N +P 4 0 1 0 -100 0 100 100 100 -100 -100 0 N +P 4 0 1 0 -100 100 -100 -100 100 0 -100 100 N +X inout1 1 -300 0 200 R 50 50 1 1 B +X Cbar 2 0 350 200 D 50 50 1 1 I +X C 3 0 -250 200 U 50 50 1 1 I +X inout2 4 300 0 200 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD4013/CD4013.cir b/Failed_subcircuits/CD4013/CD4013.cir new file mode 100644 index 000000000..507a7ac1e --- /dev/null +++ b/Failed_subcircuits/CD4013/CD4013.cir @@ -0,0 +1,36 @@ +* C:\Users\arpit\coding\esim_projects\CD4013\CD4013.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 08/07/22 20:00:56 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +v1 vdd GND DC +v2 reset GND pulse +v3 Din GND pulse +v4 set GND pulse +v5 clk GND pulse +U4 reset plot_v1 +U1 Din plot_v1 +U3 set plot_v1 +U2 clk plot_v1 +U6 Q plot_v1 +U5 Qbar plot_v1 +X2 reset vdd GND Net-_X14-Pad1_ inv +X1 set vdd GND Net-_X1-Pad4_ inv +X4 Net-_X10-Pad2_ vdd GND Net-_X10-Pad3_ inv +X5 Net-_X11-Pad4_ vdd GND Net-_X13-Pad1_ inv +X3 clk vdd GND Net-_X10-Pad2_ inv +X6 Din Net-_X10-Pad3_ Net-_X10-Pad2_ Net-_X6-Pad4_ tg +X8 Net-_X8-Pad1_ Net-_X10-Pad2_ Net-_X10-Pad3_ Net-_X6-Pad4_ tg +X10 Net-_X10-Pad1_ Net-_X10-Pad2_ Net-_X10-Pad3_ Net-_X10-Pad4_ tg +X15 Net-_X10-Pad1_ Net-_X10-Pad3_ Net-_X10-Pad2_ Net-_X14-Pad4_ tg +X7 Net-_X14-Pad1_ vdd GND Net-_X10-Pad4_ Net-_X6-Pad4_ nand +X9 Net-_X10-Pad4_ vdd GND Net-_X8-Pad1_ Net-_X1-Pad4_ nand +X11 Net-_X10-Pad1_ vdd GND Net-_X11-Pad4_ Net-_X1-Pad4_ nand +X14 Net-_X14-Pad1_ vdd GND Net-_X14-Pad4_ Net-_X11-Pad4_ nand +X13 Net-_X13-Pad1_ vdd GND Q buf +X12 Net-_X10-Pad1_ vdd GND Qbar buf + +.end diff --git a/Failed_subcircuits/CD4013/CD4013.cir.out b/Failed_subcircuits/CD4013/CD4013.cir.out new file mode 100644 index 000000000..270e983d9 --- /dev/null +++ b/Failed_subcircuits/CD4013/CD4013.cir.out @@ -0,0 +1,47 @@ +* c:\users\arpit\coding\esim_projects\cd4013\cd4013.cir + +.include cmos_tg.sub +.include CMOS_inverter.sub +.include cmos_buffer.sub +.include cmos__nand.sub +v1 vdd gnd dc 5 +v2 reset gnd pulse(0 0 0 0 0 10n 200n) +v3 din gnd pulse(0 5 0 0 0 25n 50n) +v4 set gnd pulse(0 5 0 0 0 10n 400n) +v5 clk gnd pulse(0 5 0 0 0 7.5n 15n) +* u4 reset plot_v1 +* u1 din plot_v1 +* u3 set plot_v1 +* u2 clk plot_v1 +* u6 q plot_v1 +* u5 qbar plot_v1 +x2 reset vdd gnd net-_x14-pad1_ CMOS_inverter +x1 set vdd gnd net-_x1-pad4_ CMOS_inverter +x4 net-_x10-pad2_ vdd gnd net-_x10-pad3_ CMOS_inverter +x5 net-_x11-pad4_ vdd gnd net-_x13-pad1_ CMOS_inverter +x3 clk vdd gnd net-_x10-pad2_ CMOS_inverter +x6 din net-_x10-pad3_ net-_x10-pad2_ net-_x6-pad4_ cmos_tg +x8 net-_x8-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_x6-pad4_ cmos_tg +x10 net-_x10-pad1_ net-_x10-pad2_ net-_x10-pad3_ net-_x10-pad4_ cmos_tg +x15 net-_x10-pad1_ net-_x10-pad3_ net-_x10-pad2_ net-_x14-pad4_ cmos_tg +x7 net-_x14-pad1_ vdd gnd net-_x10-pad4_ net-_x6-pad4_ cmos__nand +x9 net-_x10-pad4_ vdd gnd net-_x8-pad1_ net-_x1-pad4_ cmos__nand +x11 net-_x10-pad1_ vdd gnd net-_x11-pad4_ net-_x1-pad4_ cmos__nand +x14 net-_x14-pad1_ vdd gnd net-_x14-pad4_ net-_x11-pad4_ cmos__nand +x13 net-_x13-pad1_ vdd gnd q cmos_buffer +x12 net-_x10-pad1_ vdd gnd qbar cmos_buffer +.tran 0.1e-09 400e-09 0e-09 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(reset) +plot v(din) +plot v(set) +plot v(clk) +plot v(q) +plot v(qbar) +.endc +.end diff --git a/Failed_subcircuits/CD4013/CD4013.pro b/Failed_subcircuits/CD4013/CD4013.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD4013/CD4013.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD4013/CD4013.proj b/Failed_subcircuits/CD4013/CD4013.proj new file mode 100644 index 000000000..044b391c2 --- /dev/null +++ b/Failed_subcircuits/CD4013/CD4013.proj @@ -0,0 +1 @@ +schematicFile CD4013.sch diff --git a/Failed_subcircuits/CD4013/CD4013.sch b/Failed_subcircuits/CD4013/CD4013.sch new file mode 100644 index 000000000..5131884a5 --- /dev/null +++ b/Failed_subcircuits/CD4013/CD4013.sch @@ -0,0 +1,606 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD4013-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 3100 2550 3550 2550 +Wire Wire Line + 3100 1700 3900 1700 +Wire Wire Line + 3100 4100 4150 4100 +$Comp +L DC v1 +U 1 1 62EA7EE6 +P 2650 1350 +F 0 "v1" H 2450 1450 60 0000 C CNN +F 1 "DC" H 2450 1300 60 0000 C CNN +F 2 "R1" H 2350 1350 60 0000 C CNN +F 3 "" H 2650 1350 60 0000 C CNN + 1 2650 1350 + 0 1 1 0 +$EndComp +$Comp +L pulse v2 +U 1 1 62EA80D0 +P 2650 1700 +F 0 "v2" H 2450 1800 60 0000 C CNN +F 1 "pulse" H 2450 1650 60 0000 C CNN +F 2 "R1" H 2350 1700 60 0000 C CNN +F 3 "" H 2650 1700 60 0000 C CNN + 1 2650 1700 + 0 1 -1 0 +$EndComp +$Comp +L pulse v3 +U 1 1 62EA8161 +P 2650 2550 +F 0 "v3" H 2450 2650 60 0000 C CNN +F 1 "pulse" H 2450 2500 60 0000 C CNN +F 2 "R1" H 2350 2550 60 0000 C CNN +F 3 "" H 2650 2550 60 0000 C CNN + 1 2650 2550 + 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2150 +Wire Wire Line + 9450 2150 9900 2150 +Wire Wire Line + 6950 2150 6950 4050 +Wire Wire Line + 6950 2600 9250 2600 +Connection ~ 6950 2150 +Wire Wire Line + 9100 4350 9100 2450 +Connection ~ 8750 4350 +Wire Wire Line + 9900 2150 9900 2600 +Wire Wire Line + 9900 2600 9850 2600 +Wire Wire Line + 3850 2800 3850 2900 +Wire Wire Line + 3850 2900 5000 2900 +Wire Wire Line + 5000 2900 5000 4100 +Connection ~ 5000 4100 +Wire Wire Line + 5900 3600 5900 3750 +Wire Wire Line + 6600 3750 5000 3750 +Connection ~ 5000 3750 +Wire Wire Line + 6600 2500 6600 3750 +Connection ~ 5900 3750 +Wire Wire Line + 5800 4100 7800 4100 +Wire Wire Line + 7800 4100 7800 1500 +Wire Wire Line + 3850 1500 9550 1500 +Wire Wire Line + 9550 1500 9550 2250 +Wire Wire Line + 6600 1500 6600 1900 +Connection ~ 7800 1500 +Wire Wire Line + 5900 1500 5900 3000 +Connection ~ 6600 1500 +Wire Wire Line + 3850 1500 3850 2200 +Connection ~ 5900 1500 +Wire Wire Line + 8100 2700 8100 1350 +Connection ~ 8100 1350 +Wire Wire Line + 8100 3200 8100 3400 +Wire Wire Line + 7700 2200 7700 2950 +Wire Wire Line + 7700 2950 7800 2950 +Connection ~ 7700 2200 +Wire Wire Line + 8450 2950 8450 3650 +Connection ~ 6950 2600 +Wire Wire Line + 8100 3400 7900 3400 +Wire Wire Line + 7900 3400 7900 4350 +Connection ~ 7900 4350 +Wire Wire Line + 2150 1350 2150 4500 +Wire Wire Line + 3150 1350 3150 1100 +Connection ~ 3150 1350 +Wire Wire Line + 9750 4000 9750 4050 +Connection ~ 9750 4050 +Connection ~ 3200 3550 +Wire Wire Line + 3200 2500 3200 2550 +Connection ~ 3200 2550 +Wire Wire Line + 3300 1700 3300 1700 +Connection ~ 3300 1700 +Connection ~ 3250 3550 +Wire Wire Line + 3200 4050 3200 4100 +Connection ~ 3200 4100 +Connection ~ 2150 4100 +Connection ~ 2150 4350 +$Comp +L GND #PWR1 +U 1 1 62EC235C +P 2150 4500 +F 0 "#PWR1" H 2150 4250 50 0001 C CNN +F 1 "GND" H 2150 4350 50 0000 C CNN +F 2 "" H 2150 4500 50 0001 C CNN +F 3 "" H 2150 4500 50 0001 C CNN + 1 2150 4500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9550 2850 9550 3200 +Wire Wire Line + 9550 3200 6600 3200 +Connection ~ 6600 3200 +Wire Wire Line + 2200 3550 2150 3550 +Wire Wire Line + 2200 4100 2150 4100 +$Comp +L tg X6 +U 1 1 62EFC8AF +P 3850 2550 +F 0 "X6" H 3800 2600 60 0000 C CNN +F 1 "tg" H 3850 2550 60 0000 C CNN +F 2 "" H 4400 2700 60 0001 C CNN +F 3 "" H 4400 2700 60 0001 C CNN + 1 3850 2550 + 1 0 0 -1 +$EndComp +$Comp +L tg X8 +U 1 1 62EFCB7B +P 5900 3250 +F 0 "X8" H 5850 3300 60 0000 C CNN +F 1 "tg" H 5900 3250 60 0000 C CNN +F 2 "" H 6450 3400 60 0001 C CNN +F 3 "" H 6450 3400 60 0001 C CNN + 1 5900 3250 + -1 0 0 1 +$EndComp +$Comp +L tg X10 +U 1 1 62EFD004 +P 6600 2150 +F 0 "X10" H 6550 2200 60 0000 C CNN +F 1 "tg" H 6600 2150 60 0000 C CNN +F 2 "" H 7150 2300 60 0001 C CNN +F 3 "" H 7150 2300 60 0001 C CNN + 1 6600 2150 + -1 0 0 1 +$EndComp +$Comp +L tg X15 +U 1 1 62EFD45B +P 9550 2600 +F 0 "X15" H 9500 2650 60 0000 C CNN +F 1 "tg" H 9550 2600 60 0000 C CNN +F 2 "" H 10100 2750 60 0001 C CNN +F 3 "" H 10100 2750 60 0001 C CNN + 1 9550 2600 + 1 0 0 -1 +$EndComp +$Comp +L nand X7 +U 1 1 62EFD7E3 +P 5150 2500 +F 0 "X7" H 5150 2450 60 0000 C CNN +F 1 "nand" H 5150 2550 60 0000 C CNN +F 2 "" H 5150 2450 60 0001 C CNN +F 3 "" H 5150 2450 60 0001 C CNN + 1 5150 2500 + 1 0 0 -1 +$EndComp +$Comp +L nand X9 +U 1 1 62EFD881 +P 6150 2550 +F 0 "X9" H 6150 2500 60 0000 C CNN +F 1 "nand" H 6150 2600 60 0000 C CNN +F 2 "" H 6150 2500 60 0001 C CNN +F 3 "" H 6150 2500 60 0001 C CNN + 1 6150 2550 + 1 0 0 -1 +$EndComp +$Comp +L nand X11 +U 1 1 62EFD9D8 +P 7300 2200 +F 0 "X11" H 7300 2150 60 0000 C CNN +F 1 "nand" H 7300 2250 60 0000 C CNN +F 2 "" H 7300 2150 60 0001 C CNN +F 3 "" H 7300 2150 60 0001 C CNN + 1 7300 2200 + 1 0 0 -1 +$EndComp +$Comp +L nand X14 +U 1 1 62EFDC2E +P 9100 2150 +F 0 "X14" H 9100 2100 60 0000 C CNN +F 1 "nand" H 9100 2200 60 0000 C CNN +F 2 "" H 9100 2100 60 0001 C CNN +F 3 "" H 9100 2100 60 0001 C CNN + 1 9100 2150 + 1 0 0 -1 +$EndComp +$Comp +L buf X13 +U 1 1 62EFD06F +P 8750 3650 +F 0 "X13" H 8700 3600 60 0000 C CNN +F 1 "buf" H 8700 3700 60 0000 C CNN +F 2 "" H 8700 3600 60 0001 C CNN +F 3 "" H 8700 3600 60 0001 C CNN + 1 8750 3650 + 1 0 0 -1 +$EndComp +$Comp +L buf X12 +U 1 1 62EFD187 +P 8250 4050 +F 0 "X12" H 8200 4000 60 0000 C CNN +F 1 "buf" H 8200 4100 60 0000 C CNN +F 2 "" H 8200 4000 60 0001 C CNN +F 3 "" H 8200 4000 60 0001 C CNN + 1 8250 4050 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9050 3650 10200 3650 +Wire Wire Line + 6950 4050 7950 4050 +$EndSCHEMATC diff --git a/Failed_subcircuits/CD4013/CD4013_Previous_Values.xml b/Failed_subcircuits/CD4013/CD4013_Previous_Values.xml new file mode 100644 index 000000000..937a31bd8 --- /dev/null +++ b/Failed_subcircuits/CD4013/CD4013_Previous_Values.xml @@ -0,0 +1 @@ +dc5pulse0010n200npulse0525n50npulse0510n400npulse057.5n15nC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tgC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tgC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tgC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tgC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nandC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nandC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nandC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nandC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_bufferC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_buffertruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.1400nsnsns \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/CMOS_inverter-cache.lib b/Failed_subcircuits/CD4013/CMOS_inverter-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/Failed_subcircuits/CD4013/CMOS_inverter-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD4013/CMOS_inverter.cir b/Failed_subcircuits/CD4013/CMOS_inverter.cir new file mode 100644 index 000000000..efc3276f7 --- /dev/null +++ b/Failed_subcircuits/CD4013/CMOS_inverter.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverter\CMOS_inverter.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:13:55 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad1_ PORT + +.end diff --git a/Failed_subcircuits/CD4013/CMOS_inverter.cir.out b/Failed_subcircuits/CD4013/CMOS_inverter.cir.out new file mode 100644 index 000000000..c6df11d6d --- /dev/null +++ b/Failed_subcircuits/CD4013/CMOS_inverter.cir.out @@ -0,0 +1,16 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_inverter\cmos_inverter.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m2-pad3_ net-_m1-pad3_ net-_m1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD4013/CMOS_inverter.pro b/Failed_subcircuits/CD4013/CMOS_inverter.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD4013/CMOS_inverter.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD4013/CMOS_inverter.sch b/Failed_subcircuits/CD4013/CMOS_inverter.sch new file mode 100644 index 000000000..ece0f26e2 --- /dev/null +++ b/Failed_subcircuits/CD4013/CMOS_inverter.sch @@ -0,0 +1,149 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CMOS_inverter-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 62DA908D +P 5150 2200 +F 0 "M2" H 5100 2250 50 0000 R CNN +F 1 "mosfet_p" H 5200 2350 50 0000 R CNN +F 2 "" H 5400 2300 29 0000 C CNN +F 3 "" H 5200 2200 60 0000 C CNN + 1 5150 2200 + 1 0 0 1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62DA908E +P 5100 2800 +F 0 "M1" H 5100 2650 50 0000 R CNN +F 1 "mosfet_n" H 5200 2750 50 0000 R CNN +F 2 "" H 5400 2500 29 0000 C CNN +F 3 "" H 5200 2600 60 0000 C CNN + 1 5100 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 2000 5300 1650 +Wire Wire Line + 5300 1800 5400 1800 +Wire Wire Line + 5400 1800 5400 2050 +Connection ~ 5300 1800 +Wire Wire Line + 5300 3200 5300 3600 +Wire Wire Line + 5400 3150 5400 3350 +Wire Wire Line + 5400 3350 5300 3350 +Connection ~ 5300 3350 +Wire Wire Line + 5000 2200 4800 2200 +Wire Wire Line + 4800 2200 4800 3000 +Wire Wire Line + 4800 3000 5000 3000 +Wire Wire Line + 5300 2400 5300 2800 +Wire Wire Line + 5300 2600 5900 2600 +Connection ~ 5300 2600 +Wire Wire Line + 4800 2600 4300 2600 +Connection ~ 4800 2600 +$Comp +L PORT U1 +U 2 1 62DA908F +P 5300 1400 +F 0 "U1" H 5350 1500 30 0000 C CNN +F 1 "PORT" H 5300 1400 30 0000 C CNN +F 2 "" H 5300 1400 60 0000 C CNN +F 3 "" H 5300 1400 60 0000 C CNN + 2 5300 1400 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA9090 +P 5300 3850 +F 0 "U1" H 5350 3950 30 0000 C CNN +F 1 "PORT" H 5300 3850 30 0000 C CNN +F 2 "" H 5300 3850 60 0000 C CNN +F 3 "" H 5300 3850 60 0000 C CNN + 3 5300 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 62DA9091 +P 4050 2600 +F 0 "U1" H 4100 2700 30 0000 C CNN +F 1 "PORT" H 4050 2600 30 0000 C CNN +F 2 "" H 4050 2600 60 0000 C CNN +F 3 "" H 4050 2600 60 0000 C CNN + 1 4050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62DA9092 +P 6150 2600 +F 0 "U1" H 6200 2700 30 0000 C CNN +F 1 "PORT" H 6150 2600 30 0000 C CNN +F 2 "" H 6150 2600 60 0000 C CNN +F 3 "" H 6150 2600 60 0000 C CNN + 4 6150 2600 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/Failed_subcircuits/CD4013/CMOS_inverter.sub b/Failed_subcircuits/CD4013/CMOS_inverter.sub new file mode 100644 index 000000000..a04225173 --- /dev/null +++ b/Failed_subcircuits/CD4013/CMOS_inverter.sub @@ -0,0 +1,10 @@ +* Subcircuit CMOS_inverter +.subckt CMOS_inverter net-_m1-pad2_ net-_m2-pad3_ net-_m1-pad3_ net-_m1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_inverter\cmos_inverter.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CMOS_inverter \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/CMOS_inverter_Previous_Values.xml b/Failed_subcircuits/CD4013/CMOS_inverter_Previous_Values.xml new file mode 100644 index 000000000..0388b42b0 --- /dev/null +++ b/Failed_subcircuits/CD4013/CMOS_inverter_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/NMOS-180nm.lib b/Failed_subcircuits/CD4013/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/Failed_subcircuits/CD4013/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/Failed_subcircuits/CD4013/PMOS-180nm.lib b/Failed_subcircuits/CD4013/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/Failed_subcircuits/CD4013/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/Failed_subcircuits/CD4013/README.md b/Failed_subcircuits/CD4013/README.md new file mode 100644 index 000000000..cead83c50 --- /dev/null +++ b/Failed_subcircuits/CD4013/README.md @@ -0,0 +1,35 @@ + +# CD4013 CMOS Dual D-Flip Flop IC + +CD4013 is a digital IC, containing two identical D Flip Flops with Data, Set, Reset and Clock as Input Signals; Q and Q bar as outputs. + + +## Usage/Examples + +Counters + +Data registers + +Shift registers + +Frequency Dividers + + +## Documentation + +To know the details of CD4013 IC please refer to this link [CD4013_datasheet.](https://www.ti.com/lit/ds/symlink/cd4013b.pdf) + +## Error observed + +The output obtained is very erratic and noisy. + +## Possible Solution + +The W/L Ratio of the components used in the design can be optimised/reconfigured in order to obtain desired performance. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/analysis b/Failed_subcircuits/CD4013/analysis new file mode 100644 index 000000000..55a27cb8b --- /dev/null +++ b/Failed_subcircuits/CD4013/analysis @@ -0,0 +1 @@ +.tran 0.1e-09 400e-09 0e-09 \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/cmos__nand-cache.lib b/Failed_subcircuits/CD4013/cmos__nand-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos__nand-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD4013/cmos__nand.cir b/Failed_subcircuits/CD4013/cmos__nand.cir new file mode 100644 index 000000000..74d63f52f --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos__nand.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nand\cmos__nand.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:20:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad4_ mosfet_n +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M2-Pad4_ Net-_M2-Pad4_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad4_ Net-_M1-Pad1_ Net-_M3-Pad2_ PORT + +.end diff --git a/Failed_subcircuits/CD4013/cmos__nand.cir.out b/Failed_subcircuits/CD4013/cmos__nand.cir.out new file mode 100644 index 000000000..d5ec37173 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos__nand.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos__nand\cmos__nand.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m2-pad4_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m1-pad3_ net-_m2-pad4_ net-_m1-pad1_ net-_m3-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD4013/cmos__nand.pro b/Failed_subcircuits/CD4013/cmos__nand.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos__nand.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD4013/cmos__nand.sch b/Failed_subcircuits/CD4013/cmos__nand.sch new file mode 100644 index 000000000..7c5df3c1e --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos__nand.sch @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:cmos__nand-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M1 +U 1 1 62DA9263 +P 5400 2750 +F 0 "M1" H 5350 2800 50 0000 R CNN +F 1 "mosfet_p" H 5450 2900 50 0000 R CNN +F 2 "" H 5650 2850 29 0000 C CNN +F 3 "" H 5450 2750 60 0000 C CNN + 1 5400 2750 + 1 0 0 1 +$EndComp +$Comp +L mosfet_p M4 +U 1 1 62DA9264 +P 6350 2750 +F 0 "M4" H 6300 2800 50 0000 R CNN +F 1 "mosfet_p" H 6400 2900 50 0000 R CNN +F 2 "" H 6600 2850 29 0000 C CNN +F 3 "" H 6400 2750 60 0000 C CNN + 1 6350 2750 + -1 0 0 1 +$EndComp +$Comp +L mosfet_n M2 +U 1 1 62DA9265 +P 5700 3250 +F 0 "M2" H 5700 3100 50 0000 R CNN +F 1 "mosfet_n" H 5800 3200 50 0000 R CNN +F 2 "" H 6000 2950 29 0000 C CNN +F 3 "" H 5800 3050 60 0000 C CNN + 1 5700 3250 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M3 +U 1 1 62DA9266 +P 6100 3750 +F 0 "M3" H 6100 3600 50 0000 R CNN +F 1 "mosfet_n" H 6200 3700 50 0000 R CNN +F 2 "" H 6400 3450 29 0000 C CNN +F 3 "" H 6200 3550 60 0000 C CNN + 1 6100 3750 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5550 2950 5550 3050 +Wire Wire Line + 5550 3050 6200 3050 +Wire Wire Line + 6200 3050 6200 2950 +Wire Wire Line + 5900 3050 5900 3250 +Connection ~ 5900 3050 +Wire Wire Line + 5900 3650 5900 3750 +Wire Wire Line + 5900 4150 5900 4450 +Wire Wire Line + 5800 4100 5800 4250 +Wire Wire Line + 5700 4250 5900 4250 +Connection ~ 5900 4250 +Wire Wire Line + 6000 3600 6000 3700 +Wire Wire Line + 6000 3700 5700 3700 +Wire Wire Line + 5700 3700 5700 4250 +Connection ~ 5800 4250 +Wire Wire Line + 5550 2550 5550 2400 +Wire Wire Line + 5550 2400 6200 2400 +Wire Wire Line + 6200 2400 6200 2550 +Wire Wire Line + 5650 2600 5650 2400 +Connection ~ 5650 2400 +Wire Wire Line + 6100 2600 6100 2400 +Connection ~ 6100 2400 +Wire Wire Line + 5900 2400 5900 2200 +Connection ~ 5900 2400 +Wire Wire Line + 5250 2750 5250 3450 +Wire Wire Line + 5250 3450 5600 3450 +Wire Wire Line + 6500 2750 6500 3950 +Wire Wire Line + 6500 3950 6200 3950 +Wire Wire Line + 6500 3350 7150 3350 +Connection ~ 6500 3350 +Wire Wire Line + 5250 3050 4900 3050 +Connection ~ 5250 3050 +Wire Wire Line + 5900 3150 6800 3150 +Connection ~ 5900 3150 +$Comp +L PORT U1 +U 1 1 62DA9267 +P 4650 3050 +F 0 "U1" H 4700 3150 30 0000 C CNN +F 1 "PORT" H 4650 3050 30 0000 C CNN +F 2 "" H 4650 3050 60 0000 C CNN +F 3 "" H 4650 3050 60 0000 C CNN + 1 4650 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62DA9268 +P 5900 1950 +F 0 "U1" H 5950 2050 30 0000 C CNN +F 1 "PORT" H 5900 1950 30 0000 C CNN +F 2 "" H 5900 1950 60 0000 C CNN +F 3 "" H 5900 1950 60 0000 C CNN + 2 5900 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA9269 +P 5900 4700 +F 0 "U1" H 5950 4800 30 0000 C CNN +F 1 "PORT" H 5900 4700 30 0000 C CNN +F 2 "" H 5900 4700 60 0000 C CNN +F 3 "" H 5900 4700 60 0000 C CNN + 3 5900 4700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 62DA926A +P 7400 3350 +F 0 "U1" H 7450 3450 30 0000 C CNN +F 1 "PORT" H 7400 3350 30 0000 C CNN +F 2 "" H 7400 3350 60 0000 C CNN +F 3 "" H 7400 3350 60 0000 C CNN + 5 7400 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62DA926B +P 7050 3150 +F 0 "U1" H 7100 3250 30 0000 C CNN +F 1 "PORT" H 7050 3150 30 0000 C CNN +F 2 "" H 7050 3150 60 0000 C CNN +F 3 "" H 7050 3150 60 0000 C CNN + 4 7050 3150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/Failed_subcircuits/CD4013/cmos__nand.sub b/Failed_subcircuits/CD4013/cmos__nand.sub new file mode 100644 index 000000000..f47823eeb --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos__nand.sub @@ -0,0 +1,12 @@ +* Subcircuit cmos__nand +.subckt cmos__nand net-_m1-pad2_ net-_m1-pad3_ net-_m2-pad4_ net-_m1-pad1_ net-_m3-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\cmos__nand\cmos__nand.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m2-pad4_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cmos__nand \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/cmos__nand_Previous_Values.xml b/Failed_subcircuits/CD4013/cmos__nand_Previous_Values.xml new file mode 100644 index 000000000..f43eb2d54 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos__nand_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/cmos_buffer-cache.lib b/Failed_subcircuits/CD4013/cmos_buffer-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_buffer-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD4013/cmos_buffer.cir b/Failed_subcircuits/CD4013/cmos_buffer.cir new file mode 100644 index 000000000..07e1bfbfa --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_buffer.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_buffer\cmos_buffer.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 08/07/22 19:48:01 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M4 Net-_M3-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p +M3 Net-_M3-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M1-Pad3_ Net-_M3-Pad1_ PORT + +.end diff --git a/Failed_subcircuits/CD4013/cmos_buffer.cir.out b/Failed_subcircuits/CD4013/cmos_buffer.cir.out new file mode 100644 index 000000000..8ca59f9f9 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_buffer.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_buffer\cmos_buffer.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m4 net-_m3-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m2-pad3_ net-_m1-pad3_ net-_m3-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD4013/cmos_buffer.pro b/Failed_subcircuits/CD4013/cmos_buffer.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_buffer.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD4013/cmos_buffer.sch b/Failed_subcircuits/CD4013/cmos_buffer.sch new file mode 100644 index 000000000..778621398 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_buffer.sch @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:cmos_buffer-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M4 +U 1 1 62DA98C4 +P 5800 2950 +F 0 "M4" H 5750 3000 50 0000 R CNN +F 1 "mosfet_p" H 5850 3100 50 0000 R CNN +F 2 "" H 6050 3050 29 0000 C CNN +F 3 "" H 5850 2950 60 0000 C CNN + 1 5800 2950 + 1 0 0 1 +$EndComp +$Comp +L mosfet_n M3 +U 1 1 62DA98C5 +P 5750 3550 +F 0 "M3" H 5750 3400 50 0000 R CNN +F 1 "mosfet_n" H 5850 3500 50 0000 R CNN +F 2 "" H 6050 3250 29 0000 C CNN +F 3 "" H 5850 3350 60 0000 C CNN + 1 5750 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 2500 5950 2750 +Wire Wire Line + 5950 2650 6050 2650 +Wire Wire Line + 6050 2650 6050 2800 +Connection ~ 5950 2650 +Wire Wire Line + 5950 4200 5950 3950 +Wire Wire Line + 6050 3900 6050 4100 +Wire Wire Line + 6050 4100 5950 4100 +Connection ~ 5950 4100 +Wire Wire Line + 5650 2950 5650 3750 +Wire Wire Line + 5950 3150 5950 3550 +Wire Wire Line + 5950 3350 6050 3350 +Connection ~ 5950 3350 +Wire Wire Line + 5050 3350 5650 3350 +Connection ~ 5650 3350 +$Comp +L mosfet_p M2 +U 1 1 62DA98C9 +P 4900 2950 +F 0 "M2" H 4850 3000 50 0000 R CNN +F 1 "mosfet_p" H 4950 3100 50 0000 R CNN +F 2 "" H 5150 3050 29 0000 C CNN +F 3 "" H 4950 2950 60 0000 C CNN + 1 4900 2950 + 1 0 0 1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62DA98CA +P 4850 3550 +F 0 "M1" H 4850 3400 50 0000 R CNN +F 1 "mosfet_n" H 4950 3500 50 0000 R CNN +F 2 "" H 5150 3250 29 0000 C CNN +F 3 "" H 4950 3350 60 0000 C CNN + 1 4850 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 2500 5050 2750 +Wire Wire Line + 5050 2650 5150 2650 +Wire Wire Line + 5150 2650 5150 2800 +Connection ~ 5050 2650 +Wire Wire Line + 5050 3950 5050 4200 +Wire Wire Line + 5150 3900 5150 4100 +Wire Wire Line + 5150 4100 5050 4100 +Connection ~ 5050 4100 +Wire Wire Line + 4750 2950 4750 3750 +Wire Wire Line + 5050 3150 5050 3550 +Connection ~ 5050 3350 +Wire Wire Line + 4750 3350 4600 3350 +Connection ~ 4750 3350 +Wire Wire Line + 5050 4200 5950 4200 +Wire Wire Line + 5500 4350 5500 4200 +Connection ~ 5500 4200 +Wire Wire Line + 5050 2500 5950 2500 +Wire Wire Line + 5500 2300 5500 2500 +Connection ~ 5500 2500 +$Comp +L PORT U1 +U 1 1 62EFC9E1 +P 4350 3350 +F 0 "U1" H 4400 3450 30 0000 C CNN +F 1 "PORT" H 4350 3350 30 0000 C CNN +F 2 "" H 4350 3350 60 0000 C CNN +F 3 "" H 4350 3350 60 0000 C CNN + 1 4350 3350 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 62EFCA6F +P 5500 4600 +F 0 "U1" H 5550 4700 30 0000 C CNN +F 1 "PORT" H 5500 4600 30 0000 C CNN +F 2 "" H 5500 4600 60 0000 C CNN +F 3 "" H 5500 4600 60 0000 C CNN + 3 5500 4600 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 62EFCB16 +P 5500 2050 +F 0 "U1" H 5550 2150 30 0000 C CNN +F 1 "PORT" H 5500 2050 30 0000 C CNN +F 2 "" H 5500 2050 60 0000 C CNN +F 3 "" H 5500 2050 60 0000 C CNN + 2 5500 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 62EFCB8F +P 6300 3350 +F 0 "U1" H 6350 3450 30 0000 C CNN +F 1 "PORT" H 6300 3350 30 0000 C CNN +F 2 "" H 6300 3350 60 0000 C CNN +F 3 "" H 6300 3350 60 0000 C CNN + 4 6300 3350 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/Failed_subcircuits/CD4013/cmos_buffer.sub b/Failed_subcircuits/CD4013/cmos_buffer.sub new file mode 100644 index 000000000..5a28b2d22 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_buffer.sub @@ -0,0 +1,12 @@ +* Subcircuit cmos_buffer +.subckt cmos_buffer net-_m1-pad2_ net-_m2-pad3_ net-_m1-pad3_ net-_m3-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_buffer\cmos_buffer.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m4 net-_m3-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cmos_buffer \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/cmos_buffer_Previous_Values.xml b/Failed_subcircuits/CD4013/cmos_buffer_Previous_Values.xml new file mode 100644 index 000000000..4744e2195 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_buffer_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/cmos_tg-cache.lib b/Failed_subcircuits/CD4013/cmos_tg-cache.lib new file mode 100644 index 000000000..4f6bd0acf --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_tg-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD4013/cmos_tg.cir b/Failed_subcircuits/CD4013/cmos_tg.cir new file mode 100644 index 000000000..5126e30c2 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_tg.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tg\cmos_tg.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:31:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad1_ Net-_M1-Pad2_ mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND mosfet_n +U1 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M1-Pad3_ PORT + +.end diff --git a/Failed_subcircuits/CD4013/cmos_tg.cir.out b/Failed_subcircuits/CD4013/cmos_tg.cir.out new file mode 100644 index 000000000..44fe2c288 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_tg.cir.out @@ -0,0 +1,16 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_tg\cmos_tg.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad1_ net-_m1-pad2_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad2_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD4013/cmos_tg.pro b/Failed_subcircuits/CD4013/cmos_tg.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_tg.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD4013/cmos_tg.sch b/Failed_subcircuits/CD4013/cmos_tg.sch new file mode 100644 index 000000000..92a4f7ae3 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_tg.sch @@ -0,0 +1,163 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:cmos_tg-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 62DA99E3 +P 5850 2700 +F 0 "M2" H 5800 2750 50 0000 R CNN +F 1 "mosfet_p" H 5900 2850 50 0000 R CNN +F 2 "" H 6100 2800 29 0000 C CNN +F 3 "" H 5900 2700 60 0000 C CNN + 1 5850 2700 + 0 1 1 0 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62DA99E4 +P 5650 3850 +F 0 "M1" H 5650 3700 50 0000 R CNN +F 1 "mosfet_n" H 5750 3800 50 0000 R CNN +F 2 "" H 5950 3550 29 0000 C CNN +F 3 "" H 5750 3650 60 0000 C CNN + 1 5650 3850 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5400 3650 5650 3650 +Wire Wire Line + 5400 2850 5400 3650 +Wire Wire Line + 5400 2850 5650 2850 +Wire Wire Line + 6300 3650 6050 3650 +Wire Wire Line + 6300 2850 6300 3650 +Wire Wire Line + 6300 2850 6050 2850 +Wire Wire Line + 6300 3250 6500 3250 +Connection ~ 6300 3250 +Wire Wire Line + 5400 3200 5200 3200 +Connection ~ 5400 3200 +Wire Wire Line + 5850 2550 5850 2350 +Wire Wire Line + 5850 3950 5850 4200 +$Comp +L GND #PWR1 +U 1 1 62DA99E5 +P 6150 3550 +F 0 "#PWR1" H 6150 3300 50 0001 C CNN +F 1 "GND" H 6150 3400 50 0000 C CNN +F 2 "" H 6150 3550 50 0001 C CNN +F 3 "" H 6150 3550 50 0001 C CNN + 1 6150 3550 + -1 0 0 1 +$EndComp +Wire Wire Line + 6150 3550 6000 3550 +Wire Wire Line + 5700 2950 5550 2950 +Wire Wire Line + 5550 2950 5550 4000 +Wire Wire Line + 5550 4000 5850 4000 +Connection ~ 5850 4000 +$Comp +L PORT U1 +U 1 1 62DA99E6 +P 4950 3200 +F 0 "U1" H 5000 3300 30 0000 C CNN +F 1 "PORT" H 4950 3200 30 0000 C CNN +F 2 "" H 4950 3200 60 0000 C CNN +F 3 "" H 4950 3200 60 0000 C CNN + 1 4950 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62DA99E7 +P 5850 2100 +F 0 "U1" H 5900 2200 30 0000 C CNN +F 1 "PORT" H 5850 2100 30 0000 C CNN +F 2 "" H 5850 2100 60 0000 C CNN +F 3 "" H 5850 2100 60 0000 C CNN + 2 5850 2100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA99E8 +P 5850 4450 +F 0 "U1" H 5900 4550 30 0000 C CNN +F 1 "PORT" H 5850 4450 30 0000 C CNN +F 2 "" H 5850 4450 60 0000 C CNN +F 3 "" H 5850 4450 60 0000 C CNN + 3 5850 4450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 62DA99E9 +P 6750 3250 +F 0 "U1" H 6800 3350 30 0000 C CNN +F 1 "PORT" H 6750 3250 30 0000 C CNN +F 2 "" H 6750 3250 60 0000 C CNN +F 3 "" H 6750 3250 60 0000 C CNN + 4 6750 3250 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/Failed_subcircuits/CD4013/cmos_tg.sub b/Failed_subcircuits/CD4013/cmos_tg.sub new file mode 100644 index 000000000..fe9ff9579 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_tg.sub @@ -0,0 +1,10 @@ +* Subcircuit cmos_tg +.subckt cmos_tg net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad2_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_tg\cmos_tg.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad1_ net-_m1-pad2_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cmos_tg \ No newline at end of file diff --git a/Failed_subcircuits/CD4013/cmos_tg_Previous_Values.xml b/Failed_subcircuits/CD4013/cmos_tg_Previous_Values.xml new file mode 100644 index 000000000..0388b42b0 --- /dev/null +++ b/Failed_subcircuits/CD4013/cmos_tg_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/CD_4027-cache.lib b/Failed_subcircuits/CD_4027/CD_4027-cache.lib new file mode 100644 index 000000000..012a44109 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CD_4027-cache.lib @@ -0,0 +1,217 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# DC +# +DEF DC v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "DC" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 w +X - 2 0 -450 300 U 50 50 1 1 w +ENDDRAW +ENDDEF +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# TG +# +DEF TG X 0 40 N N 1 F N +F0 "X" -50 0 60 H V C CNN +F1 "TG" 50 0 60 H V C CNN +F2 "" -100 300 60 H I C CNN +F3 "" -100 300 60 H I C CNN +DRAW +A 0 100 50 1 1799 0 1 0 N 50 100 -50 100 +A 0 100 50 -1799 -1 0 1 0 N -50 100 50 100 +P 5 0 1 0 -100 100 -100 -100 100 100 100 -100 -100 100 N +X in1 1 -300 0 200 R 50 50 1 1 B +X C' 2 0 300 200 D 50 50 1 1 I +X C 3 0 -250 200 U 50 50 1 1 I +X in2 4 300 0 200 L 50 50 1 1 B +ENDDRAW +ENDDEF +# +# and +# +DEF and x 0 40 N N 1 F N +F0 "x" 0 -50 60 H V C CNN +F1 "and" 0 50 60 H V C CNN +F2 "" 950 400 60 H I C CNN +F3 "" 950 400 60 H I C CNN +DRAW +T 0 -200 100 60 0 0 0 in1 Normal 0 C C +T 0 -200 -100 60 0 0 0 in2 Normal 0 C C +T 0 250 50 60 0 0 0 out Normal 0 C C +T 900 -50 200 60 0 0 0 v+ Normal 0 C C +T 900 -50 -200 60 0 0 0 v- Normal 0 C C +A 50 0 112 634 -634 0 1 0 N 100 100 100 -100 +P 4 0 1 0 100 100 -100 100 -100 -100 100 -100 N +X in1 1 -300 50 200 R 50 50 1 1 I +X v- 2 0 -300 200 U 50 50 1 1 I +X v+ 3 0 300 200 D 50 50 1 1 I +X in2 4 -300 -50 200 R 50 50 1 1 I +X out 5 350 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# buf-RESCUE-CD_4027 +# +DEF buf-RESCUE-CD_4027 X 0 40 N N 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "buf-RESCUE-CD_4027" 0 50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +T 0 -150 50 60 0 0 0 in Normal 0 C C +T 0 200 50 60 0 0 0 out Normal 0 C C +T 0 50 150 60 0 0 0 v+ Normal 0 C C +T 0 50 -150 60 0 0 0 v- Normal 0 C C +P 4 0 1 0 -50 100 -50 -100 100 0 -50 100 N +X in 1 -250 0 200 R 50 50 1 1 I +X v- 2 0 -250 200 U 50 50 1 1 I +X v+ 3 0 250 200 D 50 50 1 1 I +X out 4 300 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# inv-RESCUE-CD_4027 +# +DEF inv-RESCUE-CD_4027 X 0 0 N N 1 F N +F0 "X" -50 0 60 H V C CNN +F1 "inv-RESCUE-CD_4027" 50 -50 60 H V C CNN +F2 "" 0 200 60 H I C CNN +F3 "" 0 200 60 H I C CNN +DRAW +T 0 -250 50 60 0 0 0 in Normal 0 C C +T 0 300 50 60 0 0 0 out Normal 0 C C +T 0 -50 150 60 0 0 0 v+ Normal 0 C C +T 0 -50 -200 60 0 0 0 v- Normal 0 C C +A 175 0 25 1 1799 0 1 0 N 200 0 150 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +P 4 0 1 0 -100 100 -100 -150 150 0 -100 100 N +X in 1 -300 0 200 R 50 50 1 1 I +X v+ 2 0 250 200 D 50 50 1 1 I +X v- 3 0 -300 200 U 50 50 1 1 I +X out 4 400 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# nand-RESCUE-CD_4027 +# +DEF nand-RESCUE-CD_4027 X 0 40 N N 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "nand-RESCUE-CD_4027" 0 50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +T 0 -200 100 60 0 0 0 in1 Normal 0 C C +T 0 -200 -100 60 0 0 0 in2 Normal 0 C C +T 0 300 50 60 0 0 0 out Normal 0 C C +T 0 50 200 60 0 0 0 v+ Normal 0 C C +T 0 50 -200 60 0 0 0 v- Normal 0 C C +A 0 0 141 450 -450 0 1 0 N 100 100 100 -100 +A 175 0 25 1 1799 0 1 0 N 200 0 150 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +P 4 0 1 0 100 100 -100 100 -100 -100 100 -100 N +X in1 1 -300 50 200 R 50 50 1 1 I +X v+ 2 0 300 200 D 50 50 1 1 I +X v- 3 0 -300 200 U 50 50 1 1 I +X out 4 400 0 200 L 50 50 1 1 O +X in2 5 -300 -50 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# or +# +DEF or X 0 40 N N 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "or" 0 50 60 H V C CNN +F2 "" 700 300 60 H I C CNN +F3 "" 700 300 60 H I C CNN +DRAW +T 0 -200 100 60 0 0 0 in1 Normal 0 C C +T 0 -200 -100 60 0 0 0 in2 Normal 0 C C +T 0 250 50 60 0 0 0 out Normal 0 C C +T 900 -50 200 60 0 0 0 v+ Normal 0 C C +T 900 -50 -200 60 0 0 0 v- Normal 0 C C +A -250 0 180 337 -337 0 1 0 N -100 100 -100 -100 +A -107 278 378 -889 -472 0 1 0 N -100 -100 150 0 +A -103 -269 369 895 468 0 1 0 N -100 100 150 0 +X in1 1 -300 50 200 R 50 50 1 1 I +X in2 2 -300 -50 200 R 50 50 1 1 I +X v- 3 0 -300 200 U 50 50 1 1 I +X v+ 4 0 300 200 D 50 50 1 1 I +X out 5 350 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# plot_v1 +# +DEF plot_v1 U 0 40 Y Y 1 F N +F0 "U" 0 500 60 H V C CNN +F1 "plot_v1" 200 350 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 0 500 100 0 1 0 N +X ~ ~ 0 200 200 U 50 50 1 1 I +ENDDRAW +ENDDEF +# +# pulse +# +DEF pulse v 0 40 Y Y 1 F N +F0 "v" -200 100 60 H V C CNN +F1 "pulse" -200 -50 60 H V C CNN +F2 "R1" -300 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + 1_pin +$ENDFPLIST +DRAW +A -25 -450 501 928 871 0 1 0 N -50 50 0 50 +A 25 400 451 -931 -868 0 1 0 N 0 -50 50 -50 +A 75 600 551 -926 -873 0 1 0 N 50 50 100 50 +A 350 0 403 -1728 1728 0 1 0 N -50 -50 -50 50 +A 450 0 453 1736 -1736 0 1 0 N 0 50 0 -50 +A 600 0 552 -1748 1748 0 1 0 N 50 -50 50 50 +C 0 0 150 0 1 0 N +X + 1 0 450 300 D 50 50 1 1 P +X - 2 0 -450 300 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD_4027/CD_4027-rescue.lib b/Failed_subcircuits/CD_4027/CD_4027-rescue.lib new file mode 100644 index 000000000..7a7818c4f --- /dev/null +++ b/Failed_subcircuits/CD_4027/CD_4027-rescue.lib @@ -0,0 +1,86 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# buf-RESCUE-CD_4027 +# +DEF buf-RESCUE-CD_4027 X 0 40 N N 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "buf-RESCUE-CD_4027" 0 50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +T 0 -150 50 60 0 0 0 in Normal 0 C C +T 0 200 50 60 0 0 0 out Normal 0 C C +T 0 50 150 60 0 0 0 v+ Normal 0 C C +T 0 50 -150 60 0 0 0 v- Normal 0 C C +P 4 0 1 0 -50 100 -50 -100 100 0 -50 100 N +X in 1 -250 0 200 R 50 50 1 1 I +X v- 2 0 -250 200 U 50 50 1 1 I +X v+ 3 0 250 200 D 50 50 1 1 I +X out 4 300 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# inv-RESCUE-CD_4027 +# +DEF inv-RESCUE-CD_4027 X 0 0 N N 1 F N +F0 "X" -50 0 60 H V C CNN +F1 "inv-RESCUE-CD_4027" 50 -50 60 H V C CNN +F2 "" 0 200 60 H I C CNN +F3 "" 0 200 60 H I C CNN +DRAW +T 0 -250 50 60 0 0 0 in Normal 0 C C +T 0 300 50 60 0 0 0 out Normal 0 C C +T 0 -50 150 60 0 0 0 v+ Normal 0 C C +T 0 -50 -200 60 0 0 0 v- Normal 0 C C +A 175 0 25 1 1799 0 1 0 N 200 0 150 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +P 4 0 1 0 -100 100 -100 -150 150 0 -100 100 N +X in 1 -300 0 200 R 50 50 1 1 I +X v+ 2 0 250 200 D 50 50 1 1 I +X v- 3 0 -300 200 U 50 50 1 1 I +X out 4 400 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# nand-RESCUE-CD_4027 +# +DEF nand-RESCUE-CD_4027 X 0 40 N N 1 F N +F0 "X" 0 -50 60 H V C CNN +F1 "nand-RESCUE-CD_4027" 0 50 60 H V C CNN +F2 "" 0 -50 60 H I C CNN +F3 "" 0 -50 60 H I C CNN +DRAW +T 0 -200 100 60 0 0 0 in1 Normal 0 C C +T 0 -200 -100 60 0 0 0 in2 Normal 0 C C +T 0 300 50 60 0 0 0 out Normal 0 C C +T 0 50 200 60 0 0 0 v+ Normal 0 C C +T 0 50 -200 60 0 0 0 v- Normal 0 C C +A 0 0 141 450 -450 0 1 0 N 100 100 100 -100 +A 175 0 25 1 1799 0 1 0 N 200 0 150 0 +A 175 0 25 -1799 -1 0 1 0 N 150 0 200 0 +P 4 0 1 0 100 100 -100 100 -100 -100 100 -100 N +X in1 1 -300 50 200 R 50 50 1 1 I +X v+ 2 0 300 200 D 50 50 1 1 I +X v- 3 0 -300 200 U 50 50 1 1 I +X out 4 400 0 200 L 50 50 1 1 O +X in2 5 -300 -50 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD_4027/CD_4027.cir b/Failed_subcircuits/CD_4027/CD_4027.cir new file mode 100644 index 000000000..6278c4225 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CD_4027.cir @@ -0,0 +1,43 @@ +* C:\Users\arpit\coding\esim_projects\CD_4027\CD_4027.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/30/22 00:04:20 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +X4 Set Vdd GND Net-_X14-Pad1_ inv +X1 J GND Vdd Net-_X1-Pad4_ buf +X2 K Vdd GND Net-_X2-Pad4_ inv +X3 Clock Vdd GND Net-_X11-Pad2_ inv +X6 Net-_X11-Pad2_ Vdd GND Net-_X11-Pad3_ inv +X7 Net-_X17-Pad4_ Vdd GND Net-_X7-Pad4_ inv +X8 Net-_X1-Pad4_ Net-_X17-Pad4_ GND Vdd Net-_X10-Pad1_ or +X9 Net-_X7-Pad4_ Net-_X2-Pad4_ GND Vdd Net-_X10-Pad4_ or +X10 Net-_X10-Pad1_ GND Vdd Net-_X10-Pad4_ Net-_X10-Pad5_ and +X11 Net-_X10-Pad5_ Net-_X11-Pad2_ Net-_X11-Pad3_ Net-_X11-Pad4_ TG +X12 Net-_X11-Pad4_ Vdd GND Net-_X12-Pad4_ Net-_X12-Pad5_ nand +X13 Net-_X13-Pad1_ Net-_X11-Pad3_ Net-_X11-Pad2_ Net-_X11-Pad4_ TG +X14 Net-_X14-Pad1_ Vdd GND Net-_X13-Pad1_ Net-_X12-Pad4_ nand +X15 Net-_X15-Pad1_ Net-_X11-Pad3_ Net-_X11-Pad2_ Net-_X12-Pad4_ TG +X17 Net-_X14-Pad1_ Vdd GND Net-_X17-Pad4_ Net-_X15-Pad1_ nand +X16 Net-_X15-Pad1_ Net-_X11-Pad2_ Net-_X11-Pad3_ Net-_X16-Pad4_ TG +X18 Net-_X17-Pad4_ Vdd GND Net-_X16-Pad4_ Net-_X12-Pad5_ nand +X19 Net-_X17-Pad4_ GND Vdd Q buf +X20 Net-_X16-Pad4_ GND Vdd Qbar buf +X5 Reset Vdd GND Net-_X12-Pad5_ inv +v6 Vdd GND DC +v3 Set GND pulse +v4 J GND pulse +v5 K GND pulse +v1 Reset GND pulse +v2 Clock GND pulse +U5 Set plot_v1 +U1 J plot_v1 +U2 K plot_v1 +U3 Reset plot_v1 +U4 Clock plot_v1 +U6 Q plot_v1 +U7 Qbar plot_v1 + +.end diff --git a/Failed_subcircuits/CD_4027/CD_4027.cir.out b/Failed_subcircuits/CD_4027/CD_4027.cir.out new file mode 100644 index 000000000..d96151d43 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CD_4027.cir.out @@ -0,0 +1,60 @@ +* c:\users\arpit\coding\esim_projects\cd_4027\cd_4027.cir + +.include cmos_tg.sub +.include cmos_buffer.sub +.include CMOS_inverter.sub +.include cmos__nand.sub +.include cmos_and.sub +.include cmos_or.sub +x4 set vdd gnd net-_x14-pad1_ CMOS_inverter +x1 j gnd vdd net-_x1-pad4_ cmos_buffer +x2 k vdd gnd net-_x2-pad4_ CMOS_inverter +x3 clock vdd gnd net-_x11-pad2_ CMOS_inverter +r1 clock clock1 1 +r2 reset reset1 1 +x6 net-_x11-pad2_ vdd gnd net-_x11-pad3_ CMOS_inverter +x7 net-_x17-pad4_ vdd gnd net-_x7-pad4_ CMOS_inverter +x8 net-_x1-pad4_ net-_x17-pad4_ gnd vdd net-_x10-pad1_ cmos_or +x9 net-_x7-pad4_ net-_x2-pad4_ gnd vdd net-_x10-pad4_ cmos_or +x10 net-_x10-pad1_ gnd vdd net-_x10-pad4_ net-_x10-pad5_ cmos_and +x11 net-_x10-pad5_ net-_x11-pad2_ net-_x11-pad3_ net-_x11-pad4_ cmos_tg +x12 net-_x11-pad4_ vdd gnd net-_x12-pad4_ net-_x12-pad5_ cmos__nand +x13 net-_x13-pad1_ net-_x11-pad3_ net-_x11-pad2_ net-_x11-pad4_ cmos_tg +x14 net-_x14-pad1_ vdd gnd net-_x13-pad1_ net-_x12-pad4_ cmos__nand +x15 net-_x15-pad1_ net-_x11-pad3_ net-_x11-pad2_ net-_x12-pad4_ cmos_tg +x17 net-_x14-pad1_ vdd gnd net-_x17-pad4_ net-_x15-pad1_ cmos__nand +x16 net-_x15-pad1_ net-_x11-pad2_ net-_x11-pad3_ net-_x16-pad4_ cmos_tg +x18 net-_x17-pad4_ vdd gnd net-_x16-pad4_ net-_x12-pad5_ cmos__nand +x19 net-_x17-pad4_ gnd vdd q cmos_buffer +x20 net-_x16-pad4_ gnd vdd qbar cmos_buffer +x5 reset1 vdd gnd net-_x12-pad5_ CMOS_inverter +v6 vdd gnd dc 5 +v3 set gnd pulse(0 5 0.1n 0.1n 0.1n 8n 10000n) +v2 clock1 gnd pulse(0 5 0.1n 0.1n 0.1n 1n 2n) +v4 j gnd pulse(0 5 0.1n 0.1n 0.1n 4n 8n) +v5 k gnd pulse(0 5 0.1n 0.1n 0.1n 16n 32n ) +v1 reset gnd pulse(0 5 0.1n 0.1n 0.1n 8n 10000n ) + +* u5 set plot_v1 +* u1 j plot_v1 +* u2 k plot_v1 +* u3 gnd plot_v1 +* u4 clock plot_v1 +* u6 q plot_v1 +* u7 qbar plot_v1 +.tran 0.1e-09 60e-09 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +plot v(set) +plot v(j) +plot v(k) +plot v(gnd) +plot v(clock) +plot v(q) +plot v(qbar) +.endc +.end \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/CD_4027.pro b/Failed_subcircuits/CD_4027/CD_4027.pro new file mode 100644 index 000000000..b5ba95178 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CD_4027.pro @@ -0,0 +1,72 @@ +update=07/22/22 18:33:47 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=CD_4027-rescue +LibName2=adc-dac +LibName3=memory +LibName4=xilinx +LibName5=microcontrollers +LibName6=dsp +LibName7=microchip +LibName8=analog_switches +LibName9=motorola +LibName10=texas +LibName11=intel +LibName12=audio +LibName13=interface +LibName14=digital-audio +LibName15=philips +LibName16=display +LibName17=cypress +LibName18=siliconi +LibName19=opto +LibName20=atmel +LibName21=contrib +LibName22=power +LibName23=eSim_Plot +LibName24=transistors +LibName25=conn +LibName26=eSim_User +LibName27=regul +LibName28=74xx +LibName29=cmos4000 +LibName30=eSim_Analog +LibName31=eSim_Devices +LibName32=eSim_Digital +LibName33=eSim_Hybrid +LibName34=eSim_Miscellaneous +LibName35=eSim_Power +LibName36=eSim_Sources +LibName37=eSim_Subckt +LibName38=eSim_Nghdl +LibName39=eSim_Ngveri diff --git a/Failed_subcircuits/CD_4027/CD_4027.proj b/Failed_subcircuits/CD_4027/CD_4027.proj new file mode 100644 index 000000000..5cfc4abb7 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CD_4027.proj @@ -0,0 +1 @@ +schematicFile CD_4027.sch diff --git a/Failed_subcircuits/CD_4027/CD_4027.sch b/Failed_subcircuits/CD_4027/CD_4027.sch new file mode 100644 index 000000000..8dd0b3866 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CD_4027.sch @@ -0,0 +1,768 @@ +EESchema Schematic File Version 2 +LIBS:CD_4027-rescue +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CD_4027-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L inv-RESCUE-CD_4027 X4 +U 1 1 62DA56AF +P 2850 1700 +F 0 "X4" H 2800 1700 60 0000 C CNN +F 1 "inv" H 2900 1650 60 0000 C CNN +F 2 "" H 2850 1900 60 0001 C CNN +F 3 "" H 2850 1900 60 0001 C CNN + 1 2850 1700 + 1 0 0 -1 +$EndComp +$Comp +L buf-RESCUE-CD_4027 X1 +U 1 1 62DA56DC +P 2350 2600 +F 0 "X1" H 2350 2550 60 0000 C CNN +F 1 "buf" H 2350 2650 60 0000 C CNN +F 2 "" H 2350 2550 60 0001 C CNN +F 3 "" H 2350 2550 60 0001 C CNN + 1 2350 2600 + 1 0 0 -1 +$EndComp +$Comp +L inv-RESCUE-CD_4027 X2 +U 1 1 62DA570B +P 2700 3850 +F 0 "X2" H 2650 3850 60 0000 C CNN +F 1 "inv" H 2750 3800 60 0000 C CNN +F 2 "" H 2700 4050 60 0001 C CNN +F 3 "" H 2700 4050 60 0001 C CNN + 1 2700 3850 + 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+Connection ~ 550 4900 +Wire Wire Line + 650 5850 550 5850 +Connection ~ 550 5850 +Text GLabel 11700 2400 2 60 Output ~ 0 +Q +Text GLabel 11700 4000 2 60 Output ~ 0 +Qbar +Text GLabel 1650 1650 1 60 Input ~ 0 +Set +Text GLabel 1650 2550 1 60 Input ~ 0 +J +Text GLabel 1650 3750 1 60 Input ~ 0 +K +Text GLabel 1600 4850 1 60 Input ~ 0 +Reset +Text GLabel 1600 5800 1 60 Input ~ 0 +Clock +$Comp +L plot_v1 U5 +U 1 1 62DABC0C +P 1900 1850 +F 0 "U5" H 1900 2350 60 0000 C CNN +F 1 "plot_v1" H 2100 2200 60 0000 C CNN +F 2 "" H 1900 1850 60 0000 C CNN +F 3 "" H 1900 1850 60 0000 C CNN + 1 1900 1850 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U1 +U 1 1 62DABD7E +P 1850 2750 +F 0 "U1" H 1850 3250 60 0000 C CNN +F 1 "plot_v1" H 2050 3100 60 0000 C CNN +F 2 "" H 1850 2750 60 0000 C CNN +F 3 "" H 1850 2750 60 0000 C CNN + 1 1850 2750 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U2 +U 1 1 62DABEC4 +P 1850 4000 +F 0 "U2" H 1850 4500 60 0000 C CNN +F 1 "plot_v1" H 2050 4350 60 0000 C CNN +F 2 "" H 1850 4000 60 0000 C CNN +F 3 "" H 1850 4000 60 0000 C CNN + 1 1850 4000 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U3 +U 1 1 62DAC0B6 +P 1850 5050 +F 0 "U3" H 1850 5550 60 0000 C CNN +F 1 "plot_v1" H 2050 5400 60 0000 C CNN +F 2 "" H 1850 5050 60 0000 C CNN +F 3 "" H 1850 5050 60 0000 C CNN + 1 1850 5050 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U4 +U 1 1 62DAC367 +P 1850 6000 +F 0 "U4" H 1850 6500 60 0000 C CNN +F 1 "plot_v1" H 2050 6350 60 0000 C CNN +F 2 "" H 1850 6000 60 0000 C CNN +F 3 "" H 1850 6000 60 0000 C CNN + 1 1850 6000 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U6 +U 1 1 62DAC673 +P 11500 2500 +F 0 "U6" H 11500 3000 60 0000 C CNN +F 1 "plot_v1" H 11700 2850 60 0000 C CNN +F 2 "" H 11500 2500 60 0000 C CNN +F 3 "" H 11500 2500 60 0000 C CNN + 1 11500 2500 + 1 0 0 -1 +$EndComp +$Comp +L plot_v1 U7 +U 1 1 62DACA6C +P 11600 4100 +F 0 "U7" H 11600 4600 60 0000 C CNN +F 1 "plot_v1" H 11800 4450 60 0000 C CNN +F 2 "" H 11600 4100 60 0000 C CNN +F 3 "" H 11600 4100 60 0000 C CNN + 1 11600 4100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 11600 3900 11600 4000 +Connection ~ 11600 4000 +Wire Wire Line + 11500 2300 11500 2400 +Connection ~ 11500 2400 +Wire Wire Line + 1900 1650 1900 1700 +Connection ~ 1900 1700 +Text GLabel 1750 950 1 60 Input ~ 0 +Vdd +Wire Wire Line + 1850 2550 1850 2600 +Connection ~ 1850 2600 +Wire Wire Line + 1850 3800 1850 3850 +Connection ~ 1850 3850 +Wire Wire Line + 1850 4900 1850 4850 +Connection ~ 1850 4900 +Wire Wire Line + 1850 5800 1850 5850 +Connection ~ 1850 5850 +Wire Wire Line + 1750 950 1750 1000 +Connection ~ 1750 1000 +Wire Wire Line + 1650 1650 1650 1700 +Connection ~ 1650 1700 +Wire Wire Line + 1650 2550 1650 2600 +Connection ~ 1650 2600 +Wire Wire Line + 1650 3750 1650 3850 +Connection ~ 1650 3850 +Wire Wire Line + 1600 4850 1600 4900 +Connection ~ 1600 4900 +Wire Wire Line + 1600 5800 1600 5850 +Connection ~ 1600 5850 +Wire Wire Line + 3950 5550 3950 5600 +Wire Wire Line + 1550 4900 2650 4900 +Wire Wire Line + 1500 6700 1500 6300 +Connection ~ 1500 6300 +$EndSCHEMATC diff --git a/Failed_subcircuits/CD_4027/CD_4027_Previous_Values.xml b/Failed_subcircuits/CD_4027/CD_4027_Previous_Values.xml new file mode 100644 index 000000000..683626cd1 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CD_4027_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or Amperes00.1900Secnsnsdc2.5pulse01200n10npulse0150n25npulse0180n40npulse00200n10npulse0115n7.5nC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_bufferC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverterC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_orC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_orC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_andC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tgC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nandC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tgC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nandC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tgC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nandC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tgC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nandC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_bufferC:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_bufferC:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverter \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/CMOS_inverter-cache.lib b/Failed_subcircuits/CD_4027/CMOS_inverter-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/Failed_subcircuits/CD_4027/CMOS_inverter-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD_4027/CMOS_inverter.cir b/Failed_subcircuits/CD_4027/CMOS_inverter.cir new file mode 100644 index 000000000..efc3276f7 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CMOS_inverter.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\CMOS_inverter\CMOS_inverter.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:13:55 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M1-Pad3_ Net-_M1-Pad1_ PORT + +.end diff --git a/Failed_subcircuits/CD_4027/CMOS_inverter.cir.out b/Failed_subcircuits/CD_4027/CMOS_inverter.cir.out new file mode 100644 index 000000000..c6df11d6d --- /dev/null +++ b/Failed_subcircuits/CD_4027/CMOS_inverter.cir.out @@ -0,0 +1,16 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_inverter\cmos_inverter.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m2-pad3_ net-_m1-pad3_ net-_m1-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD_4027/CMOS_inverter.pro b/Failed_subcircuits/CD_4027/CMOS_inverter.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CMOS_inverter.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD_4027/CMOS_inverter.sch b/Failed_subcircuits/CD_4027/CMOS_inverter.sch new file mode 100644 index 000000000..ece0f26e2 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CMOS_inverter.sch @@ -0,0 +1,149 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:CMOS_inverter-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 62DA908D +P 5150 2200 +F 0 "M2" H 5100 2250 50 0000 R CNN +F 1 "mosfet_p" H 5200 2350 50 0000 R CNN +F 2 "" H 5400 2300 29 0000 C CNN +F 3 "" H 5200 2200 60 0000 C CNN + 1 5150 2200 + 1 0 0 1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62DA908E +P 5100 2800 +F 0 "M1" H 5100 2650 50 0000 R CNN +F 1 "mosfet_n" H 5200 2750 50 0000 R CNN +F 2 "" H 5400 2500 29 0000 C CNN +F 3 "" H 5200 2600 60 0000 C CNN + 1 5100 2800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5300 2000 5300 1650 +Wire Wire Line + 5300 1800 5400 1800 +Wire Wire Line + 5400 1800 5400 2050 +Connection ~ 5300 1800 +Wire Wire Line + 5300 3200 5300 3600 +Wire Wire Line + 5400 3150 5400 3350 +Wire Wire Line + 5400 3350 5300 3350 +Connection ~ 5300 3350 +Wire Wire Line + 5000 2200 4800 2200 +Wire Wire Line + 4800 2200 4800 3000 +Wire Wire Line + 4800 3000 5000 3000 +Wire Wire Line + 5300 2400 5300 2800 +Wire Wire Line + 5300 2600 5900 2600 +Connection ~ 5300 2600 +Wire Wire Line + 4800 2600 4300 2600 +Connection ~ 4800 2600 +$Comp +L PORT U1 +U 2 1 62DA908F +P 5300 1400 +F 0 "U1" H 5350 1500 30 0000 C CNN +F 1 "PORT" H 5300 1400 30 0000 C CNN +F 2 "" H 5300 1400 60 0000 C CNN +F 3 "" H 5300 1400 60 0000 C CNN + 2 5300 1400 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA9090 +P 5300 3850 +F 0 "U1" H 5350 3950 30 0000 C CNN +F 1 "PORT" H 5300 3850 30 0000 C CNN +F 2 "" H 5300 3850 60 0000 C CNN +F 3 "" H 5300 3850 60 0000 C CNN + 3 5300 3850 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 62DA9091 +P 4050 2600 +F 0 "U1" H 4100 2700 30 0000 C CNN +F 1 "PORT" H 4050 2600 30 0000 C CNN +F 2 "" H 4050 2600 60 0000 C CNN +F 3 "" H 4050 2600 60 0000 C CNN + 1 4050 2600 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62DA9092 +P 6150 2600 +F 0 "U1" H 6200 2700 30 0000 C CNN +F 1 "PORT" H 6150 2600 30 0000 C CNN +F 2 "" H 6150 2600 60 0000 C CNN +F 3 "" H 6150 2600 60 0000 C CNN + 4 6150 2600 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/Failed_subcircuits/CD_4027/CMOS_inverter.sub b/Failed_subcircuits/CD_4027/CMOS_inverter.sub new file mode 100644 index 000000000..a04225173 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CMOS_inverter.sub @@ -0,0 +1,10 @@ +* Subcircuit CMOS_inverter +.subckt CMOS_inverter net-_m1-pad2_ net-_m2-pad3_ net-_m1-pad3_ net-_m1-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_inverter\cmos_inverter.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends CMOS_inverter \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/CMOS_inverter_Previous_Values.xml b/Failed_subcircuits/CD_4027/CMOS_inverter_Previous_Values.xml new file mode 100644 index 000000000..0388b42b0 --- /dev/null +++ b/Failed_subcircuits/CD_4027/CMOS_inverter_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/NMOS-180nm.lib b/Failed_subcircuits/CD_4027/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/Failed_subcircuits/CD_4027/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/Failed_subcircuits/CD_4027/PMOS-180nm.lib b/Failed_subcircuits/CD_4027/PMOS-180nm.lib new file mode 100644 index 000000000..032b5b95e --- /dev/null +++ b/Failed_subcircuits/CD_4027/PMOS-180nm.lib @@ -0,0 +1,11 @@ +.model CMOSP PMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=4.1589E17 VTH0=-0.3938813 K1=0.5479015 ++ K2=0.0360586 K3=0.0993095 K3B=5.7086622 W0=1E-6 NLX=1.313191E-7 DVT0W=0 DVT1W=0 DVT2W=0 DVT0=0.4911363 ++ DVT1=0.2227356 DVT2=0.1 U0=115.6852975 UA=1.505832E-9 UB=1E-21 UC=-1E-10 VSAT=1.329694E5 A0=1.7590478 ++ AGS=0.3641621 B0=3.427126E-7 B1=1.062928E-6 KETA=0.0134667 A1=0.6859506 A2=0.3506788 RDSW=168.5705677 ++ PRWG=0.5 PRWB=-0.4987371 WR=1 WINT=0 LINT=3.028832E-8 XL=0 XW=-1E-8 DWG=-2.349633E-8 DWB=-7.152486E-9 ++ VOFF=-0.0994037 NFACTOR=1.9424315 CIT=0 CDSC=2.4E-4 CDSCD=0 CDSCB=0 ETA0=0.0608072 ETAB=-0.0426148 ++ DSUB=0.7343015 PCLM=3.2579974 PDIBLC1=7.229527E-6 PDIBLC2=0.025389 PDIBLCB=-1E-3 DROUT=0 PSCBE1=1.454878E10 ++ PSCBE2=4.202027E-9 PVAG=15 DELTA=0.01 RSH=7.8 MOBMOD=1 PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 ++ UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 ++ CGDO=6.32E-10 CGSO=6.32E-10 CGBO=1E-12 CJ=1.172138E-3 PB=0.8421173 MJ=0.4109788 CJSW=2.242609E-10 PBSW=0.8 + MJSW=0.3752089 CJSWG=4.22E-10 PBSWG=0.8 MJSWG=0.3752089 CF=0 PVTH0=1.888482E-3 PRDSW=11.5315407 PK2=1.559399E-3 ++ WKETA=0.0319301 LKETA=2.955547E-3 PU0=-1.1105313 PUA=-4.62102E-11 PUB=1E-21 PVSAT=50 PETA0=1E-4 PKETA=-4.346368E-3) diff --git a/Failed_subcircuits/CD_4027/README.md b/Failed_subcircuits/CD_4027/README.md new file mode 100644 index 000000000..2af839d8b --- /dev/null +++ b/Failed_subcircuits/CD_4027/README.md @@ -0,0 +1,35 @@ + +# CD4027 CMOS Dual J-K Flip Flop IC + +CD4027 is a single monolithic chip IC, containing two identical JK Flip Flops with J, K , Set, Reset and Clock as Input Signals; Buffered Q and Q bar as outputs. + + +## Usage/Examples + +Counters + +Data registers + +Shift registers + +Frequency Dividers + + +## Documentation + +To know the details of CD4027 IC please refer to this link [CD4027_datasheet.](https://www.ti.com/lit/ds/symlink/cd4027b.pdf?ts=1665941098406) + +## Error observed + +The output obtained is very erratic and noisy. + +## Possible Solution + +The W/L Ratio of the components used in the design can be optimised/reconfigured in order to obtain desired results. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/analysis b/Failed_subcircuits/CD_4027/analysis new file mode 100644 index 000000000..5e4737687 --- /dev/null +++ b/Failed_subcircuits/CD_4027/analysis @@ -0,0 +1 @@ +.tran 0.1e-09 900e-09 0e-00 \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos__nand-cache.lib b/Failed_subcircuits/CD_4027/cmos__nand-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos__nand-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD_4027/cmos__nand.cir b/Failed_subcircuits/CD_4027/cmos__nand.cir new file mode 100644 index 000000000..74d63f52f --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos__nand.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cmos__nand\cmos__nand.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:20:14 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad4_ mosfet_n +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M2-Pad4_ Net-_M2-Pad4_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad4_ Net-_M1-Pad1_ Net-_M3-Pad2_ PORT + +.end diff --git a/Failed_subcircuits/CD_4027/cmos__nand.cir.out b/Failed_subcircuits/CD_4027/cmos__nand.cir.out new file mode 100644 index 000000000..d5ec37173 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos__nand.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos__nand\cmos__nand.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m2-pad4_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m1-pad3_ net-_m2-pad4_ net-_m1-pad1_ net-_m3-pad2_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD_4027/cmos__nand.pro b/Failed_subcircuits/CD_4027/cmos__nand.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos__nand.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD_4027/cmos__nand.sch b/Failed_subcircuits/CD_4027/cmos__nand.sch new file mode 100644 index 000000000..7c5df3c1e --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos__nand.sch @@ -0,0 +1,211 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:cmos__nand-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M1 +U 1 1 62DA9263 +P 5400 2750 +F 0 "M1" H 5350 2800 50 0000 R CNN +F 1 "mosfet_p" H 5450 2900 50 0000 R CNN +F 2 "" H 5650 2850 29 0000 C CNN +F 3 "" H 5450 2750 60 0000 C CNN + 1 5400 2750 + 1 0 0 1 +$EndComp +$Comp +L mosfet_p M4 +U 1 1 62DA9264 +P 6350 2750 +F 0 "M4" H 6300 2800 50 0000 R CNN +F 1 "mosfet_p" H 6400 2900 50 0000 R CNN +F 2 "" H 6600 2850 29 0000 C CNN +F 3 "" H 6400 2750 60 0000 C CNN + 1 6350 2750 + -1 0 0 1 +$EndComp +$Comp +L mosfet_n M2 +U 1 1 62DA9265 +P 5700 3250 +F 0 "M2" H 5700 3100 50 0000 R CNN +F 1 "mosfet_n" H 5800 3200 50 0000 R CNN +F 2 "" H 6000 2950 29 0000 C CNN +F 3 "" H 5800 3050 60 0000 C CNN + 1 5700 3250 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M3 +U 1 1 62DA9266 +P 6100 3750 +F 0 "M3" H 6100 3600 50 0000 R CNN +F 1 "mosfet_n" H 6200 3700 50 0000 R CNN +F 2 "" H 6400 3450 29 0000 C CNN +F 3 "" H 6200 3550 60 0000 C CNN + 1 6100 3750 + -1 0 0 -1 +$EndComp +Wire Wire Line + 5550 2950 5550 3050 +Wire Wire Line + 5550 3050 6200 3050 +Wire Wire Line + 6200 3050 6200 2950 +Wire Wire Line + 5900 3050 5900 3250 +Connection ~ 5900 3050 +Wire Wire Line + 5900 3650 5900 3750 +Wire Wire Line + 5900 4150 5900 4450 +Wire Wire Line + 5800 4100 5800 4250 +Wire Wire Line + 5700 4250 5900 4250 +Connection ~ 5900 4250 +Wire Wire Line + 6000 3600 6000 3700 +Wire Wire Line + 6000 3700 5700 3700 +Wire Wire Line + 5700 3700 5700 4250 +Connection ~ 5800 4250 +Wire Wire Line + 5550 2550 5550 2400 +Wire Wire Line + 5550 2400 6200 2400 +Wire Wire Line + 6200 2400 6200 2550 +Wire Wire Line + 5650 2600 5650 2400 +Connection ~ 5650 2400 +Wire Wire Line + 6100 2600 6100 2400 +Connection ~ 6100 2400 +Wire Wire Line + 5900 2400 5900 2200 +Connection ~ 5900 2400 +Wire Wire Line + 5250 2750 5250 3450 +Wire Wire Line + 5250 3450 5600 3450 +Wire Wire Line + 6500 2750 6500 3950 +Wire Wire Line + 6500 3950 6200 3950 +Wire Wire Line + 6500 3350 7150 3350 +Connection ~ 6500 3350 +Wire Wire Line + 5250 3050 4900 3050 +Connection ~ 5250 3050 +Wire Wire Line + 5900 3150 6800 3150 +Connection ~ 5900 3150 +$Comp +L PORT U1 +U 1 1 62DA9267 +P 4650 3050 +F 0 "U1" H 4700 3150 30 0000 C CNN +F 1 "PORT" H 4650 3050 30 0000 C CNN +F 2 "" H 4650 3050 60 0000 C CNN +F 3 "" H 4650 3050 60 0000 C CNN + 1 4650 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62DA9268 +P 5900 1950 +F 0 "U1" H 5950 2050 30 0000 C CNN +F 1 "PORT" H 5900 1950 30 0000 C CNN +F 2 "" H 5900 1950 60 0000 C CNN +F 3 "" H 5900 1950 60 0000 C CNN + 2 5900 1950 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA9269 +P 5900 4700 +F 0 "U1" H 5950 4800 30 0000 C CNN +F 1 "PORT" H 5900 4700 30 0000 C CNN +F 2 "" H 5900 4700 60 0000 C CNN +F 3 "" H 5900 4700 60 0000 C CNN + 3 5900 4700 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 62DA926A +P 7400 3350 +F 0 "U1" H 7450 3450 30 0000 C CNN +F 1 "PORT" H 7400 3350 30 0000 C CNN +F 2 "" H 7400 3350 60 0000 C CNN +F 3 "" H 7400 3350 60 0000 C CNN + 5 7400 3350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62DA926B +P 7050 3150 +F 0 "U1" H 7100 3250 30 0000 C CNN +F 1 "PORT" H 7050 3150 30 0000 C CNN +F 2 "" H 7050 3150 60 0000 C CNN +F 3 "" H 7050 3150 60 0000 C CNN + 4 7050 3150 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/Failed_subcircuits/CD_4027/cmos__nand.sub b/Failed_subcircuits/CD_4027/cmos__nand.sub new file mode 100644 index 000000000..f47823eeb --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos__nand.sub @@ -0,0 +1,12 @@ +* Subcircuit cmos__nand +.subckt cmos__nand net-_m1-pad2_ net-_m1-pad3_ net-_m2-pad4_ net-_m1-pad1_ net-_m3-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\cmos__nand\cmos__nand.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m2-pad4_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cmos__nand \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos__nand_Previous_Values.xml b/Failed_subcircuits/CD_4027/cmos__nand_Previous_Values.xml new file mode 100644 index 000000000..f43eb2d54 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos__nand_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos_and-cache.lib b/Failed_subcircuits/CD_4027/cmos_and-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_and-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD_4027/cmos_and.cir b/Failed_subcircuits/CD_4027/cmos_and.cir new file mode 100644 index 000000000..722d1112e --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_and.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_and\cmos_and.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:26:47 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad4_ mosfet_n +M3 Net-_M2-Pad3_ Net-_M3-Pad2_ Net-_M2-Pad4_ Net-_M2-Pad4_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M2-Pad4_ Net-_M1-Pad3_ Net-_M3-Pad2_ Net-_M5-Pad1_ PORT +M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_p +M5 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad4_ Net-_M2-Pad4_ mosfet_n + +.end diff --git a/Failed_subcircuits/CD_4027/cmos_and.cir.out b/Failed_subcircuits/CD_4027/cmos_and.cir.out new file mode 100644 index 000000000..66507939a --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_and.cir.out @@ -0,0 +1,20 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_and\cmos_and.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m2-pad4_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m2-pad4_ net-_m1-pad3_ net-_m3-pad2_ net-_m5-pad1_ port +m6 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad4_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD_4027/cmos_and.pro b/Failed_subcircuits/CD_4027/cmos_and.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_and.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD_4027/cmos_and.sch b/Failed_subcircuits/CD_4027/cmos_and.sch new file mode 100644 index 000000000..6133af5f3 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_and.sch @@ -0,0 +1,269 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:cmos_and-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M1 +U 1 1 62DA96A4 +P 3450 2700 +F 0 "M1" H 3400 2750 50 0000 R CNN +F 1 "mosfet_p" H 3500 2850 50 0000 R CNN +F 2 "" H 3700 2800 29 0000 C CNN +F 3 "" H 3500 2700 60 0000 C CNN + 1 3450 2700 + 1 0 0 1 +$EndComp +$Comp +L mosfet_p M4 +U 1 1 62DA96A5 +P 4400 2700 +F 0 "M4" H 4350 2750 50 0000 R CNN +F 1 "mosfet_p" H 4450 2850 50 0000 R CNN +F 2 "" H 4650 2800 29 0000 C CNN +F 3 "" H 4450 2700 60 0000 C CNN + 1 4400 2700 + -1 0 0 1 +$EndComp +$Comp +L mosfet_n M2 +U 1 1 62DA96A6 +P 3750 3200 +F 0 "M2" H 3750 3050 50 0000 R CNN +F 1 "mosfet_n" H 3850 3150 50 0000 R CNN +F 2 "" H 4050 2900 29 0000 C CNN +F 3 "" H 3850 3000 60 0000 C CNN + 1 3750 3200 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M3 +U 1 1 62DA96A7 +P 4150 3700 +F 0 "M3" H 4150 3550 50 0000 R CNN +F 1 "mosfet_n" H 4250 3650 50 0000 R CNN +F 2 "" H 4450 3400 29 0000 C CNN +F 3 "" H 4250 3500 60 0000 C CNN + 1 4150 3700 + -1 0 0 -1 +$EndComp +Wire Wire Line + 3600 2900 3600 3000 +Wire Wire Line + 3600 3000 4250 3000 +Wire Wire Line + 4250 3000 4250 2900 +Wire Wire Line + 3950 3000 3950 3200 +Connection ~ 3950 3000 +Wire Wire Line + 3950 3600 3950 3700 +Wire Wire Line + 3950 4100 3950 4400 +Wire Wire Line + 3850 4050 3850 4200 +Wire Wire Line + 3750 4200 3950 4200 +Connection ~ 3950 4200 +Wire Wire Line + 4050 3550 4050 3650 +Wire Wire Line + 4050 3650 3750 3650 +Wire Wire Line + 3750 3650 3750 4200 +Connection ~ 3850 4200 +Wire Wire Line + 3600 2500 3600 2350 +Wire Wire Line + 3600 2350 4250 2350 +Wire Wire Line + 4250 2350 4250 2500 +Wire Wire Line + 3700 2550 3700 2350 +Connection ~ 3700 2350 +Wire Wire Line + 4150 2550 4150 2350 +Connection ~ 4150 2350 +Wire Wire Line + 3950 2350 3950 2050 +Connection ~ 3950 2350 +Wire Wire Line + 3300 2700 3300 3400 +Wire Wire Line + 3300 3400 3650 3400 +Wire Wire Line + 4550 2700 4550 3900 +Wire Wire Line + 4550 3900 4250 3900 +Wire Wire Line + 4550 3300 5200 3300 +Connection ~ 4550 3300 +Wire Wire Line + 3300 3000 2950 3000 +Connection ~ 3300 3000 +Wire Wire Line + 3950 3100 5950 3100 +Connection ~ 3950 3100 +$Comp +L PORT U1 +U 1 1 62DA96A8 +P 2700 3000 +F 0 "U1" H 2750 3100 30 0000 C CNN +F 1 "PORT" H 2700 3000 30 0000 C CNN +F 2 "" H 2700 3000 60 0000 C CNN +F 3 "" H 2700 3000 60 0000 C CNN + 1 2700 3000 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 62DA96A9 +P 5450 3300 +F 0 "U1" H 5500 3400 30 0000 C CNN +F 1 "PORT" H 5450 3300 30 0000 C CNN +F 2 "" H 5450 3300 60 0000 C CNN +F 3 "" H 5450 3300 60 0000 C CNN + 4 5450 3300 + -1 0 0 1 +$EndComp +$Comp +L mosfet_p M6 +U 1 1 62DA96AA +P 6300 2700 +F 0 "M6" H 6250 2750 50 0000 R CNN +F 1 "mosfet_p" H 6350 2850 50 0000 R CNN +F 2 "" H 6550 2800 29 0000 C CNN +F 3 "" H 6350 2700 60 0000 C CNN + 1 6300 2700 + 1 0 0 1 +$EndComp +$Comp +L mosfet_n M5 +U 1 1 62DA96AB +P 6250 3300 +F 0 "M5" H 6250 3150 50 0000 R CNN +F 1 "mosfet_n" H 6350 3250 50 0000 R CNN +F 2 "" H 6550 3000 29 0000 C CNN +F 3 "" H 6350 3100 60 0000 C CNN + 1 6250 3300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6450 2050 6450 2500 +Wire Wire Line + 6450 2300 6550 2300 +Wire Wire Line + 6550 2300 6550 2550 +Connection ~ 6450 2300 +Wire Wire Line + 6450 4400 6450 3700 +Wire Wire Line + 6550 3650 6550 3850 +Wire Wire Line + 6550 3850 6450 3850 +Connection ~ 6450 3850 +Wire Wire Line + 6150 2700 5950 2700 +Wire Wire Line + 5950 2700 5950 3500 +Wire Wire Line + 5950 3500 6150 3500 +Wire Wire Line + 6450 2900 6450 3300 +Wire Wire Line + 6450 3100 7050 3100 +Connection ~ 6450 3100 +Connection ~ 5950 3100 +$Comp +L PORT U1 +U 5 1 62DA96AC +P 7300 3100 +F 0 "U1" H 7350 3200 30 0000 C CNN +F 1 "PORT" H 7300 3100 30 0000 C CNN +F 2 "" H 7300 3100 60 0000 C CNN +F 3 "" H 7300 3100 60 0000 C CNN + 5 7300 3100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 62DA96AD +P 5150 5050 +F 0 "U1" H 5200 5150 30 0000 C CNN +F 1 "PORT" H 5150 5050 30 0000 C CNN +F 2 "" H 5150 5050 60 0000 C CNN +F 3 "" H 5150 5050 60 0000 C CNN + 2 5150 5050 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA96AE +P 5250 1350 +F 0 "U1" H 5300 1450 30 0000 C CNN +F 1 "PORT" H 5250 1350 30 0000 C CNN +F 2 "" H 5250 1350 60 0000 C CNN +F 3 "" H 5250 1350 60 0000 C CNN + 3 5250 1350 + 0 1 1 0 +$EndComp +Wire Wire Line + 3950 2050 6450 2050 +Wire Wire Line + 3950 4400 6450 4400 +Wire Wire Line + 5150 4800 5150 4400 +Connection ~ 5150 4400 +Wire Wire Line + 5250 1600 5250 2050 +Connection ~ 5250 2050 +$EndSCHEMATC diff --git a/Failed_subcircuits/CD_4027/cmos_and.sub b/Failed_subcircuits/CD_4027/cmos_and.sub new file mode 100644 index 000000000..e7e3f3e40 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_and.sub @@ -0,0 +1,14 @@ +* Subcircuit cmos_and +.subckt cmos_and net-_m1-pad2_ net-_m2-pad4_ net-_m1-pad3_ net-_m3-pad2_ net-_m5-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_and\cmos_and.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +m3 net-_m2-pad3_ net-_m3-pad2_ net-_m2-pad4_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad4_ net-_m2-pad4_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cmos_and \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos_and_Previous_Values.xml b/Failed_subcircuits/CD_4027/cmos_and_Previous_Values.xml new file mode 100644 index 000000000..6407ef8da --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_and_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos_buffer-cache.lib b/Failed_subcircuits/CD_4027/cmos_buffer-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_buffer-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD_4027/cmos_buffer.cir b/Failed_subcircuits/CD_4027/cmos_buffer.cir new file mode 100644 index 000000000..58bbd8448 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_buffer.cir @@ -0,0 +1,15 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_buffer\cmos_buffer.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:29:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M4 Net-_M3-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p +M3 Net-_M3-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M1-Pad3_ Net-_M3-Pad1_ PORT +M2 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n + +.end diff --git a/Failed_subcircuits/CD_4027/cmos_buffer.cir.out b/Failed_subcircuits/CD_4027/cmos_buffer.cir.out new file mode 100644 index 000000000..272da17fd --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_buffer.cir.out @@ -0,0 +1,18 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_buffer\cmos_buffer.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m4 net-_m3-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m2-pad3_ net-_m1-pad3_ net-_m3-pad1_ port +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD_4027/cmos_buffer.pro b/Failed_subcircuits/CD_4027/cmos_buffer.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_buffer.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD_4027/cmos_buffer.sch b/Failed_subcircuits/CD_4027/cmos_buffer.sch new file mode 100644 index 000000000..7eeda05f2 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_buffer.sch @@ -0,0 +1,199 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:cmos_buffer-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M4 +U 1 1 62DA98C4 +P 5800 2950 +F 0 "M4" H 5750 3000 50 0000 R CNN +F 1 "mosfet_p" H 5850 3100 50 0000 R CNN +F 2 "" H 6050 3050 29 0000 C CNN +F 3 "" H 5850 2950 60 0000 C CNN + 1 5800 2950 + 1 0 0 1 +$EndComp +$Comp +L mosfet_n M3 +U 1 1 62DA98C5 +P 5750 3550 +F 0 "M3" H 5750 3400 50 0000 R CNN +F 1 "mosfet_n" H 5850 3500 50 0000 R CNN +F 2 "" H 6050 3250 29 0000 C CNN +F 3 "" H 5850 3350 60 0000 C CNN + 1 5750 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5950 2500 5950 2750 +Wire Wire Line + 5950 2650 6050 2650 +Wire Wire Line + 6050 2650 6050 2800 +Connection ~ 5950 2650 +Wire Wire Line + 5950 4200 5950 3950 +Wire Wire Line + 6050 3900 6050 4100 +Wire Wire Line + 6050 4100 5950 4100 +Connection ~ 5950 4100 +Wire Wire Line + 5650 2950 5650 3750 +Wire Wire Line + 5950 3150 5950 3550 +Wire Wire Line + 5950 3350 6050 3350 +Connection ~ 5950 3350 +Wire Wire Line + 5050 3350 5650 3350 +Connection ~ 5650 3350 +$Comp +L PORT U1 +U 2 1 62DA98C6 +P 5500 2050 +F 0 "U1" H 5550 2150 30 0000 C CNN +F 1 "PORT" H 5500 2050 30 0000 C CNN +F 2 "" H 5500 2050 60 0000 C CNN +F 3 "" H 5500 2050 60 0000 C CNN + 2 5500 2050 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA98C7 +P 5500 4600 +F 0 "U1" H 5550 4700 30 0000 C CNN +F 1 "PORT" H 5500 4600 30 0000 C CNN +F 2 "" H 5500 4600 60 0000 C CNN +F 3 "" H 5500 4600 60 0000 C CNN + 3 5500 4600 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 62DA98C8 +P 6300 3350 +F 0 "U1" H 6350 3450 30 0000 C CNN +F 1 "PORT" H 6300 3350 30 0000 C CNN +F 2 "" H 6300 3350 60 0000 C CNN +F 3 "" H 6300 3350 60 0000 C CNN + 4 6300 3350 + -1 0 0 1 +$EndComp +$Comp +L mosfet_p M2 +U 1 1 62DA98C9 +P 4900 2950 +F 0 "M2" H 4850 3000 50 0000 R CNN +F 1 "mosfet_p" H 4950 3100 50 0000 R CNN +F 2 "" H 5150 3050 29 0000 C CNN +F 3 "" H 4950 2950 60 0000 C CNN + 1 4900 2950 + 1 0 0 1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62DA98CA +P 4850 3550 +F 0 "M1" H 4850 3400 50 0000 R CNN +F 1 "mosfet_n" H 4950 3500 50 0000 R CNN +F 2 "" H 5150 3250 29 0000 C CNN +F 3 "" H 4950 3350 60 0000 C CNN + 1 4850 3550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 2500 5050 2750 +Wire Wire Line + 5050 2650 5150 2650 +Wire Wire Line + 5150 2650 5150 2800 +Connection ~ 5050 2650 +Wire Wire Line + 5050 3950 5050 4200 +Wire Wire Line + 5150 3900 5150 4100 +Wire Wire Line + 5150 4100 5050 4100 +Connection ~ 5050 4100 +Wire Wire Line + 4750 2950 4750 3750 +Wire Wire Line + 5050 3150 5050 3550 +Connection ~ 5050 3350 +Wire Wire Line + 4750 3350 4600 3350 +Connection ~ 4750 3350 +$Comp +L PORT U1 +U 1 1 62DA98CB +P 4350 3350 +F 0 "U1" H 4400 3450 30 0000 C CNN +F 1 "PORT" H 4350 3350 30 0000 C CNN +F 2 "" H 4350 3350 60 0000 C CNN +F 3 "" H 4350 3350 60 0000 C CNN + 1 4350 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5050 4200 5950 4200 +Wire Wire Line + 5500 4350 5500 4200 +Connection ~ 5500 4200 +Wire Wire Line + 5050 2500 5950 2500 +Wire Wire Line + 5500 2300 5500 2500 +Connection ~ 5500 2500 +$EndSCHEMATC diff --git a/Failed_subcircuits/CD_4027/cmos_buffer.sub b/Failed_subcircuits/CD_4027/cmos_buffer.sub new file mode 100644 index 000000000..5a28b2d22 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_buffer.sub @@ -0,0 +1,12 @@ +* Subcircuit cmos_buffer +.subckt cmos_buffer net-_m1-pad2_ net-_m2-pad3_ net-_m1-pad3_ net-_m3-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_buffer\cmos_buffer.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m4 net-_m3-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m3-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m2 net-_m1-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cmos_buffer \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos_buffer_Previous_Values.xml b/Failed_subcircuits/CD_4027/cmos_buffer_Previous_Values.xml new file mode 100644 index 000000000..4744e2195 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_buffer_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos_or-cache.lib b/Failed_subcircuits/CD_4027/cmos_or-cache.lib new file mode 100644 index 000000000..6c512720e --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_or-cache.lib @@ -0,0 +1,100 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD_4027/cmos_or.cir b/Failed_subcircuits/CD_4027/cmos_or.cir new file mode 100644 index 000000000..ac0eb439f --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_or.cir @@ -0,0 +1,17 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_or\cmos_or.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:23:59 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M2-Pad1_ Net-_M1-Pad2_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p +M3 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M2-Pad1_ Net-_M2-Pad3_ mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +M4 Net-_M1-Pad1_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n +U1 Net-_M1-Pad2_ Net-_M3-Pad2_ Net-_M1-Pad3_ Net-_M2-Pad3_ Net-_M5-Pad1_ PORT +M6 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M2-Pad3_ Net-_M2-Pad3_ mosfet_p +M5 Net-_M5-Pad1_ Net-_M1-Pad1_ Net-_M1-Pad3_ Net-_M1-Pad3_ mosfet_n + +.end diff --git a/Failed_subcircuits/CD_4027/cmos_or.cir.out b/Failed_subcircuits/CD_4027/cmos_or.cir.out new file mode 100644 index 000000000..5da07a14b --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_or.cir.out @@ -0,0 +1,20 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_or\cmos_or.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m2-pad1_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ net-_m2-pad3_ net-_m5-pad1_ port +m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD_4027/cmos_or.pro b/Failed_subcircuits/CD_4027/cmos_or.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_or.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD_4027/cmos_or.sch b/Failed_subcircuits/CD_4027/cmos_or.sch new file mode 100644 index 000000000..676b0d249 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_or.sch @@ -0,0 +1,277 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:cmos_or-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 62DA9496 +P 4150 2400 +F 0 "M2" H 4100 2450 50 0000 R CNN +F 1 "mosfet_p" H 4200 2550 50 0000 R CNN +F 2 "" H 4400 2500 29 0000 C CNN +F 3 "" H 4200 2400 60 0000 C CNN + 1 4150 2400 + 1 0 0 1 +$EndComp +$Comp +L mosfet_p M3 +U 1 1 62DA9497 +P 4450 3150 +F 0 "M3" H 4400 3200 50 0000 R CNN +F 1 "mosfet_p" H 4500 3300 50 0000 R CNN +F 2 "" H 4700 3250 29 0000 C CNN +F 3 "" H 4500 3150 60 0000 C CNN + 1 4450 3150 + -1 0 0 1 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62DA9498 +P 3650 3800 +F 0 "M1" H 3650 3650 50 0000 R CNN +F 1 "mosfet_n" H 3750 3750 50 0000 R CNN +F 2 "" H 3950 3500 29 0000 C CNN +F 3 "" H 3750 3600 60 0000 C CNN + 1 3650 3800 + 1 0 0 -1 +$EndComp +$Comp +L mosfet_n M4 +U 1 1 62DA9499 +P 4950 3800 +F 0 "M4" H 4950 3650 50 0000 R CNN +F 1 "mosfet_n" H 5050 3750 50 0000 R CNN +F 2 "" H 5250 3500 29 0000 C CNN +F 3 "" H 5050 3600 60 0000 C CNN + 1 4950 3800 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4300 2600 4300 2950 +Wire Wire Line + 4300 3350 4300 3600 +Wire Wire Line + 3850 3600 4750 3600 +Wire Wire Line + 3850 3600 3850 3800 +Wire Wire Line + 4750 3600 4750 3800 +Connection ~ 4300 3600 +Wire Wire Line + 4300 1850 4300 2200 +Wire Wire Line + 4300 2150 4500 2150 +Wire Wire Line + 4400 2150 4400 2250 +Connection ~ 4300 2150 +Wire Wire Line + 4200 3000 4200 2900 +Wire Wire Line + 4200 2900 4500 2900 +Wire Wire Line + 4500 2900 4500 2150 +Connection ~ 4400 2150 +Wire Wire Line + 3850 4200 3850 4350 +Wire Wire Line + 4750 4350 3850 4350 +Wire Wire Line + 4750 4200 4750 4350 +Wire Wire Line + 3950 4150 3950 4250 +Wire Wire Line + 3950 4250 3850 4250 +Connection ~ 3850 4250 +Wire Wire Line + 4650 4150 4650 4250 +Wire Wire Line + 4650 4250 4750 4250 +Connection ~ 4750 4250 +Wire Wire Line + 4000 2400 3550 2400 +Wire Wire Line + 3550 2400 3550 4000 +Wire Wire Line + 4600 3150 5050 3150 +Wire Wire Line + 5050 3150 5050 4000 +Wire Wire Line + 5050 3550 5550 3550 +Connection ~ 5050 3550 +Wire Wire Line + 3550 3050 3100 3050 +Connection ~ 3550 3050 +Wire Wire Line + 4300 3450 4850 3450 +Wire Wire Line + 4850 3450 4850 2900 +Wire Wire Line + 4850 2900 6850 2900 +Connection ~ 4300 3450 +Wire Wire Line + 4300 4350 4300 4600 +Connection ~ 4300 4350 +$Comp +L PORT U1 +U 1 1 62DA949A +P 2850 3050 +F 0 "U1" H 2900 3150 30 0000 C CNN +F 1 "PORT" H 2850 3050 30 0000 C CNN +F 2 "" H 2850 3050 60 0000 C CNN +F 3 "" H 2850 3050 60 0000 C CNN + 1 2850 3050 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62DA949B +P 5800 3550 +F 0 "U1" H 5850 3650 30 0000 C CNN +F 1 "PORT" H 5800 3550 30 0000 C CNN +F 2 "" H 5800 3550 60 0000 C CNN +F 3 "" H 5800 3550 60 0000 C CNN + 2 5800 3550 + -1 0 0 1 +$EndComp +$Comp +L mosfet_p M6 +U 1 1 62DA949C +P 7200 2500 +F 0 "M6" H 7150 2550 50 0000 R CNN +F 1 "mosfet_p" H 7250 2650 50 0000 R CNN +F 2 "" H 7450 2600 29 0000 C CNN +F 3 "" H 7250 2500 60 0000 C CNN + 1 7200 2500 + 1 0 0 1 +$EndComp +$Comp +L mosfet_n M5 +U 1 1 62DA949D +P 7150 3100 +F 0 "M5" H 7150 2950 50 0000 R CNN +F 1 "mosfet_n" H 7250 3050 50 0000 R CNN +F 2 "" H 7450 2800 29 0000 C CNN +F 3 "" H 7250 2900 60 0000 C CNN + 1 7150 3100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7350 1850 7350 2300 +Wire Wire Line + 7350 2100 7450 2100 +Wire Wire Line + 7450 2100 7450 2350 +Connection ~ 7350 2100 +Wire Wire Line + 7350 4600 7350 3500 +Wire Wire Line + 7450 3450 7450 3650 +Wire Wire Line + 7450 3650 7350 3650 +Connection ~ 7350 3650 +Wire Wire Line + 7050 2500 6850 2500 +Wire Wire Line + 6850 2500 6850 3300 +Wire Wire Line + 6850 3300 7050 3300 +Wire Wire Line + 7350 2700 7350 3100 +Wire Wire Line + 7350 2900 7950 2900 +Connection ~ 7350 2900 +Connection ~ 6850 2900 +$Comp +L PORT U1 +U 5 1 62DA949E +P 8200 2900 +F 0 "U1" H 8250 3000 30 0000 C CNN +F 1 "PORT" H 8200 2900 30 0000 C CNN +F 2 "" H 8200 2900 60 0000 C CNN +F 3 "" H 8200 2900 60 0000 C CNN + 5 8200 2900 + -1 0 0 1 +$EndComp +Wire Wire Line + 7350 1850 4300 1850 +Wire Wire Line + 4300 4600 7350 4600 +Wire Wire Line + 5800 4600 5800 5100 +Connection ~ 5800 4600 +Wire Wire Line + 5850 1850 5850 1450 +Connection ~ 5850 1850 +$Comp +L PORT U1 +U 4 1 62DA949F +P 5850 1200 +F 0 "U1" H 5900 1300 30 0000 C CNN +F 1 "PORT" H 5850 1200 30 0000 C CNN +F 2 "" H 5850 1200 60 0000 C CNN +F 3 "" H 5850 1200 60 0000 C CNN + 4 5850 1200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA94A0 +P 5800 5350 +F 0 "U1" H 5850 5450 30 0000 C CNN +F 1 "PORT" H 5800 5350 30 0000 C CNN +F 2 "" H 5800 5350 60 0000 C CNN +F 3 "" H 5800 5350 60 0000 C CNN + 3 5800 5350 + 0 -1 -1 0 +$EndComp +$EndSCHEMATC diff --git a/Failed_subcircuits/CD_4027/cmos_or.sub b/Failed_subcircuits/CD_4027/cmos_or.sub new file mode 100644 index 000000000..e8f56ac0b --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_or.sub @@ -0,0 +1,14 @@ +* Subcircuit cmos_or +.subckt cmos_or net-_m1-pad2_ net-_m3-pad2_ net-_m1-pad3_ net-_m2-pad3_ net-_m5-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_or\cmos_or.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m2-pad1_ net-_m1-pad2_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m3 net-_m1-pad1_ net-_m3-pad2_ net-_m2-pad1_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m4 net-_m1-pad1_ net-_m3-pad2_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +m6 net-_m5-pad1_ net-_m1-pad1_ net-_m2-pad3_ net-_m2-pad3_ CMOSP W=100u L=100u M=1 +m5 net-_m5-pad1_ net-_m1-pad1_ net-_m1-pad3_ net-_m1-pad3_ CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cmos_or \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos_or_Previous_Values.xml b/Failed_subcircuits/CD_4027/cmos_or_Previous_Values.xml new file mode 100644 index 000000000..0a2091c06 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_or_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos_tg-cache.lib b/Failed_subcircuits/CD_4027/cmos_tg-cache.lib new file mode 100644 index 000000000..4f6bd0acf --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_tg-cache.lib @@ -0,0 +1,113 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# GND +# +DEF GND #PWR 0 0 Y Y 1 F P +F0 "#PWR" 0 -250 50 H I C CNN +F1 "GND" 0 -150 50 H V C CNN +F2 "" 0 0 50 H I C CNN +F3 "" 0 0 50 H I C CNN +DRAW +P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N +X GND 1 0 0 0 D 50 50 1 1 W N +ENDDRAW +ENDDEF +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_MOS_N +# +DEF eSim_MOS_N M 0 0 Y N 1 F N +F0 "M" 0 -150 50 H V R CNN +F1 "eSim_MOS_N" 100 -50 50 H V R CNN +F2 "" 300 -300 29 H V C CNN +F3 "" 100 -200 60 H V C CNN +ALIAS mosfet_n +DRAW +C 150 -200 111 0 1 10 N +P 2 0 1 10 130 -290 130 -250 N +P 2 0 1 0 130 -270 200 -270 N +P 2 0 1 10 130 -220 130 -180 N +P 2 0 1 0 130 -200 200 -200 N +P 2 0 1 10 130 -150 130 -110 N +P 2 0 1 0 130 -130 200 -130 N +P 2 0 1 0 200 -300 200 -270 N +P 2 0 1 0 200 -130 200 -100 N +P 3 0 1 10 110 -275 110 -125 110 -125 N +P 3 0 1 0 200 -200 300 -200 300 -250 N +P 4 0 1 0 140 -200 180 -215 180 -185 140 -200 F +X D 1 200 0 100 D 50 50 1 1 P +X G 2 -100 -200 210 R 50 50 1 1 P +X S 3 200 -400 100 U 50 50 1 1 P +X B 4 300 -350 98 U 47 47 1 1 P +ENDDRAW +ENDDEF +# +# eSim_MOS_P +# +DEF eSim_MOS_P M 0 0 Y N 1 F N +F0 "M" -50 50 50 H V R CNN +F1 "eSim_MOS_P" 50 150 50 H V R CNN +F2 "" 250 100 29 H V C CNN +F3 "" 50 0 60 H V C CNN +ALIAS mosfet_p +DRAW +C 100 0 111 0 1 10 N +P 2 0 1 0 80 -70 150 -70 N +P 2 0 1 10 80 -50 80 -90 N +P 2 0 1 0 80 0 150 0 N +P 2 0 1 10 80 20 80 -20 N +P 2 0 1 0 80 70 150 70 N +P 2 0 1 10 80 90 80 50 N +P 2 0 1 0 150 -70 150 -100 N +P 2 0 1 0 150 100 150 70 N +P 3 0 1 10 60 75 60 -75 60 -75 N +P 3 0 1 0 150 0 250 0 250 -50 N +P 4 0 1 0 140 0 100 -15 100 15 140 0 F +X D 1 150 200 100 D 50 50 1 1 P +X G 2 -150 0 210 R 50 50 1 1 P +X S 3 150 -200 100 U 50 50 1 1 P +X B 4 250 -150 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/CD_4027/cmos_tg.cir b/Failed_subcircuits/CD_4027/cmos_tg.cir new file mode 100644 index 000000000..5126e30c2 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_tg.cir @@ -0,0 +1,13 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\cmos_tg\cmos_tg.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/22/22 18:31:42 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +M2 Net-_M1-Pad3_ Net-_M2-Pad2_ Net-_M1-Pad1_ Net-_M1-Pad2_ mosfet_p +M1 Net-_M1-Pad1_ Net-_M1-Pad2_ Net-_M1-Pad3_ GND mosfet_n +U1 Net-_M1-Pad1_ Net-_M2-Pad2_ Net-_M1-Pad2_ Net-_M1-Pad3_ PORT + +.end diff --git a/Failed_subcircuits/CD_4027/cmos_tg.cir.out b/Failed_subcircuits/CD_4027/cmos_tg.cir.out new file mode 100644 index 000000000..44fe2c288 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_tg.cir.out @@ -0,0 +1,16 @@ +* c:\fossee\esim\library\subcircuitlibrary\cmos_tg\cmos_tg.cir + +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad1_ net-_m1-pad2_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* u1 net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad2_ net-_m1-pad3_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/CD_4027/cmos_tg.pro b/Failed_subcircuits/CD_4027/cmos_tg.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_tg.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/CD_4027/cmos_tg.sch b/Failed_subcircuits/CD_4027/cmos_tg.sch new file mode 100644 index 000000000..92a4f7ae3 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_tg.sch @@ -0,0 +1,163 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:cmos_tg-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L mosfet_p M2 +U 1 1 62DA99E3 +P 5850 2700 +F 0 "M2" H 5800 2750 50 0000 R CNN +F 1 "mosfet_p" H 5900 2850 50 0000 R CNN +F 2 "" H 6100 2800 29 0000 C CNN +F 3 "" H 5900 2700 60 0000 C CNN + 1 5850 2700 + 0 1 1 0 +$EndComp +$Comp +L mosfet_n M1 +U 1 1 62DA99E4 +P 5650 3850 +F 0 "M1" H 5650 3700 50 0000 R CNN +F 1 "mosfet_n" H 5750 3800 50 0000 R CNN +F 2 "" H 5950 3550 29 0000 C CNN +F 3 "" H 5750 3650 60 0000 C CNN + 1 5650 3850 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5400 3650 5650 3650 +Wire Wire Line + 5400 2850 5400 3650 +Wire Wire Line + 5400 2850 5650 2850 +Wire Wire Line + 6300 3650 6050 3650 +Wire Wire Line + 6300 2850 6300 3650 +Wire Wire Line + 6300 2850 6050 2850 +Wire Wire Line + 6300 3250 6500 3250 +Connection ~ 6300 3250 +Wire Wire Line + 5400 3200 5200 3200 +Connection ~ 5400 3200 +Wire Wire Line + 5850 2550 5850 2350 +Wire Wire Line + 5850 3950 5850 4200 +$Comp +L GND #PWR1 +U 1 1 62DA99E5 +P 6150 3550 +F 0 "#PWR1" H 6150 3300 50 0001 C CNN +F 1 "GND" H 6150 3400 50 0000 C CNN +F 2 "" H 6150 3550 50 0001 C CNN +F 3 "" H 6150 3550 50 0001 C CNN + 1 6150 3550 + -1 0 0 1 +$EndComp +Wire Wire Line + 6150 3550 6000 3550 +Wire Wire Line + 5700 2950 5550 2950 +Wire Wire Line + 5550 2950 5550 4000 +Wire Wire Line + 5550 4000 5850 4000 +Connection ~ 5850 4000 +$Comp +L PORT U1 +U 1 1 62DA99E6 +P 4950 3200 +F 0 "U1" H 5000 3300 30 0000 C CNN +F 1 "PORT" H 4950 3200 30 0000 C CNN +F 2 "" H 4950 3200 60 0000 C CNN +F 3 "" H 4950 3200 60 0000 C CNN + 1 4950 3200 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 62DA99E7 +P 5850 2100 +F 0 "U1" H 5900 2200 30 0000 C CNN +F 1 "PORT" H 5850 2100 30 0000 C CNN +F 2 "" H 5850 2100 60 0000 C CNN +F 3 "" H 5850 2100 60 0000 C CNN + 2 5850 2100 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 62DA99E8 +P 5850 4450 +F 0 "U1" H 5900 4550 30 0000 C CNN +F 1 "PORT" H 5850 4450 30 0000 C CNN +F 2 "" H 5850 4450 60 0000 C CNN +F 3 "" H 5850 4450 60 0000 C CNN + 3 5850 4450 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 62DA99E9 +P 6750 3250 +F 0 "U1" H 6800 3350 30 0000 C CNN +F 1 "PORT" H 6750 3250 30 0000 C CNN +F 2 "" H 6750 3250 60 0000 C CNN +F 3 "" H 6750 3250 60 0000 C CNN + 4 6750 3250 + -1 0 0 1 +$EndComp +$EndSCHEMATC diff --git a/Failed_subcircuits/CD_4027/cmos_tg.sub b/Failed_subcircuits/CD_4027/cmos_tg.sub new file mode 100644 index 000000000..fe9ff9579 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_tg.sub @@ -0,0 +1,10 @@ +* Subcircuit cmos_tg +.subckt cmos_tg net-_m1-pad1_ net-_m2-pad2_ net-_m1-pad2_ net-_m1-pad3_ +* c:\fossee\esim\library\subcircuitlibrary\cmos_tg\cmos_tg.cir +.include PMOS-180nm.lib +.include NMOS-180nm.lib +m2 net-_m1-pad3_ net-_m2-pad2_ net-_m1-pad1_ net-_m1-pad2_ CMOSP W=100u L=100u M=1 +m1 net-_m1-pad1_ net-_m1-pad2_ net-_m1-pad3_ gnd CMOSN W=100u L=100u M=1 +* Control Statements + +.ends cmos_tg \ No newline at end of file diff --git a/Failed_subcircuits/CD_4027/cmos_tg_Previous_Values.xml b/Failed_subcircuits/CD_4027/cmos_tg_Previous_Values.xml new file mode 100644 index 000000000..0388b42b0 --- /dev/null +++ b/Failed_subcircuits/CD_4027/cmos_tg_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\MOS\PMOS-180nm.libC:\FOSSEE\eSim\library\deviceModelLibrary\MOS\NMOS-180nm.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/ICL8038/CBAT54_Schottky.lib b/Failed_subcircuits/ICL8038/CBAT54_Schottky.lib new file mode 100644 index 000000000..258626e9a --- /dev/null +++ b/Failed_subcircuits/ICL8038/CBAT54_Schottky.lib @@ -0,0 +1,13 @@ +.MODEL CBAT54 D ++ IS=16.999E-9 ++ N=1.0057 ++ RS=.85033 ++ IKF=49.383E-3 ++ CJO=9.8624E-12 ++ M=1.9579 ++ VJ=9.9900 ++ ISR=170.34E-9 ++ NR=4.9950 ++ BV=30.194 ++ IBV=3.9188E-3 ++ TT=7.2135E-9 diff --git a/Failed_subcircuits/ICL8038/D.lib b/Failed_subcircuits/ICL8038/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/Failed_subcircuits/ICL8038/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/Failed_subcircuits/ICL8038/ICL8038-cache.lib b/Failed_subcircuits/ICL8038/ICL8038-cache.lib new file mode 100644 index 000000000..fa8f67b21 --- /dev/null +++ b/Failed_subcircuits/ICL8038/ICL8038-cache.lib @@ -0,0 +1,126 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/ICL8038/ICL8038.cir b/Failed_subcircuits/ICL8038/ICL8038.cir new file mode 100644 index 000000000..195f88fb1 --- /dev/null +++ b/Failed_subcircuits/ICL8038/ICL8038.cir @@ -0,0 +1,120 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\ICL8038\ICL8038.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 09/14/22 23:03:48 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q51 Net-_Q10-Pad1_ Net-_Q51-Pad2_ Net-_Q49-Pad2_ eSim_NPN +Q49 Net-_D4-Pad2_ Net-_Q49-Pad2_ Net-_Q49-Pad3_ eSim_PNP +Q47 Net-_Q10-Pad1_ Net-_Q47-Pad2_ Net-_Q45-Pad2_ eSim_NPN +Q45 Net-_D4-Pad2_ Net-_Q45-Pad2_ Net-_Q45-Pad3_ eSim_PNP +Q43 Net-_Q10-Pad1_ Net-_Q43-Pad2_ Net-_Q41-Pad2_ eSim_NPN +Q41 Net-_D4-Pad2_ Net-_Q41-Pad2_ Net-_Q41-Pad3_ eSim_PNP +Q39 Net-_Q10-Pad1_ Net-_Q39-Pad2_ Net-_Q37-Pad2_ eSim_NPN +Q37 Net-_D4-Pad2_ Net-_Q37-Pad2_ Net-_Q37-Pad3_ eSim_PNP +Q38 Net-_Q10-Pad1_ Net-_Q38-Pad2_ Net-_Q38-Pad3_ eSim_NPN +Q40 Net-_D4-Pad2_ Net-_Q40-Pad2_ Net-_Q38-Pad2_ eSim_PNP +Q44 Net-_D4-Pad2_ Net-_Q44-Pad2_ Net-_Q42-Pad2_ eSim_PNP +Q42 Net-_Q10-Pad1_ Net-_Q42-Pad2_ Net-_Q42-Pad3_ eSim_NPN +Q46 Net-_Q10-Pad1_ Net-_Q46-Pad2_ Net-_Q46-Pad3_ eSim_NPN +Q48 Net-_D4-Pad2_ Net-_Q48-Pad2_ Net-_Q46-Pad2_ eSim_PNP +Q52 Net-_D4-Pad2_ Net-_Q52-Pad2_ Net-_Q50-Pad2_ eSim_PNP +Q50 Net-_Q10-Pad1_ Net-_Q50-Pad2_ Net-_Q49-Pad3_ eSim_NPN +Q33 Net-_Q10-Pad1_ Net-_Q33-Pad2_ Net-_Q31-Pad2_ eSim_NPN +Q31 Net-_Q10-Pad1_ Net-_Q31-Pad2_ Net-_Q27-Pad3_ eSim_NPN +Q24 Net-_Q22-Pad2_ Net-_Q16-Pad3_ Net-_Q24-Pad3_ eSim_NPN +Q27 Net-_Q22-Pad2_ Net-_Q24-Pad3_ Net-_Q27-Pad3_ eSim_NPN +Q28 Net-_D8-Pad1_ Net-_Q25-Pad3_ Net-_Q28-Pad3_ eSim_PNP +Q25 Net-_D8-Pad1_ Net-_Q16-Pad3_ Net-_Q25-Pad3_ eSim_PNP +Q32 Net-_D4-Pad2_ Net-_Q32-Pad2_ Net-_Q28-Pad3_ eSim_PNP +Q34 Net-_D4-Pad2_ Net-_Q34-Pad2_ Net-_Q32-Pad2_ eSim_PNP +Q29 Net-_Q29-Pad1_ Net-_Q29-Pad1_ Net-_Q29-Pad3_ eSim_NPN +Q35 Net-_Q10-Pad1_ Net-_Q29-Pad1_ Net-_Q35-Pad3_ eSim_NPN +Q30 Net-_D4-Pad2_ Net-_Q26-Pad3_ Net-_Q29-Pad3_ eSim_PNP +Q36 Net-_D4-Pad2_ Net-_Q26-Pad3_ Net-_Q35-Pad3_ eSim_PNP +Q22 Net-_D9-Pad1_ Net-_Q22-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q10-Pad1_ Net-_Q14-Pad1_ Net-_Q15-Pad3_ eSim_NPN +Q16 Net-_Q15-Pad3_ Net-_Q15-Pad3_ Net-_Q16-Pad3_ eSim_NPN +Q8 Net-_Q10-Pad2_ Net-_Q14-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_Q10-Pad3_ Net-_Q10-Pad3_ Net-_D5-Pad2_ eSim_NPN +Q4 Net-_Q10-Pad1_ Net-_Q3-Pad3_ Net-_Q14-Pad2_ eSim_NPN +Q3 Net-_Q14-Pad2_ Net-_Q14-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q6 Net-_Q14-Pad2_ Net-_Q10-Pad3_ Net-_Q6-Pad3_ eSim_NPN +Q17 Net-_Q16-Pad3_ Net-_D5-Pad2_ Net-_Q12-Pad1_ eSim_NPN +Q18 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q18-Pad3_ eSim_NPN +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_NPN +Q7 Net-_D5-Pad2_ Net-_Q12-Pad1_ Net-_Q7-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_D1-Pad1_ Net-_Q1-Pad3_ eSim_NPN +Q5 Net-_Q1-Pad1_ Net-_D6-Pad2_ Net-_Q5-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q2-Pad2_ Net-_D4-Pad2_ eSim_NPN +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D1-Pad2_ Net-_D2-Pad2_ eSim_Diode +D3 Net-_D2-Pad2_ Net-_D3-Pad2_ eSim_Diode +D4 Net-_D3-Pad2_ Net-_D4-Pad2_ eSim_Diode +R1 Net-_Q1-Pad1_ Net-_D1-Pad1_ 30k +R4 Net-_Q5-Pad3_ Net-_Q2-Pad2_ 270 +R5 Net-_Q2-Pad2_ Net-_D4-Pad2_ 2.7k +R10 Net-_D6-Pad1_ Net-_D5-Pad1_ 470 +R11 Net-_D7-Pad1_ Net-_D6-Pad2_ 27k +Q21 Net-_D6-Pad1_ Net-_D9-Pad1_ Net-_D4-Pad2_ eSim_NPN +R8 Net-_Q1-Pad3_ Net-_D6-Pad2_ 620 +R13 Net-_Q1-Pad3_ Net-_D6-Pad1_ 1.8k +R9 Net-_Q12-Pad3_ Net-_D4-Pad2_ 100 +R7 Net-_Q7-Pad3_ Net-_D4-Pad2_ 100 +R12 Net-_Q18-Pad3_ Net-_D4-Pad2_ 100 +Q26 Net-_Q10-Pad1_ Net-_Q23-Pad3_ Net-_Q26-Pad3_ eSim_NPN +Q23 Net-_Q10-Pad1_ Net-_Q15-Pad3_ Net-_Q23-Pad3_ eSim_NPN +R16 Net-_Q23-Pad3_ Net-_Q26-Pad3_ 27k +R18 Net-_Q26-Pad3_ Net-_D4-Pad2_ 27k +R20 Net-_Q10-Pad1_ Net-_Q29-Pad1_ 27k +R14 Net-_D4-Pad2_ Net-_D8-Pad1_ 4.7k +R15 Net-_D4-Pad2_ Net-_D9-Pad1_ 4.7k +R6 Net-_Q6-Pad3_ Net-_D5-Pad2_ 40k +R2 Net-_Q10-Pad1_ Net-_R2-Pad2_ 11k +R3 Net-_R2-Pad2_ Net-_D4-Pad2_ 39k +R17 Net-_Q10-Pad1_ Net-_Q22-Pad2_ 4k +R22 Net-_Q10-Pad1_ Net-_Q33-Pad2_ 5k +R23 Net-_Q33-Pad2_ Net-_Q34-Pad2_ 5k +R24 Net-_Q34-Pad2_ Net-_D4-Pad2_ 5k +R19 Net-_Q28-Pad3_ Net-_Q10-Pad1_ 15k +R21 Net-_D4-Pad2_ Net-_Q27-Pad3_ 10k +R26 Net-_Q45-Pad3_ Net-_Q49-Pad3_ 800 +R27 Net-_Q41-Pad3_ Net-_Q49-Pad3_ 2.7k +R28 Net-_Q37-Pad3_ Net-_Q49-Pad3_ 10k +R31 Net-_Q46-Pad3_ Net-_Q49-Pad3_ 800 +R30 Net-_Q42-Pad3_ Net-_Q49-Pad3_ 2.7k +R29 Net-_Q38-Pad3_ Net-_Q49-Pad3_ 10k +R35 Net-_Q10-Pad1_ Net-_Q42-Pad2_ 33k +R37 Net-_Q10-Pad1_ Net-_Q46-Pad2_ 33k +R39 Net-_Q10-Pad1_ Net-_Q50-Pad2_ 33k +R32 Net-_Q37-Pad2_ Net-_D4-Pad2_ 33k +R34 Net-_Q41-Pad2_ Net-_D4-Pad2_ 33k +R36 Net-_Q45-Pad2_ Net-_D4-Pad2_ 33k +R38 Net-_Q49-Pad2_ Net-_D4-Pad2_ 33k +R44 Net-_Q39-Pad2_ Net-_Q40-Pad2_ 1600 +R45 Net-_Q40-Pad2_ Net-_Q44-Pad2_ 330 +R46 Net-_Q44-Pad2_ Net-_Q48-Pad2_ 375 +R47 Net-_Q48-Pad2_ Net-_Q52-Pad2_ 200 +R48 Net-_Q52-Pad2_ Net-_D4-Pad2_ 5.6k +R43 Net-_Q43-Pad2_ Net-_Q39-Pad2_ 330 +R42 Net-_Q47-Pad2_ Net-_Q43-Pad2_ 375 +R41 Net-_Q51-Pad2_ Net-_Q47-Pad2_ 200 +R40 Net-_Q10-Pad1_ Net-_Q51-Pad2_ 5.2k +R25 Net-_Q35-Pad3_ Net-_Q49-Pad3_ 1k +U1 Net-_Q2-Pad1_ Net-_R2-Pad2_ Net-_Q3-Pad3_ Net-_Q10-Pad1_ Net-_Q10-Pad1_ Net-_Q16-Pad3_ Net-_D4-Pad2_ Net-_Q35-Pad3_ Net-_Q49-Pad3_ Net-_Q10-Pad1_ Net-_Q51-Pad2_ Net-_Q52-Pad2_ ? ? PORT +R33 Net-_Q10-Pad1_ Net-_Q38-Pad2_ 33k +Q9 Net-_D5-Pad2_ Net-_D5-Pad1_ Net-_D4-Pad2_ eSim_NPN +D5 Net-_D5-Pad1_ Net-_D5-Pad2_ eSim_Diode +D9 Net-_D9-Pad1_ Net-_D6-Pad1_ eSim_Diode +Q19 Net-_D7-Pad1_ Net-_D8-Pad1_ Net-_D4-Pad2_ eSim_NPN +D8 Net-_D8-Pad1_ Net-_D7-Pad1_ eSim_Diode +Q13 Net-_D6-Pad2_ Net-_D6-Pad1_ Net-_D4-Pad2_ eSim_NPN +D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode +Q20 Net-_D6-Pad1_ Net-_D7-Pad1_ Net-_D4-Pad2_ eSim_NPN +D7 Net-_D7-Pad1_ Net-_D6-Pad1_ eSim_Diode + +.end diff --git a/Failed_subcircuits/ICL8038/ICL8038.cir.out b/Failed_subcircuits/ICL8038/ICL8038.cir.out new file mode 100644 index 000000000..71cc36cce --- /dev/null +++ b/Failed_subcircuits/ICL8038/ICL8038.cir.out @@ -0,0 +1,125 @@ +* c:\fossee\esim\library\subcircuitlibrary\icl8038\icl8038.cir + +.include CBAT54_Schottky.lib +.include PNP.lib +.include D.lib +.include NPN.lib +q51 net-_q10-pad1_ net-_q51-pad2_ net-_q49-pad2_ Q2N2222 +q49 net-_d4-pad2_ net-_q49-pad2_ net-_q49-pad3_ Q2N2907A +q47 net-_q10-pad1_ net-_q47-pad2_ net-_q45-pad2_ Q2N2222 +q45 net-_d4-pad2_ net-_q45-pad2_ net-_q45-pad3_ Q2N2907A +q43 net-_q10-pad1_ net-_q43-pad2_ net-_q41-pad2_ Q2N2222 +q41 net-_d4-pad2_ net-_q41-pad2_ net-_q41-pad3_ Q2N2907A +q39 net-_q10-pad1_ net-_q39-pad2_ net-_q37-pad2_ Q2N2222 +q37 net-_d4-pad2_ net-_q37-pad2_ net-_q37-pad3_ Q2N2907A +q38 net-_q10-pad1_ net-_q38-pad2_ net-_q38-pad3_ Q2N2222 +q40 net-_d4-pad2_ net-_q40-pad2_ net-_q38-pad2_ Q2N2907A +q44 net-_d4-pad2_ net-_q44-pad2_ net-_q42-pad2_ Q2N2907A +q42 net-_q10-pad1_ net-_q42-pad2_ net-_q42-pad3_ Q2N2222 +q46 net-_q10-pad1_ net-_q46-pad2_ net-_q46-pad3_ Q2N2222 +q48 net-_d4-pad2_ net-_q48-pad2_ net-_q46-pad2_ Q2N2907A +q52 net-_d4-pad2_ net-_q52-pad2_ net-_q50-pad2_ Q2N2907A +q50 net-_q10-pad1_ net-_q50-pad2_ net-_q49-pad3_ Q2N2222 +q33 net-_q10-pad1_ net-_q33-pad2_ net-_q31-pad2_ Q2N2222 +q31 net-_q10-pad1_ net-_q31-pad2_ net-_q27-pad3_ Q2N2222 +q24 net-_q22-pad2_ net-_q16-pad3_ net-_q24-pad3_ Q2N2222 +q27 net-_q22-pad2_ net-_q24-pad3_ net-_q27-pad3_ Q2N2222 +q28 net-_d8-pad1_ net-_q25-pad3_ net-_q28-pad3_ Q2N2907A +q25 net-_d8-pad1_ net-_q16-pad3_ net-_q25-pad3_ Q2N2907A +q32 net-_d4-pad2_ net-_q32-pad2_ net-_q28-pad3_ Q2N2907A +q34 net-_d4-pad2_ net-_q34-pad2_ net-_q32-pad2_ Q2N2907A +q29 net-_q29-pad1_ net-_q29-pad1_ net-_q29-pad3_ Q2N2222 +q35 net-_q10-pad1_ net-_q29-pad1_ net-_q35-pad3_ Q2N2222 +q30 net-_d4-pad2_ net-_q26-pad3_ net-_q29-pad3_ Q2N2907A +q36 net-_d4-pad2_ net-_q26-pad3_ net-_q35-pad3_ Q2N2907A +q22 net-_d9-pad1_ net-_q22-pad2_ net-_q10-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q14-pad2_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q14-pad1_ net-_q15-pad3_ Q2N2222 +q16 net-_q15-pad3_ net-_q15-pad3_ net-_q16-pad3_ Q2N2222 +q8 net-_q10-pad2_ net-_q14-pad2_ net-_q10-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_q10-pad3_ net-_q10-pad3_ net-_d5-pad2_ Q2N2222 +q4 net-_q10-pad1_ net-_q3-pad3_ net-_q14-pad2_ Q2N2222 +q3 net-_q14-pad2_ net-_q14-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_q14-pad2_ net-_q10-pad3_ net-_q6-pad3_ Q2N2222 +q17 net-_q16-pad3_ net-_d5-pad2_ net-_q12-pad1_ Q2N2222 +q18 net-_q12-pad1_ net-_q12-pad1_ net-_q18-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2222 +q7 net-_d5-pad2_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_d1-pad1_ net-_q1-pad3_ Q2N2222 +q5 net-_q1-pad1_ net-_d6-pad2_ net-_q5-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_d4-pad2_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_d3-pad2_ 1N4148 +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +r1 net-_q1-pad1_ net-_d1-pad1_ 30k +r4 net-_q5-pad3_ net-_q2-pad2_ 270 +r5 net-_q2-pad2_ net-_d4-pad2_ 2.7k +r10 net-_d6-pad1_ net-_d5-pad1_ 470 +r11 net-_d7-pad1_ net-_d6-pad2_ 27k +q21 net-_d6-pad1_ net-_d9-pad1_ net-_d4-pad2_ Q2N2222 +r8 net-_q1-pad3_ net-_d6-pad2_ 620 +r13 net-_q1-pad3_ net-_d6-pad1_ 1.8k +r9 net-_q12-pad3_ net-_d4-pad2_ 100 +r7 net-_q7-pad3_ net-_d4-pad2_ 100 +r12 net-_q18-pad3_ net-_d4-pad2_ 100 +q26 net-_q10-pad1_ net-_q23-pad3_ net-_q26-pad3_ Q2N2222 +q23 net-_q10-pad1_ net-_q15-pad3_ net-_q23-pad3_ Q2N2222 +r16 net-_q23-pad3_ net-_q26-pad3_ 27k +r18 net-_q26-pad3_ net-_d4-pad2_ 27k +r20 net-_q10-pad1_ net-_q29-pad1_ 27k +r14 net-_d4-pad2_ net-_d8-pad1_ 4.7k +r15 net-_d4-pad2_ net-_d9-pad1_ 4.7k +r6 net-_q6-pad3_ net-_d5-pad2_ 40k +r2 net-_q10-pad1_ net-_r2-pad2_ 11k +r3 net-_r2-pad2_ net-_d4-pad2_ 39k +r17 net-_q10-pad1_ net-_q22-pad2_ 4k +r22 net-_q10-pad1_ net-_q33-pad2_ 5k +r23 net-_q33-pad2_ net-_q34-pad2_ 5k +r24 net-_q34-pad2_ net-_d4-pad2_ 5k +r19 net-_q28-pad3_ net-_q10-pad1_ 15k +r21 net-_d4-pad2_ net-_q27-pad3_ 10k +r26 net-_q45-pad3_ net-_q49-pad3_ 800 +r27 net-_q41-pad3_ net-_q49-pad3_ 2.7k +r28 net-_q37-pad3_ net-_q49-pad3_ 10k +r31 net-_q46-pad3_ net-_q49-pad3_ 800 +r30 net-_q42-pad3_ net-_q49-pad3_ 2.7k +r29 net-_q38-pad3_ net-_q49-pad3_ 10k +r35 net-_q10-pad1_ net-_q42-pad2_ 33k +r37 net-_q10-pad1_ net-_q46-pad2_ 33k +r39 net-_q10-pad1_ net-_q50-pad2_ 33k +r32 net-_q37-pad2_ net-_d4-pad2_ 33k +r34 net-_q41-pad2_ net-_d4-pad2_ 33k +r36 net-_q45-pad2_ net-_d4-pad2_ 33k +r38 net-_q49-pad2_ net-_d4-pad2_ 33k +r44 net-_q39-pad2_ net-_q40-pad2_ 1600 +r45 net-_q40-pad2_ net-_q44-pad2_ 330 +r46 net-_q44-pad2_ net-_q48-pad2_ 375 +r47 net-_q48-pad2_ net-_q52-pad2_ 200 +r48 net-_q52-pad2_ net-_d4-pad2_ 5.6k +r43 net-_q43-pad2_ net-_q39-pad2_ 330 +r42 net-_q47-pad2_ net-_q43-pad2_ 375 +r41 net-_q51-pad2_ net-_q47-pad2_ 200 +r40 net-_q10-pad1_ net-_q51-pad2_ 5.2k +r25 net-_q35-pad3_ net-_q49-pad3_ 1k +* u1 net-_q2-pad1_ net-_r2-pad2_ net-_q3-pad3_ net-_q10-pad1_ net-_q10-pad1_ net-_q16-pad3_ net-_d4-pad2_ net-_q35-pad3_ net-_q49-pad3_ net-_q10-pad1_ net-_q51-pad2_ net-_q52-pad2_ ? ? port +r33 net-_q10-pad1_ net-_q38-pad2_ 33k +q9 net-_d5-pad2_ net-_d5-pad1_ net-_d4-pad2_ Q2N2222 +d5 net-_d5-pad1_ net-_d5-pad2_ CBAT54 +d9 net-_d9-pad1_ net-_d6-pad1_ CBAT54 +q19 net-_d7-pad1_ net-_d8-pad1_ net-_d4-pad2_ Q2N2222 +d8 net-_d8-pad1_ net-_d7-pad1_ CBAT54 +q13 net-_d6-pad2_ net-_d6-pad1_ net-_d4-pad2_ Q2N2222 +d6 net-_d6-pad1_ net-_d6-pad2_ CBAT54 +q20 net-_d6-pad1_ net-_d7-pad1_ net-_d4-pad2_ Q2N2222 +d7 net-_d7-pad1_ net-_d6-pad1_ CBAT54 +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/ICL8038/ICL8038.pro b/Failed_subcircuits/ICL8038/ICL8038.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/ICL8038/ICL8038.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/ICL8038/ICL8038.sch b/Failed_subcircuits/ICL8038/ICL8038.sch new file mode 100644 index 000000000..1b326268f --- /dev/null +++ b/Failed_subcircuits/ICL8038/ICL8038.sch @@ -0,0 +1,2077 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:ICL8038-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q51 +U 1 1 63038149 +P 24500 700 +F 0 "Q51" H 24400 750 50 0000 R CNN +F 1 "eSim_NPN" H 24450 850 50 0000 R CNN +F 2 "" H 24700 800 29 0000 C CNN +F 3 "" H 24500 700 60 0000 C CNN + 1 24500 700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q49 +U 1 1 6303814A +P 24100 1050 +F 0 "Q49" H 24000 1100 50 0000 R CNN +F 1 "eSim_PNP" H 24050 1200 50 0000 R CNN +F 2 "" H 24300 1150 29 0000 C CNN +F 3 "" H 24100 1050 60 0000 C CNN + 1 24100 1050 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q47 +U 1 1 6303814B +P 23700 1400 +F 0 "Q47" H 23600 1450 50 0000 R CNN +F 1 "eSim_NPN" H 23650 1550 50 0000 R CNN +F 2 "" H 23900 1500 29 0000 C CNN +F 3 "" H 23700 1400 60 0000 C CNN + 1 23700 1400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q45 +U 1 1 6303814C +P 23250 1700 +F 0 "Q45" H 23150 1750 50 0000 R CNN +F 1 "eSim_PNP" H 23200 1850 50 0000 R CNN +F 2 "" H 23450 1800 29 0000 C CNN +F 3 "" H 23250 1700 60 0000 C CNN + 1 23250 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q43 +U 1 1 6303814D +P 22800 2100 +F 0 "Q43" H 22700 2150 50 0000 R CNN +F 1 "eSim_NPN" H 22750 2250 50 0000 R CNN +F 2 "" H 23000 2200 29 0000 C CNN +F 3 "" H 22800 2100 60 0000 C CNN + 1 22800 2100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q41 +U 1 1 6303814E +P 22400 2450 +F 0 "Q41" H 22300 2500 50 0000 R CNN +F 1 "eSim_PNP" H 22350 2600 50 0000 R CNN +F 2 "" H 22600 2550 29 0000 C CNN +F 3 "" H 22400 2450 60 0000 C CNN + 1 22400 2450 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q39 +U 1 1 6303814F +P 22000 2850 +F 0 "Q39" H 21900 2900 50 0000 R CNN +F 1 "eSim_NPN" H 21950 3000 50 0000 R CNN +F 2 "" H 22200 2950 29 0000 C CNN +F 3 "" H 22000 2850 60 0000 C CNN + 1 22000 2850 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q37 +U 1 1 63038150 +P 21550 3200 +F 0 "Q37" H 21450 3250 50 0000 R CNN +F 1 "eSim_PNP" H 21750 3350 50 0000 R CNN +F 2 "" H 21750 3300 29 0000 C CNN +F 3 "" H 21550 3200 60 0000 C CNN + 1 21550 3200 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q38 +U 1 1 63038151 +P 21750 4450 +F 0 "Q38" H 21650 4500 50 0000 R CNN +F 1 "eSim_NPN" H 22000 4300 50 0000 R CNN +F 2 "" H 21950 4550 29 0000 C CNN +F 3 "" H 21750 4450 60 0000 C CNN + 1 21750 4450 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q40 +U 1 1 63038152 +P 22150 4700 +F 0 "Q40" H 22050 4750 50 0000 R CNN +F 1 "eSim_PNP" H 22100 4850 50 0000 R CNN +F 2 "" H 22350 4800 29 0000 C CNN +F 3 "" H 22150 4700 60 0000 C CNN + 1 22150 4700 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q44 +U 1 1 63038153 +P 23000 5300 +F 0 "Q44" H 22900 5350 50 0000 R CNN +F 1 "eSim_PNP" H 22950 5450 50 0000 R CNN +F 2 "" H 23200 5400 29 0000 C CNN +F 3 "" H 23000 5300 60 0000 C CNN + 1 23000 5300 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q42 +U 1 1 63038154 +P 22600 5000 +F 0 "Q42" H 22500 5050 50 0000 R CNN +F 1 "eSim_NPN" H 22550 5150 50 0000 R CNN +F 2 "" H 22800 5100 29 0000 C CNN +F 3 "" H 22600 5000 60 0000 C CNN + 1 22600 5000 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q46 +U 1 1 63038155 +P 23400 5600 +F 0 "Q46" H 23300 5650 50 0000 R CNN +F 1 "eSim_NPN" H 23350 5750 50 0000 R CNN +F 2 "" H 23600 5700 29 0000 C CNN +F 3 "" H 23400 5600 60 0000 C CNN + 1 23400 5600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q48 +U 1 1 63038156 +P 23800 5900 +F 0 "Q48" H 23700 5950 50 0000 R CNN +F 1 "eSim_PNP" H 23750 6050 50 0000 R CNN +F 2 "" H 24000 6000 29 0000 C CNN +F 3 "" H 23800 5900 60 0000 C CNN + 1 23800 5900 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q52 +U 1 1 63038157 +P 24650 6500 +F 0 "Q52" H 24550 6550 50 0000 R CNN +F 1 "eSim_PNP" H 24600 6650 50 0000 R CNN +F 2 "" H 24850 6600 29 0000 C CNN +F 3 "" H 24650 6500 60 0000 C CNN + 1 24650 6500 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q50 +U 1 1 63038158 +P 24250 6200 +F 0 "Q50" H 24150 6250 50 0000 R CNN +F 1 "eSim_NPN" H 24200 6350 50 0000 R CNN +F 2 "" H 24450 6300 29 0000 C CNN +F 3 "" H 24250 6200 60 0000 C CNN + 1 24250 6200 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q33 +U 1 1 63038159 +P 19850 1000 +F 0 "Q33" H 19750 1050 50 0000 R CNN +F 1 "eSim_NPN" H 19800 1150 50 0000 R CNN +F 2 "" H 20050 1100 29 0000 C CNN +F 3 "" H 19850 1000 60 0000 C CNN + 1 19850 1000 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q31 +U 1 1 6303815A +P 19700 1500 +F 0 "Q31" H 19600 1550 50 0000 R CNN +F 1 "eSim_NPN" H 19650 1650 50 0000 R CNN +F 2 "" H 19900 1600 29 0000 C CNN +F 3 "" H 19700 1500 60 0000 C CNN + 1 19700 1500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q24 +U 1 1 6303815B +P 18800 1000 +F 0 "Q24" H 18700 1050 50 0000 R CNN +F 1 "eSim_NPN" H 18750 1150 50 0000 R CNN +F 2 "" H 19000 1100 29 0000 C CNN +F 3 "" H 18800 1000 60 0000 C CNN + 1 18800 1000 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q27 +U 1 1 6303815C +P 18950 1500 +F 0 "Q27" H 18850 1550 50 0000 R CNN +F 1 "eSim_NPN" H 18900 1650 50 0000 R CNN +F 2 "" H 19150 1600 29 0000 C CNN +F 3 "" H 18950 1500 60 0000 C CNN + 1 18950 1500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q28 +U 1 1 6303815D +P 19100 2750 +F 0 "Q28" H 19000 2800 50 0000 R CNN +F 1 "eSim_PNP" H 19050 2900 50 0000 R CNN +F 2 "" H 19300 2850 29 0000 C CNN +F 3 "" H 19100 2750 60 0000 C CNN + 1 19100 2750 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q25 +U 1 1 6303815E +P 18800 3050 +F 0 "Q25" H 18700 3100 50 0000 R CNN +F 1 "eSim_PNP" H 18750 3200 50 0000 R CNN +F 2 "" H 19000 3150 29 0000 C CNN +F 3 "" H 18800 3050 60 0000 C CNN + 1 18800 3050 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q32 +U 1 1 6303815F +P 19700 2750 +F 0 "Q32" H 19600 2800 50 0000 R CNN +F 1 "eSim_PNP" H 19650 2900 50 0000 R CNN +F 2 "" H 19900 2850 29 0000 C CNN +F 3 "" H 19700 2750 60 0000 C CNN + 1 19700 2750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q34 +U 1 1 63038160 +P 20000 3000 +F 0 "Q34" H 19900 3050 50 0000 R CNN +F 1 "eSim_PNP" H 19950 3150 50 0000 R CNN +F 2 "" H 20200 3100 29 0000 C CNN +F 3 "" H 20000 3000 60 0000 C CNN + 1 20000 3000 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q29 +U 1 1 63038161 +P 19500 5100 +F 0 "Q29" H 19400 5150 50 0000 R CNN +F 1 "eSim_NPN" H 19450 5250 50 0000 R CNN +F 2 "" H 19700 5200 29 0000 C CNN +F 3 "" H 19500 5100 60 0000 C CNN + 1 19500 5100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q35 +U 1 1 63038162 +P 20000 5100 +F 0 "Q35" H 19900 5150 50 0000 R CNN +F 1 "eSim_NPN" H 19950 5250 50 0000 R CNN +F 2 "" H 20200 5200 29 0000 C CNN +F 3 "" H 20000 5100 60 0000 C CNN + 1 20000 5100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q30 +U 1 1 63038163 +P 19500 6200 +F 0 "Q30" H 19400 6250 50 0000 R CNN +F 1 "eSim_PNP" H 19450 6350 50 0000 R CNN +F 2 "" H 19700 6300 29 0000 C CNN +F 3 "" H 19500 6200 60 0000 C CNN + 1 19500 6200 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q36 +U 1 1 63038164 +P 20000 6200 +F 0 "Q36" H 19900 6250 50 0000 R CNN +F 1 "eSim_PNP" H 19950 6350 50 0000 R CNN +F 2 "" H 20200 6300 29 0000 C CNN +F 3 "" H 20000 6200 60 0000 C CNN + 1 20000 6200 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q22 +U 1 1 63038165 +P 18050 650 +F 0 "Q22" H 17950 700 50 0000 R CNN +F 1 "eSim_PNP" H 18000 800 50 0000 R CNN +F 2 "" H 18250 750 29 0000 C CNN +F 3 "" H 18050 650 60 0000 C CNN + 1 18050 650 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 63038166 +P 16700 800 +F 0 "Q14" H 16600 850 50 0000 R CNN +F 1 "eSim_PNP" H 16650 950 50 0000 R CNN +F 2 "" H 16900 900 29 0000 C CNN +F 3 "" H 16700 800 60 0000 C CNN + 1 16700 800 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 63038167 +P 17000 1200 +F 0 "Q15" H 16900 1250 50 0000 R CNN +F 1 "eSim_NPN" H 16950 1350 50 0000 R CNN +F 2 "" H 17200 1300 29 0000 C CNN +F 3 "" H 17000 1200 60 0000 C CNN + 1 17000 1200 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 63038168 +P 17000 1900 +F 0 "Q16" H 16900 1950 50 0000 R CNN +F 1 "eSim_NPN" H 16950 2050 50 0000 R CNN +F 2 "" H 17200 2000 29 0000 C CNN +F 3 "" H 17000 1900 60 0000 C CNN + 1 17000 1900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q8 +U 1 1 63038169 +P 16000 1100 +F 0 "Q8" H 15900 1150 50 0000 R CNN +F 1 "eSim_PNP" H 15950 1250 50 0000 R CNN +F 2 "" H 16200 1200 29 0000 C CNN +F 3 "" H 16000 1100 60 0000 C CNN + 1 16000 1100 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 6303816A +P 16300 1400 +F 0 "Q10" H 16200 1450 50 0000 R CNN +F 1 "eSim_NPN" H 16250 1550 50 0000 R CNN +F 2 "" H 16500 1500 29 0000 C CNN +F 3 "" H 16300 1400 60 0000 C CNN + 1 16300 1400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 6303816B +P 16300 1900 +F 0 "Q11" H 16200 1950 50 0000 R CNN +F 1 "eSim_NPN" H 16250 2050 50 0000 R CNN +F 2 "" H 16500 2000 29 0000 C CNN +F 3 "" H 16300 1900 60 0000 C CNN + 1 16300 1900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 6303816C +P 15650 500 +F 0 "Q4" H 15550 550 50 0000 R CNN +F 1 "eSim_NPN" H 15600 650 50 0000 R CNN +F 2 "" H 15850 600 29 0000 C CNN +F 3 "" H 15650 500 60 0000 C CNN + 1 15650 500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 6303816D +P 15550 1350 +F 0 "Q3" H 15450 1400 50 0000 R CNN +F 1 "eSim_NPN" H 15500 1500 50 0000 R CNN +F 2 "" H 15750 1450 29 0000 C CNN +F 3 "" H 15550 1350 60 0000 C CNN + 1 15550 1350 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 6303816E +P 15850 1900 +F 0 "Q6" H 15750 1950 50 0000 R CNN +F 1 "eSim_NPN" H 15800 2050 50 0000 R CNN +F 2 "" H 16050 2000 29 0000 C CNN +F 3 "" H 15850 1900 60 0000 C CNN + 1 15850 1900 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 6303816F +P 17000 2750 +F 0 "Q17" H 16900 2800 50 0000 R CNN +F 1 "eSim_NPN" H 16950 2900 50 0000 R CNN +F 2 "" H 17200 2850 29 0000 C CNN +F 3 "" H 17000 2750 60 0000 C CNN + 1 17000 2750 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 63038170 +P 17000 3400 +F 0 "Q18" H 16900 3450 50 0000 R CNN +F 1 "eSim_NPN" H 16950 3550 50 0000 R CNN +F 2 "" H 17200 3500 29 0000 C CNN +F 3 "" H 17000 3400 60 0000 C CNN + 1 17000 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 63038171 +P 16500 3400 +F 0 "Q12" H 16400 3450 50 0000 R CNN +F 1 "eSim_NPN" H 16450 3550 50 0000 R CNN +F 2 "" H 16700 3500 29 0000 C CNN +F 3 "" H 16500 3400 60 0000 C CNN + 1 16500 3400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 63038172 +P 15900 3100 +F 0 "Q7" H 15800 3150 50 0000 R CNN +F 1 "eSim_NPN" H 15850 3250 50 0000 R CNN +F 2 "" H 16100 3200 29 0000 C CNN +F 3 "" H 15900 3100 60 0000 C CNN + 1 15900 3100 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 63038173 +P 15250 3500 +F 0 "Q1" H 15150 3550 50 0000 R CNN +F 1 "eSim_NPN" H 15200 3650 50 0000 R CNN +F 2 "" H 15450 3600 29 0000 C CNN +F 3 "" H 15250 3500 60 0000 C CNN + 1 15250 3500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 63038174 +P 15650 4500 +F 0 "Q5" H 15550 4550 50 0000 R CNN +F 1 "eSim_NPN" H 15600 4650 50 0000 R CNN +F 2 "" H 15850 4600 29 0000 C CNN +F 3 "" H 15650 4500 60 0000 C CNN + 1 15650 4500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 63038175 +P 15250 5400 +F 0 "Q2" H 15150 5450 50 0000 R CNN +F 1 "eSim_NPN" H 15200 5550 50 0000 R CNN +F 2 "" H 15450 5500 29 0000 C CNN +F 3 "" H 15250 5400 60 0000 C CNN + 1 15250 5400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 6303817A +P 14650 3750 +F 0 "D1" H 14650 3850 50 0000 C CNN +F 1 "eSim_Diode" H 14650 3650 50 0000 C CNN +F 2 "" H 14650 3750 60 0000 C CNN +F 3 "" H 14650 3750 60 0000 C CNN + 1 14650 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 6303817B +P 14650 4200 +F 0 "D2" H 14650 4300 50 0000 C CNN +F 1 "eSim_Diode" H 14650 4100 50 0000 C CNN +F 2 "" H 14650 4200 60 0000 C CNN +F 3 "" H 14650 4200 60 0000 C CNN + 1 14650 4200 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 6303817C +P 14650 4600 +F 0 "D3" H 14650 4700 50 0000 C CNN +F 1 "eSim_Diode" H 14650 4500 50 0000 C CNN +F 2 "" H 14650 4600 60 0000 C CNN +F 3 "" H 14650 4600 60 0000 C CNN + 1 14650 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 6303817D +P 14650 5050 +F 0 "D4" H 14650 5150 50 0000 C CNN +F 1 "eSim_Diode" H 14650 4950 50 0000 C CNN +F 2 "" H 14650 5050 60 0000 C CNN +F 3 "" H 14650 5050 60 0000 C CNN + 1 14650 5050 + 0 1 1 0 +$EndComp +$Comp +L resistor R1 +U 1 1 6303817E +P 14600 3200 +F 0 "R1" H 14650 3330 50 0000 C CNN +F 1 "30k" H 14650 3150 50 0000 C CNN +F 2 "" H 14650 3180 30 0000 C CNN +F 3 "" V 14650 3250 30 0000 C CNN + 1 14600 3200 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 6303817F +P 15500 4950 +F 0 "R4" H 15550 5080 50 0000 C CNN +F 1 "270" H 15550 4900 50 0000 C CNN +F 2 "" H 15550 4930 30 0000 C CNN +F 3 "" V 15550 5000 30 0000 C CNN + 1 15500 4950 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 63038180 +P 15500 5700 +F 0 "R5" H 15550 5830 50 0000 C CNN +F 1 "2.7k" H 15550 5650 50 0000 C CNN +F 2 "" H 15550 5680 30 0000 C CNN +F 3 "" V 15550 5750 30 0000 C CNN + 1 15500 5700 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 63038181 +P 16700 5350 +F 0 "R10" H 16750 5480 50 0000 C CNN +F 1 "470" H 16750 5300 50 0000 C CNN +F 2 "" H 16750 5330 30 0000 C CNN +F 3 "" V 16750 5400 30 0000 C CNN + 1 16700 5350 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 63038182 +P 16800 4450 +F 0 "R11" H 16850 4580 50 0000 C CNN +F 1 "27k" H 16850 4400 50 0000 C CNN +F 2 "" H 16850 4430 30 0000 C CNN +F 3 "" V 16850 4500 30 0000 C CNN + 1 16800 4450 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q21 +U 1 1 63038183 +P 17700 5150 +F 0 "Q21" H 17600 5200 50 0000 R CNN +F 1 "eSim_NPN" H 17650 5300 50 0000 R CNN +F 2 "" H 17900 5250 29 0000 C CNN +F 3 "" H 17700 5150 60 0000 C CNN + 1 17700 5150 + -1 0 0 -1 +$EndComp +$Comp +L resistor R8 +U 1 1 63038184 +P 16400 4250 +F 0 "R8" H 16450 4380 50 0000 C CNN +F 1 "620" H 16450 4200 50 0000 C CNN +F 2 "" H 16450 4230 30 0000 C CNN +F 3 "" V 16450 4300 30 0000 C CNN + 1 16400 4250 + 0 1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 63038185 +P 17200 4250 +F 0 "R13" H 17250 4380 50 0000 C CNN +F 1 "1.8k" H 17250 4200 50 0000 C CNN +F 2 "" H 17250 4230 30 0000 C CNN +F 3 "" V 17250 4300 30 0000 C CNN + 1 17200 4250 + 0 1 1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 63038186 +P 16550 3750 +F 0 "R9" H 16600 3880 50 0000 C CNN +F 1 "100" H 16600 3700 50 0000 C CNN +F 2 "" H 16600 3730 30 0000 C CNN +F 3 "" V 16600 3800 30 0000 C CNN + 1 16550 3750 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 63038187 +P 15750 3500 +F 0 "R7" H 15800 3630 50 0000 C CNN +F 1 "100" H 15800 3450 50 0000 C CNN +F 2 "" H 15800 3480 30 0000 C CNN +F 3 "" V 15800 3550 30 0000 C CNN + 1 15750 3500 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 63038188 +P 17050 3750 +F 0 "R12" H 17100 3880 50 0000 C CNN +F 1 "100" H 17100 3700 50 0000 C CNN +F 2 "" H 17100 3730 30 0000 C CNN +F 3 "" V 17100 3800 30 0000 C CNN + 1 17050 3750 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q26 +U 1 1 63038189 +P 18850 5300 +F 0 "Q26" H 18750 5350 50 0000 R CNN +F 1 "eSim_NPN" H 18800 5450 50 0000 R CNN +F 2 "" H 19050 5400 29 0000 C CNN +F 3 "" H 18850 5300 60 0000 C CNN + 1 18850 5300 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q23 +U 1 1 6303818A +P 18400 4700 +F 0 "Q23" H 18300 4750 50 0000 R CNN +F 1 "eSim_NPN" H 18350 4850 50 0000 R CNN +F 2 "" H 18600 4800 29 0000 C CNN +F 3 "" H 18400 4700 60 0000 C CNN + 1 18400 4700 + 1 0 0 -1 +$EndComp +$Comp +L resistor R16 +U 1 1 6303818B +P 18450 5650 +F 0 "R16" H 18500 5780 50 0000 C CNN +F 1 "27k" H 18500 5600 50 0000 C CNN +F 2 "" H 18500 5630 30 0000 C CNN +F 3 "" V 18500 5700 30 0000 C CNN + 1 18450 5650 + 0 1 1 0 +$EndComp +$Comp +L resistor R18 +U 1 1 6303818C +P 18900 6250 +F 0 "R18" H 18950 6380 50 0000 C CNN +F 1 "27k" H 18950 6200 50 0000 C CNN +F 2 "" H 18950 6230 30 0000 C CNN +F 3 "" V 18950 6300 30 0000 C CNN + 1 18900 6250 + 0 1 1 0 +$EndComp +$Comp +L resistor R20 +U 1 1 6303818D +P 19350 4450 +F 0 "R20" H 19400 4580 50 0000 C CNN +F 1 "27k" H 19400 4400 50 0000 C CNN +F 2 "" H 19400 4430 30 0000 C CNN +F 3 "" V 19400 4500 30 0000 C CNN + 1 19350 4450 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 6303818E +P 17750 5750 +F 0 "R14" H 17800 5880 50 0000 C CNN +F 1 "4.7k" H 17800 5700 50 0000 C CNN +F 2 "" H 17800 5730 30 0000 C CNN +F 3 "" V 17800 5800 30 0000 C CNN + 1 17750 5750 + -1 0 0 1 +$EndComp +$Comp +L resistor R15 +U 1 1 6303818F +P 18000 5450 +F 0 "R15" H 18050 5580 50 0000 C CNN +F 1 "4.7k" H 18050 5400 50 0000 C CNN +F 2 "" H 18050 5430 30 0000 C CNN +F 3 "" V 18050 5500 30 0000 C CNN + 1 18000 5450 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R6 +U 1 1 63038190 +P 15700 2300 +F 0 "R6" H 15750 2430 50 0000 C CNN +F 1 "40k" H 15750 2250 50 0000 C CNN +F 2 "" H 15750 2280 30 0000 C CNN +F 3 "" V 15750 2350 30 0000 C CNN + 1 15700 2300 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 63038191 +P 14950 650 +F 0 "R2" H 15000 780 50 0000 C CNN +F 1 "11k" H 15000 600 50 0000 C CNN +F 2 "" H 15000 630 30 0000 C CNN +F 3 "" V 15000 700 30 0000 C CNN + 1 14950 650 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 63038192 +P 14950 1550 +F 0 "R3" H 15000 1680 50 0000 C CNN +F 1 "39k" H 15000 1500 50 0000 C CNN +F 2 "" H 15000 1530 30 0000 C CNN +F 3 "" V 15000 1600 30 0000 C CNN + 1 14950 1550 + 0 1 1 0 +$EndComp +$Comp +L resistor R17 +U 1 1 63038193 +P 18850 400 +F 0 "R17" H 18900 530 50 0000 C CNN +F 1 "4k" H 18900 350 50 0000 C CNN +F 2 "" H 18900 380 30 0000 C CNN +F 3 "" V 18900 450 30 0000 C CNN + 1 18850 400 + 0 1 1 0 +$EndComp +$Comp +L resistor R22 +U 1 1 63038194 +P 20150 550 +F 0 "R22" H 20200 680 50 0000 C CNN +F 1 "5k" H 20200 500 50 0000 C CNN +F 2 "" H 20200 530 30 0000 C CNN +F 3 "" V 20200 600 30 0000 C CNN + 1 20150 550 + 0 1 1 0 +$EndComp +$Comp +L resistor R23 +U 1 1 63038195 +P 20150 1750 +F 0 "R23" H 20200 1880 50 0000 C CNN +F 1 "5k" H 20200 1700 50 0000 C CNN +F 2 "" H 20200 1730 30 0000 C CNN +F 3 "" V 20200 1800 30 0000 C CNN + 1 20150 1750 + 0 1 1 0 +$EndComp +$Comp +L resistor R24 +U 1 1 63038196 +P 20150 3400 +F 0 "R24" H 20200 3530 50 0000 C CNN +F 1 "5k" H 20200 3350 50 0000 C CNN +F 2 "" H 20200 3380 30 0000 C CNN +F 3 "" V 20200 3450 30 0000 C CNN + 1 20150 3400 + 0 1 1 0 +$EndComp +$Comp +L resistor R19 +U 1 1 63038197 +P 19000 2200 +F 0 "R19" H 19050 2330 50 0000 C CNN +F 1 "15k" H 19050 2150 50 0000 C CNN +F 2 "" H 19050 2180 30 0000 C CNN +F 3 "" V 19050 2250 30 0000 C CNN + 1 19000 2200 + -1 0 0 1 +$EndComp +$Comp +L resistor R21 +U 1 1 63038198 +P 19700 2050 +F 0 "R21" H 19750 2180 50 0000 C CNN +F 1 "10k" H 19750 2000 50 0000 C CNN +F 2 "" H 19750 2030 30 0000 C CNN +F 3 "" V 19750 2100 30 0000 C CNN + 1 19700 2050 + -1 0 0 1 +$EndComp +$Comp +L resistor R26 +U 1 1 63038199 +P 21250 1450 +F 0 "R26" H 21300 1580 50 0000 C CNN +F 1 "800" H 21300 1400 50 0000 C CNN +F 2 "" H 21300 1430 30 0000 C CNN +F 3 "" V 21300 1500 30 0000 C CNN + 1 21250 1450 + -1 0 0 1 +$EndComp +$Comp +L resistor R27 +U 1 1 6303819A +P 21250 2200 +F 0 "R27" H 21300 2330 50 0000 C CNN +F 1 "2.7k" H 21300 2150 50 0000 C CNN +F 2 "" H 21300 2180 30 0000 C CNN +F 3 "" V 21300 2250 30 0000 C CNN + 1 21250 2200 + -1 0 0 1 +$EndComp +$Comp +L resistor R28 +U 1 1 6303819B +P 21250 2950 +F 0 "R28" H 21300 3080 50 0000 C CNN +F 1 "10k" H 21300 2900 50 0000 C CNN +F 2 "" H 21300 2930 30 0000 C CNN +F 3 "" V 21300 3000 30 0000 C CNN + 1 21250 2950 + -1 0 0 1 +$EndComp +$Comp +L resistor R31 +U 1 1 6303819C +P 21400 5850 +F 0 "R31" H 21450 5980 50 0000 C CNN +F 1 "800" H 21450 5800 50 0000 C CNN +F 2 "" H 21450 5830 30 0000 C CNN +F 3 "" V 21450 5900 30 0000 C CNN + 1 21400 5850 + -1 0 0 -1 +$EndComp +$Comp +L resistor R30 +U 1 1 6303819D +P 21400 5450 +F 0 "R30" H 21450 5580 50 0000 C CNN +F 1 "2.7k" H 21450 5400 50 0000 C CNN +F 2 "" H 21450 5430 30 0000 C CNN +F 3 "" V 21450 5500 30 0000 C CNN + 1 21400 5450 + -1 0 0 -1 +$EndComp +$Comp +L resistor R29 +U 1 1 6303819E +P 21400 4850 +F 0 "R29" H 21450 4980 50 0000 C CNN +F 1 "10k" H 21450 4800 50 0000 C CNN +F 2 "" H 21450 4830 30 0000 C CNN +F 3 "" V 21450 4900 30 0000 C CNN + 1 21400 4850 + -1 0 0 -1 +$EndComp +$Comp +L resistor R35 +U 1 1 6303819F +P 22850 4200 +F 0 "R35" H 22900 4330 50 0000 C CNN +F 1 "33k" H 22900 4150 50 0000 C CNN +F 2 "" H 22900 4180 30 0000 C CNN +F 3 "" V 22900 4250 30 0000 C CNN + 1 22850 4200 + 0 1 1 0 +$EndComp +$Comp +L resistor R37 +U 1 1 630381A0 +P 23650 4200 +F 0 "R37" H 23700 4330 50 0000 C CNN +F 1 "33k" H 23700 4150 50 0000 C CNN +F 2 "" H 23700 4180 30 0000 C CNN +F 3 "" V 23700 4250 30 0000 C CNN + 1 23650 4200 + 0 1 1 0 +$EndComp +$Comp +L resistor R39 +U 1 1 630381A1 +P 24500 4200 +F 0 "R39" H 24550 4330 50 0000 C CNN +F 1 "33k" H 24550 4150 50 0000 C CNN +F 2 "" H 24550 4180 30 0000 C CNN +F 3 "" V 24550 4250 30 0000 C CNN + 1 24500 4200 + 0 1 1 0 +$EndComp +$Comp +L resistor R32 +U 1 1 630381A2 +P 21850 3450 +F 0 "R32" H 21900 3580 50 0000 C CNN +F 1 "33k" H 21900 3400 50 0000 C CNN +F 2 "" H 21900 3430 30 0000 C CNN +F 3 "" V 21900 3500 30 0000 C CNN + 1 21850 3450 + 0 1 1 0 +$EndComp +$Comp +L resistor R34 +U 1 1 630381A3 +P 22650 3450 +F 0 "R34" H 22700 3580 50 0000 C CNN +F 1 "33k" H 22700 3400 50 0000 C CNN +F 2 "" H 22700 3430 30 0000 C CNN +F 3 "" V 22700 3500 30 0000 C CNN + 1 22650 3450 + 0 1 1 0 +$EndComp +$Comp +L resistor R36 +U 1 1 630381A4 +P 23550 3450 +F 0 "R36" H 23600 3580 50 0000 C CNN +F 1 "33k" H 23600 3400 50 0000 C CNN +F 2 "" H 23600 3430 30 0000 C CNN +F 3 "" V 23600 3500 30 0000 C CNN + 1 23550 3450 + 0 1 1 0 +$EndComp +$Comp +L resistor R38 +U 1 1 630381A5 +P 24350 3450 +F 0 "R38" H 24400 3580 50 0000 C CNN +F 1 "33k" H 24400 3400 50 0000 C CNN +F 2 "" H 24400 3430 30 0000 C CNN +F 3 "" V 24400 3500 30 0000 C CNN + 1 24350 3450 + 0 1 1 0 +$EndComp +$Comp +L resistor R44 +U 1 1 630381A6 +P 25000 3800 +F 0 "R44" H 25050 3930 50 0000 C CNN +F 1 "1600" H 25050 3750 50 0000 C CNN +F 2 "" H 25050 3780 30 0000 C CNN +F 3 "" V 25050 3850 30 0000 C CNN + 1 25000 3800 + 0 1 1 0 +$EndComp +$Comp +L resistor R45 +U 1 1 630381A7 +P 25000 4950 +F 0 "R45" H 25050 5080 50 0000 C CNN +F 1 "330" H 25050 4900 50 0000 C CNN +F 2 "" H 25050 4930 30 0000 C CNN +F 3 "" V 25050 5000 30 0000 C CNN + 1 25000 4950 + 0 1 1 0 +$EndComp +$Comp +L resistor R46 +U 1 1 630381A8 +P 25000 5550 +F 0 "R46" H 25050 5680 50 0000 C CNN +F 1 "375" H 25050 5500 50 0000 C CNN +F 2 "" H 25050 5530 30 0000 C CNN +F 3 "" V 25050 5600 30 0000 C CNN + 1 25000 5550 + 0 1 1 0 +$EndComp +$Comp +L resistor R47 +U 1 1 630381A9 +P 25000 6150 +F 0 "R47" H 25050 6280 50 0000 C CNN +F 1 "200" H 25050 6100 50 0000 C CNN +F 2 "" H 25050 6130 30 0000 C CNN +F 3 "" V 25050 6200 30 0000 C CNN + 1 25000 6150 + 0 1 1 0 +$EndComp +$Comp +L resistor R48 +U 1 1 630381AA +P 25000 6750 +F 0 "R48" H 25050 6880 50 0000 C CNN +F 1 "5.6k" H 25050 6700 50 0000 C CNN +F 2 "" H 25050 6730 30 0000 C CNN +F 3 "" V 25050 6800 30 0000 C CNN + 1 25000 6750 + 0 1 1 0 +$EndComp +$Comp +L resistor R43 +U 1 1 630381AB +P 25000 2450 +F 0 "R43" H 25050 2580 50 0000 C CNN +F 1 "330" H 25050 2400 50 0000 C CNN +F 2 "" H 25050 2430 30 0000 C CNN +F 3 "" V 25050 2500 30 0000 C CNN + 1 25000 2450 + 0 1 1 0 +$EndComp +$Comp +L resistor R42 +U 1 1 630381AC +P 25000 1700 +F 0 "R42" H 25050 1830 50 0000 C CNN +F 1 "375" H 25050 1650 50 0000 C CNN +F 2 "" H 25050 1680 30 0000 C CNN +F 3 "" V 25050 1750 30 0000 C CNN + 1 25000 1700 + 0 1 1 0 +$EndComp +$Comp +L resistor R41 +U 1 1 630381AD +P 25000 1000 +F 0 "R41" H 25050 1130 50 0000 C CNN +F 1 "200" H 25050 950 50 0000 C CNN +F 2 "" H 25050 980 30 0000 C CNN +F 3 "" V 25050 1050 30 0000 C CNN + 1 25000 1000 + 0 1 1 0 +$EndComp +$Comp +L resistor R40 +U 1 1 630381AE +P 25000 400 +F 0 "R40" H 25050 530 50 0000 C CNN +F 1 "5.2k" H 25050 350 50 0000 C CNN +F 2 "" H 25050 380 30 0000 C CNN +F 3 "" V 25050 450 30 0000 C CNN + 1 25000 400 + 0 1 1 0 +$EndComp +$Comp +L resistor R25 +U 1 1 630381AF +P 20650 5750 +F 0 "R25" H 20700 5880 50 0000 C CNN +F 1 "1k" H 20700 5700 50 0000 C CNN +F 2 "" H 20700 5730 30 0000 C CNN +F 3 "" V 20700 5800 30 0000 C CNN + 1 20650 5750 + 1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 11 1 630381B0 +P 25600 700 +F 0 "U1" H 25650 800 30 0000 C CNN +F 1 "PORT" H 25600 700 30 0000 C CNN +F 2 "" H 25600 700 60 0000 C CNN +F 3 "" H 25600 700 60 0000 C CNN + 11 25600 700 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 630381B1 +P 20450 6250 +F 0 "U1" H 20500 6350 30 0000 C CNN +F 1 "PORT" H 20450 6250 30 0000 C CNN +F 2 "" H 20450 6250 60 0000 C CNN +F 3 "" H 20450 6250 60 0000 C CNN + 8 20450 6250 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 5 1 630381B2 +P 17550 50 +F 0 "U1" H 17600 150 30 0000 C CNN +F 1 "PORT" H 17550 50 30 0000 C CNN +F 2 "" H 17550 50 60 0000 C CNN +F 3 "" H 17550 50 60 0000 C CNN + 5 17550 50 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 4 1 630381B3 +P 16850 50 +F 0 "U1" H 16900 150 30 0000 C CNN +F 1 "PORT" H 16850 50 30 0000 C CNN +F 2 "" H 16850 50 60 0000 C CNN +F 3 "" H 16850 50 60 0000 C CNN + 4 16850 50 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 10 1 630381B4 +P 25600 250 +F 0 "U1" H 25650 350 30 0000 C CNN +F 1 "PORT" H 25600 250 30 0000 C CNN +F 2 "" H 25600 250 60 0000 C CNN +F 3 "" H 25600 250 60 0000 C CNN + 10 25600 250 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 2 1 630381B5 +P 15350 0 +F 0 "U1" H 15400 100 30 0000 C CNN +F 1 "PORT" H 15350 0 30 0000 C CNN +F 2 "" H 15350 0 60 0000 C CNN +F 3 "" H 15350 0 60 0000 C CNN + 2 15350 0 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 3 1 630381B6 +P 15850 100 +F 0 "U1" H 15900 200 30 0000 C CNN +F 1 "PORT" H 15850 100 30 0000 C CNN +F 2 "" H 15850 100 60 0000 C CNN +F 3 "" H 15850 100 60 0000 C CNN + 3 15850 100 + -1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 6 1 630381B7 +P 17550 1350 +F 0 "U1" H 17600 1450 30 0000 C CNN +F 1 "PORT" H 17550 1350 30 0000 C CNN +F 2 "" H 17550 1350 60 0000 C CNN +F 3 "" H 17550 1350 60 0000 C CNN + 6 17550 1350 + 0 -1 1 0 +$EndComp +$Comp +L PORT U1 +U 1 1 630381B8 +P 14150 4850 +F 0 "U1" H 14200 4950 30 0000 C CNN +F 1 "PORT" H 14150 4850 30 0000 C CNN +F 2 "" H 14150 4850 60 0000 C CNN +F 3 "" H 14150 4850 60 0000 C CNN + 1 14150 4850 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 12 1 630381B9 +P 25600 6500 +F 0 "U1" H 25650 6600 30 0000 C CNN +F 1 "PORT" H 25600 6500 30 0000 C CNN +F 2 "" H 25600 6500 60 0000 C CNN +F 3 "" H 25600 6500 60 0000 C CNN + 12 25600 6500 + -1 0 0 -1 +$EndComp +$Comp +L resistor R33 +U 1 1 630381BA +P 22000 4200 +F 0 "R33" H 22050 4330 50 0000 C CNN +F 1 "33k" H 22050 4150 50 0000 C CNN +F 2 "" H 22050 4180 30 0000 C CNN +F 3 "" V 22050 4250 30 0000 C CNN + 1 22000 4200 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 9 1 630381BB +P 20950 7100 +F 0 "U1" H 21000 7200 30 0000 C CNN +F 1 "PORT" H 20950 7100 30 0000 C CNN +F 2 "" H 20950 7100 60 0000 C CNN +F 3 "" H 20950 7100 60 0000 C CNN + 9 20950 7100 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 630381BC +P 20100 7150 +F 0 "U1" H 20150 7250 30 0000 C CNN +F 1 "PORT" H 20100 7150 30 0000 C CNN +F 2 "" H 20100 7150 60 0000 C CNN +F 3 "" H 20100 7150 60 0000 C CNN + 7 20100 7150 + 0 -1 -1 0 +$EndComp +NoConn ~ 25700 4350 +NoConn ~ 25700 4600 +$Comp +L PORT U1 +U 13 1 630381BD +P 26200 4350 +F 0 "U1" H 26250 4450 30 0000 C CNN +F 1 "PORT" H 26200 4350 30 0000 C CNN +F 2 "" H 26200 4350 60 0000 C CNN +F 3 "" H 26200 4350 60 0000 C CNN + 13 26200 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 14 1 630381BE +P 26200 4600 +F 0 "U1" H 26250 4700 30 0000 C CNN +F 1 "PORT" H 26200 4600 30 0000 C CNN +F 2 "" H 26200 4600 60 0000 C CNN +F 3 "" H 26200 4600 60 0000 C CNN + 14 26200 4600 + -1 0 0 1 +$EndComp +Wire Wire Line + 15550 5150 15550 5600 +Wire Wire Line + 15450 5400 15550 5400 +Wire Wire Line + 15850 4500 16600 4500 +Connection ~ 15550 5400 +Wire Wire Line + 14650 3400 14650 3600 +Wire Wire Line + 14650 3900 14650 4050 +Wire Wire Line + 14650 4350 14650 4450 +Wire Wire Line + 14650 4750 14650 4900 +Wire Wire Line + 14650 3100 14650 3000 +Wire Wire Line + 14650 3500 15050 3500 +Connection ~ 14650 3500 +Wire Wire Line + 15550 3000 15550 4300 +Wire Wire Line + 15550 4700 15550 4850 +Wire Wire Line + 15350 3700 15350 4150 +Wire Wire Line + 15350 4150 17250 4150 +Connection ~ 16450 4150 +Wire Wire Line + 16450 4450 16450 4800 +Connection ~ 16450 4500 +Wire Wire Line + 16900 4500 16950 4500 +Wire Wire Line + 16950 4500 16950 5600 +Connection ~ 16950 5000 +Wire Wire Line + 16750 5850 16750 5550 +Wire Wire Line + 16750 4700 16750 5250 +Wire Wire Line + 16750 4700 17600 4700 +Wire Wire Line + 17250 4450 17250 4850 +Connection ~ 17250 4700 +Wire Wire Line + 17600 4700 17600 4950 +Wire Wire Line + 15800 3300 15800 3400 +Wire Wire Line + 16600 3600 16600 3650 +Wire Wire Line + 17100 3600 17100 3650 +Wire Wire Line + 16100 3100 17100 3100 +Wire Wire Line + 17100 2950 17100 3200 +Wire Wire Line + 16600 3200 16600 3100 +Connection ~ 16600 3100 +Wire Wire Line + 16300 3400 16300 3100 +Connection ~ 16300 3100 +Wire Wire Line + 16800 3400 16800 3100 +Connection ~ 16800 3100 +Connection ~ 17100 3100 +Wire Wire Line + 15800 2750 16800 2750 +Wire Wire Line + 16100 2750 16100 5750 +Connection ~ 16100 2750 +Wire Wire Line + 17100 2100 17100 2550 +Wire Wire Line + 17100 1400 17100 1700 +Wire Wire Line + 16800 1900 16800 1650 +Wire Wire Line + 16800 1650 17800 1650 +Connection ~ 17100 1650 +Wire Wire Line + 18950 5500 18950 6150 +Wire Wire Line + 18500 4900 18500 5550 +Wire Wire Line + 18500 5850 18500 6050 +Wire Wire Line + 18500 6050 18950 6050 +Connection ~ 18950 6050 +Wire Wire Line + 19400 5300 19400 6000 +Wire Wire Line + 19700 5100 19800 5100 +Wire Wire Line + 19400 4650 19400 4900 +Wire Wire Line + 19400 6650 19400 6400 +Wire Wire Line + 20100 6400 20100 6900 +Wire Wire Line + 14650 5200 14650 6650 +Wire Wire Line + 14650 6650 22050 6650 +Connection ~ 16100 6650 +Wire Wire Line + 15550 5900 15550 6650 +Connection ~ 15550 6650 +Wire Wire Line + 15150 5600 15150 6650 +Connection ~ 15150 6650 +Wire Wire Line + 17950 850 17950 5250 +Wire Wire Line + 17950 5550 17950 6650 +Connection ~ 17950 5800 +Wire Wire Line + 17600 5350 17600 6650 +Connection ~ 17600 6650 +Wire Wire Line + 17250 5350 17250 6650 +Connection ~ 17250 6650 +Wire Wire Line + 16450 5450 16450 6650 +Connection ~ 16450 6650 +Wire Wire Line + 17450 5800 17450 3300 +Wire Wire Line + 17250 5800 17550 5800 +Wire Wire Line + 17450 3300 19200 3300 +Wire Wire Line + 16400 2100 16400 2750 +Wire Wire Line + 15750 2650 16400 2650 +Wire Wire Line + 15750 2100 15750 2200 +Wire Wire Line + 15750 2500 15750 2650 +Wire Wire Line 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Wire Line + 18900 2850 18900 2750 +Wire Wire Line + 18900 3300 18900 3250 +Connection ~ 18900 3300 +Connection ~ 20200 3000 +Wire Wire Line + 19200 2550 19600 2550 +Wire Wire Line + 18500 2250 18800 2250 +Wire Wire Line + 19100 2250 19400 2250 +Wire Wire Line + 19400 2250 19400 2550 +Connection ~ 19400 2550 +Wire Wire Line + 19900 3950 19900 3200 +Wire Wire Line + 19600 3950 19600 2950 +Wire Wire Line + 19400 4350 19400 4250 +Wire Wire Line + 20100 5800 20550 5800 +Wire Wire Line + 20450 5800 20450 6000 +Connection ~ 20100 5800 +Connection ~ 20450 5800 +Wire Wire Line + 20100 5300 20100 6000 +Wire Wire Line + 19700 6200 19800 6200 +Wire Wire Line + 18950 5700 19750 5700 +Wire Wire Line + 19750 5700 19750 6200 +Connection ~ 19750 6200 +Connection ~ 18950 5700 +Wire Wire Line + 18500 4500 18500 4250 +Wire Wire Line + 17800 4700 18200 4700 +Wire Wire Line + 18650 5300 18500 5300 +Connection ~ 18500 5300 +Wire Wire Line + 18950 6650 18950 6450 +Wire Wire Line + 19350 2100 19500 2100 +Wire Wire Line + 16800 600 16800 450 +Connection ~ 17100 450 +Wire Wire Line + 16800 450 17100 450 +Wire Wire Line + 16400 900 16100 900 +Connection ~ 16400 900 +Wire Wire Line + 15750 800 16500 800 +Connection ~ 15750 800 +Wire Wire Line + 15450 1700 15450 1550 +Wire Wire Line + 15750 1350 15750 1350 +Connection ~ 15750 1350 +Wire Wire Line + 15800 3700 15800 3950 +Wire Wire Line + 20200 3950 15800 3950 +Connection ~ 16600 3950 +Connection ~ 17100 3950 +Wire Wire Line + 15800 2900 15800 2750 +Connection ~ 16400 2750 +Connection ~ 16400 2650 +Wire Wire Line + 14650 3000 15550 3000 +Wire Wire Line + 15350 3300 15350 3000 +Connection ~ 15350 3000 +Connection ~ 19400 6650 +Connection ~ 20100 6650 +Wire Wire Line + 16400 50 16400 1200 +Wire Wire Line + 16950 6000 16950 6650 +Connection ~ 16950 6650 +Connection ~ 17450 5800 +Wire Wire Line + 15150 4850 15150 5200 +Wire Wire Line + 17950 5800 17850 5800 +Connection ~ 18950 6650 +Connection ~ 17950 6650 +Wire Wire Line + 25700 4350 25950 4350 +Wire Wire Line + 25700 4600 25950 4600 +Wire Wire Line + 24000 3750 24000 1250 +Connection ~ 24000 3750 +Wire Wire Line + 20200 3600 20200 3950 +Connection ~ 19900 3950 +Connection ~ 19600 3950 +Wire Wire Line + 18150 3950 18150 6650 +Connection ~ 18150 6650 +Connection ~ 18150 3950 +Connection ~ 20200 3750 +Connection ~ 21450 3750 +Wire Wire Line + 20200 3750 24400 3750 +Wire Wire Line + 22050 7050 25050 7050 +Connection ~ 22050 6650 +Wire Wire Line + 16100 6150 16100 6650 +Wire Wire Line + 20600 2100 20600 3750 +Connection ~ 20600 3750 +$Comp +L eSim_NPN Q9 +U 1 1 631A711B +P 16200 5950 +F 0 "Q9" H 16100 6000 50 0000 R CNN +F 1 "eSim_NPN" H 16150 6100 50 0000 R CNN +F 2 "" H 16400 6050 29 0000 C CNN +F 3 "" H 16200 5950 60 0000 C CNN + 1 16200 5950 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 631A7121 +P 16350 5700 +F 0 "D5" H 16350 5800 50 0000 C CNN +F 1 "eSim_Diode" H 16350 5600 50 0000 C CNN +F 2 "" H 16350 5700 60 0000 C CNN +F 3 "" H 16350 5700 60 0000 C CNN + 1 16350 5700 + -1 0 0 1 +$EndComp +Wire Wire Line + 16100 5700 16200 5700 +Wire Wire Line + 16500 5700 16500 5950 +Wire Wire Line + 16500 5950 16400 5950 +Connection ~ 16500 5850 +Connection ~ 16100 5700 +$Comp +L eSim_Diode D9 +U 1 1 631A81FB +P 17850 4900 +F 0 "D9" H 17850 5000 50 0000 C CNN +F 1 "eSim_Diode" H 17850 4800 50 0000 C CNN +F 2 "" H 17850 4900 60 0000 C CNN +F 3 "" H 17850 4900 60 0000 C CNN + 1 17850 4900 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 631AA096 +P 17050 5800 +F 0 "Q19" H 16950 5850 50 0000 R CNN +F 1 "eSim_NPN" H 17000 5950 50 0000 R CNN +F 2 "" H 17250 5900 29 0000 C CNN +F 3 "" H 17050 5800 60 0000 C CNN + 1 17050 5800 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D8 +U 1 1 631AA09C +P 17200 5550 +F 0 "D8" H 17200 5650 50 0000 C CNN +F 1 "eSim_Diode" H 17200 5450 50 0000 C CNN +F 2 "" H 17200 5550 60 0000 C CNN +F 3 "" H 17200 5550 60 0000 C CNN + 1 17200 5550 + -1 0 0 1 +$EndComp +Wire Wire Line + 16950 5550 17050 5550 +Wire Wire Line + 17350 5550 17350 5800 +Connection ~ 16950 5550 +Connection ~ 17350 5800 +$Comp +L eSim_NPN Q13 +U 1 1 631AFC74 +P 16400 5150 +F 0 "Q13" H 16300 5200 50 0000 R CNN +F 1 "eSim_NPN" H 16350 5300 50 0000 R CNN +F 2 "" H 16600 5250 29 0000 C CNN +F 3 "" H 16400 5150 60 0000 C CNN + 1 16400 5150 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 631AFC7A +P 16550 4900 +F 0 "D6" H 16550 5000 50 0000 C CNN +F 1 "eSim_Diode" H 16550 4800 50 0000 C CNN +F 2 "" H 16550 4900 60 0000 C CNN +F 3 "" H 16550 4900 60 0000 C CNN + 1 16550 4900 + -1 0 0 1 +$EndComp +Wire Wire Line + 16300 4900 16400 4900 +Wire Wire Line + 16300 4900 16300 4950 +Wire Wire Line + 16700 5150 16600 5150 +Wire Wire Line + 16700 4900 16700 5150 +Wire Wire Line + 16300 5350 16300 5450 +Wire Wire Line + 16300 5450 16450 5450 +Wire Wire Line + 16750 5050 16700 5050 +Connection ~ 16700 5050 +Connection ~ 16750 5050 +Wire Wire Line + 16450 4800 16350 4800 +Wire Wire Line + 16350 4800 16350 4900 +Connection ~ 16350 4900 +$Comp +L eSim_NPN Q20 +U 1 1 631B21DC +P 17300 5150 +F 0 "Q20" H 17200 5200 50 0000 R CNN +F 1 "eSim_NPN" H 17250 5300 50 0000 R CNN +F 2 "" H 17500 5250 29 0000 C CNN +F 3 "" H 17300 5150 60 0000 C CNN + 1 17300 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 631B21E2 +P 17150 4900 +F 0 "D7" H 17150 5000 50 0000 C CNN +F 1 "eSim_Diode" H 17150 4800 50 0000 C CNN +F 2 "" H 17150 4900 60 0000 C CNN +F 3 "" H 17150 4900 60 0000 C CNN + 1 17150 4900 + 1 0 0 1 +$EndComp +Wire Wire Line + 17300 4900 17400 4900 +Wire Wire Line + 17000 5150 17100 5150 +Wire Wire Line + 17000 4900 17000 5150 +Wire Wire Line + 17400 4900 17400 4950 +Wire Wire Line + 17250 4850 17350 4850 +Wire Wire Line + 17350 4850 17350 4900 +Connection ~ 17350 4900 +Wire Wire Line + 17000 5000 16950 5000 +Connection ~ 17000 5000 +Wire Wire Line + 17400 5350 17250 5350 +Wire Wire Line + 17700 4900 17600 4900 +Connection ~ 17600 4900 +Wire Wire Line + 18000 4900 18000 5150 +Wire Wire Line + 18000 5150 17900 5150 +Wire Wire Line + 18000 5050 18050 5050 +Wire Wire Line + 18050 5050 18050 5200 +Wire Wire Line + 18050 5200 17950 5200 +Connection ~ 17950 5200 +Connection ~ 18000 5050 +Wire Wire Line + 16750 5850 16500 5850 +$EndSCHEMATC diff --git a/Failed_subcircuits/ICL8038/ICL8038.sub b/Failed_subcircuits/ICL8038/ICL8038.sub new file mode 100644 index 000000000..ab250d921 --- /dev/null +++ b/Failed_subcircuits/ICL8038/ICL8038.sub @@ -0,0 +1,119 @@ +* Subcircuit ICL8038 +.subckt ICL8038 net-_q2-pad1_ net-_r2-pad2_ net-_q3-pad3_ net-_q10-pad1_ net-_q10-pad1_ net-_q16-pad3_ net-_d4-pad2_ net-_q35-pad3_ net-_q49-pad3_ net-_q10-pad1_ net-_q51-pad2_ net-_q52-pad2_ ? ? +* c:\fossee\esim\library\subcircuitlibrary\icl8038\icl8038.cir +.include CBAT54_Schottky.lib +.include PNP.lib +.include D.lib +.include NPN.lib +q51 net-_q10-pad1_ net-_q51-pad2_ net-_q49-pad2_ Q2N2222 +q49 net-_d4-pad2_ net-_q49-pad2_ net-_q49-pad3_ Q2N2907A +q47 net-_q10-pad1_ net-_q47-pad2_ net-_q45-pad2_ Q2N2222 +q45 net-_d4-pad2_ net-_q45-pad2_ net-_q45-pad3_ Q2N2907A +q43 net-_q10-pad1_ net-_q43-pad2_ net-_q41-pad2_ Q2N2222 +q41 net-_d4-pad2_ net-_q41-pad2_ net-_q41-pad3_ Q2N2907A +q39 net-_q10-pad1_ net-_q39-pad2_ net-_q37-pad2_ Q2N2222 +q37 net-_d4-pad2_ net-_q37-pad2_ net-_q37-pad3_ Q2N2907A +q38 net-_q10-pad1_ net-_q38-pad2_ net-_q38-pad3_ Q2N2222 +q40 net-_d4-pad2_ net-_q40-pad2_ net-_q38-pad2_ Q2N2907A +q44 net-_d4-pad2_ net-_q44-pad2_ net-_q42-pad2_ Q2N2907A +q42 net-_q10-pad1_ net-_q42-pad2_ net-_q42-pad3_ Q2N2222 +q46 net-_q10-pad1_ net-_q46-pad2_ net-_q46-pad3_ Q2N2222 +q48 net-_d4-pad2_ net-_q48-pad2_ net-_q46-pad2_ Q2N2907A +q52 net-_d4-pad2_ net-_q52-pad2_ net-_q50-pad2_ Q2N2907A +q50 net-_q10-pad1_ net-_q50-pad2_ net-_q49-pad3_ Q2N2222 +q33 net-_q10-pad1_ net-_q33-pad2_ net-_q31-pad2_ Q2N2222 +q31 net-_q10-pad1_ net-_q31-pad2_ net-_q27-pad3_ Q2N2222 +q24 net-_q22-pad2_ net-_q16-pad3_ net-_q24-pad3_ Q2N2222 +q27 net-_q22-pad2_ net-_q24-pad3_ net-_q27-pad3_ Q2N2222 +q28 net-_d8-pad1_ net-_q25-pad3_ net-_q28-pad3_ Q2N2907A +q25 net-_d8-pad1_ net-_q16-pad3_ net-_q25-pad3_ Q2N2907A +q32 net-_d4-pad2_ net-_q32-pad2_ net-_q28-pad3_ Q2N2907A +q34 net-_d4-pad2_ net-_q34-pad2_ net-_q32-pad2_ Q2N2907A +q29 net-_q29-pad1_ net-_q29-pad1_ net-_q29-pad3_ Q2N2222 +q35 net-_q10-pad1_ net-_q29-pad1_ net-_q35-pad3_ Q2N2222 +q30 net-_d4-pad2_ net-_q26-pad3_ net-_q29-pad3_ Q2N2907A +q36 net-_d4-pad2_ net-_q26-pad3_ net-_q35-pad3_ Q2N2907A +q22 net-_d9-pad1_ net-_q22-pad2_ net-_q10-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q14-pad2_ net-_q10-pad1_ Q2N2907A +q15 net-_q10-pad1_ net-_q14-pad1_ net-_q15-pad3_ Q2N2222 +q16 net-_q15-pad3_ net-_q15-pad3_ net-_q16-pad3_ Q2N2222 +q8 net-_q10-pad2_ net-_q14-pad2_ net-_q10-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_q10-pad3_ net-_q10-pad3_ net-_d5-pad2_ Q2N2222 +q4 net-_q10-pad1_ net-_q3-pad3_ net-_q14-pad2_ Q2N2222 +q3 net-_q14-pad2_ net-_q14-pad2_ net-_q3-pad3_ Q2N2222 +q6 net-_q14-pad2_ net-_q10-pad3_ net-_q6-pad3_ Q2N2222 +q17 net-_q16-pad3_ net-_d5-pad2_ net-_q12-pad1_ Q2N2222 +q18 net-_q12-pad1_ net-_q12-pad1_ net-_q18-pad3_ Q2N2222 +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2222 +q7 net-_d5-pad2_ net-_q12-pad1_ net-_q7-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_d1-pad1_ net-_q1-pad3_ Q2N2222 +q5 net-_q1-pad1_ net-_d6-pad2_ net-_q5-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q2-pad2_ net-_d4-pad2_ Q2N2222 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d1-pad2_ net-_d2-pad2_ 1N4148 +d3 net-_d2-pad2_ net-_d3-pad2_ 1N4148 +d4 net-_d3-pad2_ net-_d4-pad2_ 1N4148 +r1 net-_q1-pad1_ net-_d1-pad1_ 30k +r4 net-_q5-pad3_ net-_q2-pad2_ 270 +r5 net-_q2-pad2_ net-_d4-pad2_ 2.7k +r10 net-_d6-pad1_ net-_d5-pad1_ 470 +r11 net-_d7-pad1_ net-_d6-pad2_ 27k +q21 net-_d6-pad1_ net-_d9-pad1_ net-_d4-pad2_ Q2N2222 +r8 net-_q1-pad3_ net-_d6-pad2_ 620 +r13 net-_q1-pad3_ net-_d6-pad1_ 1.8k +r9 net-_q12-pad3_ net-_d4-pad2_ 100 +r7 net-_q7-pad3_ net-_d4-pad2_ 100 +r12 net-_q18-pad3_ net-_d4-pad2_ 100 +q26 net-_q10-pad1_ net-_q23-pad3_ net-_q26-pad3_ Q2N2222 +q23 net-_q10-pad1_ net-_q15-pad3_ net-_q23-pad3_ Q2N2222 +r16 net-_q23-pad3_ net-_q26-pad3_ 27k +r18 net-_q26-pad3_ net-_d4-pad2_ 27k +r20 net-_q10-pad1_ net-_q29-pad1_ 27k +r14 net-_d4-pad2_ net-_d8-pad1_ 4.7k +r15 net-_d4-pad2_ net-_d9-pad1_ 4.7k +r6 net-_q6-pad3_ net-_d5-pad2_ 40k +r2 net-_q10-pad1_ net-_r2-pad2_ 11k +r3 net-_r2-pad2_ net-_d4-pad2_ 39k +r17 net-_q10-pad1_ net-_q22-pad2_ 4k +r22 net-_q10-pad1_ net-_q33-pad2_ 5k +r23 net-_q33-pad2_ net-_q34-pad2_ 5k +r24 net-_q34-pad2_ net-_d4-pad2_ 5k +r19 net-_q28-pad3_ net-_q10-pad1_ 15k +r21 net-_d4-pad2_ net-_q27-pad3_ 10k +r26 net-_q45-pad3_ net-_q49-pad3_ 800 +r27 net-_q41-pad3_ net-_q49-pad3_ 2.7k +r28 net-_q37-pad3_ net-_q49-pad3_ 10k +r31 net-_q46-pad3_ net-_q49-pad3_ 800 +r30 net-_q42-pad3_ net-_q49-pad3_ 2.7k +r29 net-_q38-pad3_ net-_q49-pad3_ 10k +r35 net-_q10-pad1_ net-_q42-pad2_ 33k +r37 net-_q10-pad1_ net-_q46-pad2_ 33k +r39 net-_q10-pad1_ net-_q50-pad2_ 33k +r32 net-_q37-pad2_ net-_d4-pad2_ 33k +r34 net-_q41-pad2_ net-_d4-pad2_ 33k +r36 net-_q45-pad2_ net-_d4-pad2_ 33k +r38 net-_q49-pad2_ net-_d4-pad2_ 33k +r44 net-_q39-pad2_ net-_q40-pad2_ 1600 +r45 net-_q40-pad2_ net-_q44-pad2_ 330 +r46 net-_q44-pad2_ net-_q48-pad2_ 375 +r47 net-_q48-pad2_ net-_q52-pad2_ 200 +r48 net-_q52-pad2_ net-_d4-pad2_ 5.6k +r43 net-_q43-pad2_ net-_q39-pad2_ 330 +r42 net-_q47-pad2_ net-_q43-pad2_ 375 +r41 net-_q51-pad2_ net-_q47-pad2_ 200 +r40 net-_q10-pad1_ net-_q51-pad2_ 5.2k +r25 net-_q35-pad3_ net-_q49-pad3_ 1k +r33 net-_q10-pad1_ net-_q38-pad2_ 33k +q9 net-_d5-pad2_ net-_d5-pad1_ net-_d4-pad2_ Q2N2222 +d5 net-_d5-pad1_ net-_d5-pad2_ CBAT54 +d9 net-_d9-pad1_ net-_d6-pad1_ CBAT54 +q19 net-_d7-pad1_ net-_d8-pad1_ net-_d4-pad2_ Q2N2222 +d8 net-_d8-pad1_ net-_d7-pad1_ CBAT54 +q13 net-_d6-pad2_ net-_d6-pad1_ net-_d4-pad2_ Q2N2222 +d6 net-_d6-pad1_ net-_d6-pad2_ CBAT54 +q20 net-_d6-pad1_ net-_d7-pad1_ net-_d4-pad2_ Q2N2222 +d7 net-_d7-pad1_ net-_d6-pad1_ CBAT54 +* Control Statements + +.ends ICL8038 \ No newline at end of file diff --git a/Failed_subcircuits/ICL8038/ICL8038_Previous_Values.xml b/Failed_subcircuits/ICL8038/ICL8038_Previous_Values.xml new file mode 100644 index 000000000..55455821a --- /dev/null +++ b/Failed_subcircuits/ICL8038/ICL8038_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\User Libraries\CBAT54_Schottky.libC:\FOSSEE\eSim\library\deviceModelLibrary\User Libraries\CBAT54_Schottky.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\User Libraries\CBAT54_Schottky.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\User Libraries\CBAT54_Schottky.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\User Libraries\CBAT54_Schottky.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/ICL8038/NPN.lib b/Failed_subcircuits/ICL8038/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/Failed_subcircuits/ICL8038/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Failed_subcircuits/ICL8038/PNP.lib b/Failed_subcircuits/ICL8038/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/Failed_subcircuits/ICL8038/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/Failed_subcircuits/ICL8038/README.md b/Failed_subcircuits/ICL8038/README.md new file mode 100644 index 000000000..5ebfbb8d2 --- /dev/null +++ b/Failed_subcircuits/ICL8038/README.md @@ -0,0 +1,35 @@ + +# ICL8038 Function Generator IC + +The ICL8038 is a function generator chip, capable of generating triangular, square , sine, pulse and sawtooth waveforms . + + +## Usage/Examples + +Waveform Generator + +Frequency Modulator + +Linear VCO + +Used in PLLs + + +## Documentation + +To know the details of ICL8038 IC please refer to this link [ICL8038_datasheet.](https://www.mit.edu/~6.331/icl8038data.pdf) + +## Error Observed + +The output waveform is erratic and noisy in nature. + +## Possible Solution + +The designer is suggested to perform a block by block analysis/testing of the circuit or if needed, a block level redesign of the IC to obtain the desired results. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 \ No newline at end of file diff --git a/Failed_subcircuits/ICL8038/analysis b/Failed_subcircuits/ICL8038/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/Failed_subcircuits/ICL8038/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/Failed_subcircuits/ICL8038/schottky.lib b/Failed_subcircuits/ICL8038/schottky.lib new file mode 100644 index 000000000..9579f7352 --- /dev/null +++ b/Failed_subcircuits/ICL8038/schottky.lib @@ -0,0 +1 @@ +.model 1N5819 D(IS=390n RS=0.115 BV=40.0 IBV=1.00m CJO=203p M=0.333 N=1.70 TT=4.32u) diff --git a/Failed_subcircuits/LM307/LM307-cache.lib b/Failed_subcircuits/LM307/LM307-cache.lib new file mode 100644 index 000000000..7eda2392c --- /dev/null +++ b/Failed_subcircuits/LM307/LM307-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/LM307/LM307.cir b/Failed_subcircuits/LM307/LM307.cir new file mode 100644 index 000000000..74da18b9b --- /dev/null +++ b/Failed_subcircuits/LM307/LM307.cir @@ -0,0 +1,52 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM307\LM307.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 09/09/22 20:36:04 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_J1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q9 Net-_J1-Pad1_ Net-_Q9-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q10-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q5 Net-_Q10-Pad2_ Net-_Q10-Pad2_ Net-_Q1-Pad3_ eSim_PNP +Q10 Net-_C1-Pad2_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_PNP +Q7 Net-_Q10-Pad2_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_PNP +Q18 Net-_Q18-Pad1_ Net-_Q13-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q17 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q4 Net-_Q13-Pad1_ Net-_Q2-Pad1_ Net-_Q11-Pad2_ eSim_NPN +Q3 Net-_Q2-Pad1_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R1 Net-_Q11-Pad2_ Net-_Q11-Pad3_ 40k +Q11 Net-_C1-Pad2_ Net-_Q11-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q6 Net-_Q10-Pad2_ Net-_Q6-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q8 Net-_Q13-Pad1_ Net-_Q12-Pad1_ Net-_Q6-Pad2_ eSim_NPN +R2 Net-_Q6-Pad3_ Net-_R2-Pad2_ 5k +R3 Net-_Q6-Pad2_ Net-_R2-Pad2_ 20k +R4 Net-_R2-Pad2_ Net-_J1-Pad2_ 250 +R7 Net-_Q14-Pad1_ Net-_C1-Pad2_ 120 +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n +R5 Net-_J1-Pad3_ Net-_Q12-Pad1_ 450 +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q13 Net-_Q13-Pad1_ Net-_J1-Pad3_ Net-_Q12-Pad2_ eSim_NPN +R6 Net-_Q12-Pad2_ Net-_J1-Pad2_ 10k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q14 Net-_Q14-Pad1_ Net-_Q11-Pad3_ Net-_J1-Pad2_ eSim_NPN +Q15 Net-_Q13-Pad1_ Net-_Q14-Pad1_ Net-_Q15-Pad3_ eSim_NPN +R8 Net-_Q11-Pad3_ Net-_Q15-Pad3_ 40k +Q16 Net-_Q16-Pad1_ Net-_Q15-Pad3_ Net-_Q11-Pad3_ eSim_NPN +Q19 Net-_Q18-Pad1_ Net-_Q18-Pad1_ Net-_Q19-Pad3_ eSim_NPN +Q21 Net-_Q18-Pad1_ Net-_Q21-Pad2_ Net-_C2-Pad1_ eSim_NPN +Q23 Net-_J1-Pad1_ Net-_Q18-Pad1_ Net-_Q21-Pad2_ eSim_NPN +R13 Net-_C2-Pad1_ Net-_Q21-Pad2_ 25 +C2 Net-_C2-Pad1_ Net-_C1-Pad1_ 2p +R14 Net-_Q22-Pad3_ Net-_Q21-Pad2_ 65 +R12 Net-_C1-Pad1_ Net-_Q22-Pad3_ 7.5k +R9 Net-_C1-Pad1_ Net-_Q16-Pad1_ 620 +Q20 Net-_J1-Pad2_ Net-_Q16-Pad1_ Net-_Q19-Pad3_ eSim_PNP +Q22 Net-_Q22-Pad1_ Net-_Q16-Pad1_ Net-_Q22-Pad3_ eSim_PNP +Q24 Net-_Q22-Pad3_ Net-_Q22-Pad1_ Net-_J1-Pad2_ eSim_NPN +R10 Net-_Q22-Pad1_ Net-_Q11-Pad3_ 80k +R11 Net-_Q11-Pad3_ Net-_J1-Pad2_ 650 +U1 Net-_Q1-Pad2_ Net-_Q9-Pad2_ Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_C2-Pad1_ ? ? ? PORT + +.end diff --git a/Failed_subcircuits/LM307/LM307.cir.out b/Failed_subcircuits/LM307/LM307.cir.out new file mode 100644 index 000000000..c5a8a1e24 --- /dev/null +++ b/Failed_subcircuits/LM307/LM307.cir.out @@ -0,0 +1,56 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm307\lm307.cir + +.include NPN.lib +.include PNP.lib +.include NJF.lib +q1 net-_j1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q9 net-_j1-pad1_ net-_q9-pad2_ net-_q10-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q10-pad2_ net-_q1-pad3_ Q2N2907A +q5 net-_q10-pad2_ net-_q10-pad2_ net-_q1-pad3_ Q2N2907A +q10 net-_c1-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A +q7 net-_q10-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A +q18 net-_q18-pad1_ net-_q13-pad1_ net-_j1-pad1_ Q2N2907A +q17 net-_q13-pad1_ net-_q13-pad1_ net-_j1-pad1_ Q2N2907A +q4 net-_q13-pad1_ net-_q2-pad1_ net-_q11-pad2_ Q2N2222 +q3 net-_q2-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +r1 net-_q11-pad2_ net-_q11-pad3_ 40k +q11 net-_c1-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q6 net-_q10-pad2_ net-_q6-pad2_ net-_q6-pad3_ Q2N2222 +q8 net-_q13-pad1_ net-_q12-pad1_ net-_q6-pad2_ Q2N2222 +r2 net-_q6-pad3_ net-_r2-pad2_ 5k +r3 net-_q6-pad2_ net-_r2-pad2_ 20k +r4 net-_r2-pad2_ net-_j1-pad2_ 250 +r7 net-_q14-pad1_ net-_c1-pad2_ 120 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +r5 net-_j1-pad3_ net-_q12-pad1_ 450 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_j1-pad2_ Q2N2222 +q13 net-_q13-pad1_ net-_j1-pad3_ net-_q12-pad2_ Q2N2222 +r6 net-_q12-pad2_ net-_j1-pad2_ 10k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q14 net-_q14-pad1_ net-_q11-pad3_ net-_j1-pad2_ Q2N2222 +q15 net-_q13-pad1_ net-_q14-pad1_ net-_q15-pad3_ Q2N2222 +r8 net-_q11-pad3_ net-_q15-pad3_ 40k +q16 net-_q16-pad1_ net-_q15-pad3_ net-_q11-pad3_ Q2N2222 +q19 net-_q18-pad1_ net-_q18-pad1_ net-_q19-pad3_ Q2N2222 +q21 net-_q18-pad1_ net-_q21-pad2_ net-_c2-pad1_ Q2N2222 +q23 net-_j1-pad1_ net-_q18-pad1_ net-_q21-pad2_ Q2N2222 +r13 net-_c2-pad1_ net-_q21-pad2_ 25 +c2 net-_c2-pad1_ net-_c1-pad1_ 2p +r14 net-_q22-pad3_ net-_q21-pad2_ 65 +r12 net-_c1-pad1_ net-_q22-pad3_ 7.5k +r9 net-_c1-pad1_ net-_q16-pad1_ 620 +q20 net-_j1-pad2_ net-_q16-pad1_ net-_q19-pad3_ Q2N2907A +q22 net-_q22-pad1_ net-_q16-pad1_ net-_q22-pad3_ Q2N2907A +q24 net-_q22-pad3_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +r10 net-_q22-pad1_ net-_q11-pad3_ 80k +r11 net-_q11-pad3_ net-_j1-pad2_ 650 +* u1 net-_q1-pad2_ net-_q9-pad2_ net-_j1-pad1_ net-_j1-pad2_ net-_c2-pad1_ ? ? ? port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/LM307/LM307.pro b/Failed_subcircuits/LM307/LM307.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/LM307/LM307.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/LM307/LM307.sch b/Failed_subcircuits/LM307/LM307.sch new file mode 100644 index 000000000..16ed3f660 --- /dev/null +++ b/Failed_subcircuits/LM307/LM307.sch @@ -0,0 +1,867 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM307-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_NPN Q1 +U 1 1 63122A38 +P 1550 1250 +F 0 "Q1" H 1450 1300 50 0000 R CNN +F 1 "eSim_NPN" H 1500 1400 50 0000 R CNN +F 2 "" H 1750 1350 29 0000 C CNN +F 3 "" H 1550 1250 60 0000 C CNN + 1 1550 1250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q9 +U 1 1 63122A39 +P 3150 1250 +F 0 "Q9" H 3050 1300 50 0000 R CNN +F 1 "eSim_NPN" H 3100 1400 50 0000 R CNN +F 2 "" H 3350 1350 29 0000 C CNN +F 3 "" H 3150 1250 60 0000 C CNN + 1 3150 1250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 63122A3A +P 1550 1850 +F 0 "Q2" H 1450 1900 50 0000 R CNN +F 1 "eSim_PNP" H 1500 2000 50 0000 R CNN +F 2 "" H 1750 1950 29 0000 C CNN +F 3 "" H 1550 1850 60 0000 C CNN + 1 1550 1850 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 63122A3B +P 1900 2200 +F 0 "Q5" H 1800 2250 50 0000 R CNN +F 1 "eSim_PNP" H 1850 2350 50 0000 R CNN +F 2 "" H 2100 2300 29 0000 C CNN +F 3 "" H 1900 2200 60 0000 C CNN + 1 1900 2200 + -1 0 0 1 +$EndComp +Wire Wire Line + 1450 1650 1800 1650 +Wire Wire Line + 1800 1650 1800 2000 +Wire Wire Line + 1750 1850 2100 1850 +Wire Wire Line + 2100 1850 2100 2200 +Wire Wire Line + 1450 2050 1450 3500 +Wire Wire Line + 1800 2400 1800 2450 +Wire Wire Line + 1650 1450 1650 1650 +Connection ~ 1650 1650 +$Comp +L eSim_PNP Q10 +U 1 1 63122A3C +P 3150 1850 +F 0 "Q10" H 3050 1900 50 0000 R CNN +F 1 "eSim_PNP" H 3100 2000 50 0000 R CNN +F 2 "" H 3350 1950 29 0000 C CNN +F 3 "" H 3150 1850 60 0000 C CNN + 1 3150 1850 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 63122A3D +P 2800 2200 +F 0 "Q7" H 2700 2250 50 0000 R CNN +F 1 "eSim_PNP" H 2750 2350 50 0000 R CNN +F 2 "" H 3000 2300 29 0000 C CNN +F 3 "" H 2800 2200 60 0000 C CNN + 1 2800 2200 + 1 0 0 1 +$EndComp +Wire Wire Line + 2900 1650 3250 1650 +Wire Wire Line + 2900 1650 2900 2000 +Wire Wire Line + 2950 1850 2600 1850 +Wire Wire Line + 2600 1850 2600 2200 +Wire Wire Line + 3250 2050 3250 3500 +Wire Wire Line + 2900 2450 2900 2400 +Wire Wire Line + 3050 1450 3050 1650 +Connection ~ 3050 1650 +Wire Wire Line + 1800 2450 2900 2450 +Wire Wire Line + 1350 1250 850 1250 +Wire Wire Line + 3350 1250 3350 1550 +Wire Wire Line + 3350 1550 850 1550 +Wire Wire Line + 2100 2000 2600 2000 +Wire Wire Line + 2350 2000 2350 2450 +Connection ~ 2350 2450 +Connection ~ 2100 2000 +Connection ~ 2600 2000 +Connection ~ 2350 2000 +Wire Wire Line + 1650 1050 1650 900 +Wire Wire Line + 3050 1050 3050 900 +Wire Wire Line + 1650 900 8300 900 +Connection ~ 3050 900 +$Comp +L eSim_PNP Q18 +U 1 1 63122A3E +P 6750 1200 +F 0 "Q18" H 6650 1250 50 0000 R CNN +F 1 "eSim_PNP" H 6700 1350 50 0000 R CNN +F 2 "" H 6950 1300 29 0000 C CNN +F 3 "" H 6750 1200 60 0000 C CNN + 1 6750 1200 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q17 +U 1 1 63122A3F +P 6400 1500 +F 0 "Q17" H 6300 1550 50 0000 R CNN +F 1 "eSim_PNP" H 6350 1650 50 0000 R CNN +F 2 "" H 6600 1600 29 0000 C CNN +F 3 "" H 6400 1500 60 0000 C CNN + 1 6400 1500 + 1 0 0 1 +$EndComp +Wire Wire Line + 6500 1000 6850 1000 +Wire Wire Line + 6500 1000 6500 1300 +Wire Wire Line + 6700 1800 6700 1900 +Wire Wire Line + 6500 1750 6500 1700 +Wire Wire Line + 6650 900 6650 1000 +Connection ~ 6650 1000 +Wire Wire Line + 5450 1750 6500 1750 +Connection ~ 6050 1750 +Connection ~ 6650 900 +Wire Wire Line + 5400 900 5400 700 +Connection ~ 5400 900 +$Comp +L eSim_NPN Q4 +U 1 1 63122A40 +P 1800 3350 +F 0 "Q4" H 1700 3400 50 0000 R CNN +F 1 "eSim_NPN" H 1750 3500 50 0000 R CNN +F 2 "" H 2000 3450 29 0000 C CNN +F 3 "" H 1800 3350 60 0000 C CNN + 1 1800 3350 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1900 3150 1900 3000 +Wire Wire Line + 1900 3000 5450 3000 +$Comp +L eSim_NPN Q3 +U 1 1 63122A41 +P 1550 3700 +F 0 "Q3" H 1450 3750 50 0000 R CNN +F 1 "eSim_NPN" H 1500 3850 50 0000 R CNN +F 2 "" H 1750 3800 29 0000 C CNN +F 3 "" H 1550 3700 60 0000 C CNN + 1 1550 3700 + -1 0 0 -1 +$EndComp +Connection ~ 1450 3350 +Wire Wire Line + 1450 3900 1450 4200 +Wire Wire Line + 1450 4200 7450 4200 +$Comp +L resistor R1 +U 1 1 63122A42 +P 1850 3900 +F 0 "R1" H 1900 4030 50 0000 C CNN +F 1 "40k" H 1900 3850 50 0000 C CNN +F 2 "" H 1900 3880 30 0000 C CNN +F 3 "" V 1900 3950 30 0000 C CNN + 1 1850 3900 + 0 1 1 0 +$EndComp +Wire Wire Line + 1750 3700 2950 3700 +$Comp +L eSim_NPN Q11 +U 1 1 63122A43 +P 3150 3700 +F 0 "Q11" H 3050 3750 50 0000 R CNN +F 1 "eSim_NPN" H 3100 3850 50 0000 R CNN +F 2 "" H 3350 3800 29 0000 C CNN +F 3 "" H 3150 3700 60 0000 C CNN + 1 3150 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1600 3350 1450 3350 +Wire Wire Line + 1900 3550 1900 3800 +Connection ~ 1900 3700 +Wire Wire Line + 3250 4200 3250 3900 +$Comp +L eSim_NPN Q6 +U 1 1 63122A44 +P 2550 5350 +F 0 "Q6" H 2450 5400 50 0000 R CNN +F 1 "eSim_NPN" H 2500 5500 50 0000 R CNN +F 2 "" H 2750 5450 29 0000 C CNN +F 3 "" H 2550 5350 60 0000 C CNN + 1 2550 5350 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2450 2450 2450 5150 +Connection ~ 2450 2450 +$Comp +L eSim_NPN Q8 +U 1 1 63122A45 +P 3000 5100 +F 0 "Q8" H 2900 5150 50 0000 R CNN +F 1 "eSim_NPN" H 2950 5250 50 0000 R CNN +F 2 "" H 3200 5200 29 0000 C CNN +F 3 "" H 3000 5100 60 0000 C CNN + 1 3000 5100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 2900 5300 2900 5550 +Wire Wire Line + 2900 5350 2750 5350 +$Comp +L resistor R2 +U 1 1 63122A46 +P 2400 5700 +F 0 "R2" H 2450 5830 50 0000 C CNN +F 1 "5k" H 2450 5650 50 0000 C CNN +F 2 "" H 2450 5680 30 0000 C CNN +F 3 "" V 2450 5750 30 0000 C CNN + 1 2400 5700 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 63122A47 +P 2850 5650 +F 0 "R3" H 2900 5780 50 0000 C CNN +F 1 "20k" H 2900 5600 50 0000 C CNN +F 2 "" H 2900 5630 30 0000 C CNN +F 3 "" V 2900 5700 30 0000 C CNN + 1 2850 5650 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 63122A48 +P 2850 6100 +F 0 "R4" H 2900 6230 50 0000 C CNN +F 1 "250" H 2900 6050 50 0000 C CNN +F 2 "" H 2900 6080 30 0000 C CNN +F 3 "" V 2900 6150 30 0000 C CNN + 1 2850 6100 + 0 1 1 0 +$EndComp +Wire Wire Line + 2450 5600 2450 5550 +Connection ~ 2900 5350 +Wire Wire Line + 2450 5900 2450 5950 +Wire Wire Line + 2450 5950 2900 5950 +Wire Wire Line + 2900 5850 2900 6000 +Connection ~ 2900 5950 +Wire Wire Line + 2900 6300 2900 6350 +Wire Wire Line + 3250 3450 4600 3450 +Connection ~ 3250 3450 +Connection ~ 3250 4200 +$Comp +L resistor R7 +U 1 1 63122A49 +P 4800 3400 +F 0 "R7" H 4850 3530 50 0000 C CNN +F 1 "120" H 4850 3350 50 0000 C CNN +F 2 "" H 4850 3380 30 0000 C CNN +F 3 "" V 4850 3450 30 0000 C CNN + 1 4800 3400 + -1 0 0 1 +$EndComp +$Comp +L jfet_n J1 +U 1 1 63122A4A +P 3750 4450 +F 0 "J1" H 3650 4500 50 0000 R CNN +F 1 "jfet_n" H 3700 4600 50 0000 R CNN +F 2 "" H 3950 4550 29 0000 C CNN +F 3 "" H 3750 4450 60 0000 C CNN + 1 3750 4450 + 1 0 0 -1 +$EndComp +$Comp +L resistor R5 +U 1 1 63122A4B +P 3800 4850 +F 0 "R5" H 3850 4980 50 0000 C CNN +F 1 "450" H 3850 4800 50 0000 C CNN +F 2 "" H 3850 4830 30 0000 C CNN +F 3 "" V 3850 4900 30 0000 C CNN + 1 3800 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 3850 4250 3850 900 +Connection ~ 3850 900 +Wire Wire Line + 3850 4650 3850 4750 +Wire Wire Line + 3200 5100 3850 5100 +Wire Wire Line + 3850 5050 3850 5250 +$Comp +L eSim_NPN Q12 +U 1 1 63122A4C +P 3950 5450 +F 0 "Q12" H 3850 5500 50 0000 R CNN +F 1 "eSim_NPN" H 3900 5600 50 0000 R CNN +F 2 "" H 4150 5550 29 0000 C CNN +F 3 "" H 3950 5450 60 0000 C CNN + 1 3950 5450 + -1 0 0 -1 +$EndComp +Connection ~ 3850 5100 +Wire Wire Line + 2900 6350 8300 6350 +Wire Wire Line + 3550 4450 3400 4450 +Wire Wire Line + 3400 4450 3400 6350 +Connection ~ 3400 6350 +Wire Wire Line + 3850 5650 3850 6350 +Connection ~ 3850 6350 +$Comp +L eSim_NPN Q13 +U 1 1 63122A4D +P 4250 4700 +F 0 "Q13" H 4150 4750 50 0000 R CNN +F 1 "eSim_NPN" H 4200 4850 50 0000 R CNN +F 2 "" H 4450 4800 29 0000 C CNN +F 3 "" H 4250 4700 60 0000 C CNN + 1 4250 4700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4050 4700 3850 4700 +Connection ~ 3850 4700 +Wire Wire Line + 4350 4900 4350 5650 +Wire Wire Line + 4350 5450 4150 5450 +$Comp +L resistor R6 +U 1 1 63122A4E +P 4300 5750 +F 0 "R6" H 4350 5880 50 0000 C CNN +F 1 "10k" H 4350 5700 50 0000 C CNN +F 2 "" H 4350 5730 30 0000 C CNN +F 3 "" V 4350 5800 30 0000 C CNN + 1 4300 5750 + 0 1 1 0 +$EndComp +Connection ~ 4350 5450 +Wire Wire Line + 4350 5950 4350 6350 +Connection ~ 4350 6350 +Wire Wire Line + 4350 3000 4350 4500 +Connection ~ 4350 3000 +$Comp +L capacitor C1 +U 1 1 63122A4F +P 4950 3150 +F 0 "C1" H 4975 3250 50 0000 L CNN +F 1 "30p" H 4975 3050 50 0000 L CNN +F 2 "" H 4988 3000 30 0000 C CNN +F 3 "" H 4950 3150 60 0000 C CNN + 1 4950 3150 + 0 1 1 0 +$EndComp +Wire Wire Line + 4450 3450 4450 3150 +Connection ~ 4450 3450 +$Comp +L eSim_NPN Q14 +U 1 1 63122A50 +P 5150 4450 +F 0 "Q14" H 5050 4500 50 0000 R CNN +F 1 "eSim_NPN" H 5100 4600 50 0000 R CNN +F 2 "" H 5350 4550 29 0000 C CNN +F 3 "" H 5150 4450 60 0000 C CNN + 1 5150 4450 + -1 0 0 -1 +$EndComp +Wire Wire Line + 4900 3450 5150 3450 +Wire Wire Line + 5050 3450 5050 4250 +$Comp +L eSim_NPN Q15 +U 1 1 63122A51 +P 5350 3450 +F 0 "Q15" H 5250 3500 50 0000 R CNN +F 1 "eSim_NPN" H 5300 3600 50 0000 R CNN +F 2 "" H 5550 3550 29 0000 C CNN +F 3 "" H 5350 3450 60 0000 C CNN + 1 5350 3450 + 1 0 0 -1 +$EndComp +Connection ~ 5050 3450 +Wire Wire Line + 5450 1750 5450 3250 +Wire Wire Line + 5600 2800 7350 2800 +Wire Wire Line + 5050 4650 5050 6350 +Connection ~ 5050 6350 +$Comp +L resistor R8 +U 1 1 63122A52 +P 5500 4000 +F 0 "R8" H 5550 4130 50 0000 C CNN +F 1 "40k" H 5550 3950 50 0000 C CNN +F 2 "" H 5550 3980 30 0000 C CNN +F 3 "" V 5550 4050 30 0000 C CNN + 1 5500 4000 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 5450 3650 5450 3800 +Wire Wire Line + 5450 4100 5450 4450 +Connection ~ 5450 4200 +$Comp +L eSim_NPN Q16 +U 1 1 63122A53 +P 6000 3700 +F 0 "Q16" H 5900 3750 50 0000 R CNN +F 1 "eSim_NPN" H 5950 3850 50 0000 R CNN +F 2 "" H 6200 3800 29 0000 C CNN +F 3 "" H 6000 3700 60 0000 C CNN + 1 6000 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 63122A54 +P 6600 2100 +F 0 "Q19" H 6500 2150 50 0000 R CNN +F 1 "eSim_NPN" H 6550 2250 50 0000 R CNN +F 2 "" H 6800 2200 29 0000 C CNN +F 3 "" H 6600 2100 60 0000 C CNN + 1 6600 2100 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q21 +U 1 1 63122A55 +P 7350 2100 +F 0 "Q21" H 7250 2150 50 0000 R CNN +F 1 "eSim_NPN" H 7300 2250 50 0000 R CNN +F 2 "" H 7550 2200 29 0000 C CNN +F 3 "" H 7350 2100 60 0000 C CNN + 1 7350 2100 + -1 0 0 -1 +$EndComp +Wire Wire Line + 6400 1800 8000 1800 +Wire Wire Line + 7250 1800 7250 1900 +Connection ~ 6700 1800 +Wire Wire Line + 6400 1800 6400 2100 +$Comp +L eSim_NPN Q23 +U 1 1 63122A56 +P 8200 1800 +F 0 "Q23" H 8100 1850 50 0000 R CNN +F 1 "eSim_NPN" H 8150 1950 50 0000 R CNN +F 2 "" H 8400 1900 29 0000 C CNN +F 3 "" H 8200 1800 60 0000 C CNN + 1 8200 1800 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8300 900 8300 1600 +Connection ~ 7250 1800 +Wire Wire Line + 7550 2100 8300 2100 +Wire Wire Line + 8300 2000 8300 2200 +$Comp +L resistor R13 +U 1 1 63122A57 +P 7900 2350 +F 0 "R13" H 7950 2480 50 0000 C CNN +F 1 "25" H 7950 2300 50 0000 C CNN +F 2 "" H 7950 2330 30 0000 C CNN +F 3 "" V 7950 2400 30 0000 C CNN + 1 7900 2350 + 0 -1 -1 0 +$EndComp +Wire Wire Line + 7850 2150 7850 2100 +Connection ~ 7850 2100 +$Comp +L capacitor C2 +U 1 1 63122A58 +P 7050 2550 +F 0 "C2" H 7075 2650 50 0000 L CNN +F 1 "2p" H 7075 2450 50 0000 L CNN +F 2 "" H 7088 2400 30 0000 C CNN +F 3 "" H 7050 2550 60 0000 C CNN + 1 7050 2550 + 0 1 1 0 +$EndComp +Wire Wire Line + 7250 2300 7250 2550 +Wire Wire Line + 7200 2550 8700 2550 +Wire Wire Line + 7850 2550 7850 2450 +Connection ~ 7250 2550 +Connection ~ 8300 2100 +$Comp +L resistor R14 +U 1 1 63122A59 +P 8350 2400 +F 0 "R14" H 8400 2530 50 0000 C CNN +F 1 "65" H 8400 2350 50 0000 C CNN +F 2 "" H 8400 2380 30 0000 C CNN +F 3 "" V 8400 2450 30 0000 C CNN + 1 8350 2400 + 0 -1 -1 0 +$EndComp +Connection ~ 7850 2550 +Connection ~ 5450 3000 +Wire Wire Line + 6900 2550 5600 2550 +Wire Wire Line + 5600 2550 5600 3150 +$Comp +L resistor R12 +U 1 1 63122A5A +P 7450 2850 +F 0 "R12" H 7500 2980 50 0000 C CNN +F 1 "7.5k" H 7500 2800 50 0000 C CNN +F 2 "" H 7500 2830 30 0000 C CNN +F 3 "" V 7500 2900 30 0000 C CNN + 1 7450 2850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8300 2500 8300 3450 +Wire Wire Line + 8300 2800 7650 2800 +Connection ~ 5600 2800 +Wire Wire Line + 5100 3150 5700 3150 +$Comp +L resistor R9 +U 1 1 63122A5B +P 5800 3200 +F 0 "R9" H 5850 3330 50 0000 C CNN +F 1 "620" H 5850 3150 50 0000 C CNN +F 2 "" H 5850 3180 30 0000 C CNN +F 3 "" V 5850 3250 30 0000 C CNN + 1 5800 3200 + 1 0 0 -1 +$EndComp +Connection ~ 5600 3150 +Wire Wire Line + 6100 2950 6100 3500 +Wire Wire Line + 5450 3700 5800 3700 +Connection ~ 5450 3700 +Wire Wire Line + 6100 3900 6100 4200 +Connection ~ 6100 4200 +$Comp +L eSim_PNP Q20 +U 1 1 63122A5C +P 6800 3150 +F 0 "Q20" H 6700 3200 50 0000 R CNN +F 1 "eSim_PNP" H 6750 3300 50 0000 R CNN +F 2 "" H 7000 3250 29 0000 C CNN +F 3 "" H 6800 3150 60 0000 C CNN + 1 6800 3150 + -1 0 0 1 +$EndComp +Wire Wire Line + 6700 2950 6700 2300 +Wire Wire Line + 6700 6350 6700 3350 +$Comp +L eSim_PNP Q22 +U 1 1 63122A5D +P 7350 3150 +F 0 "Q22" H 7250 3200 50 0000 R CNN +F 1 "eSim_PNP" H 7300 3300 50 0000 R CNN +F 2 "" H 7550 3250 29 0000 C CNN +F 3 "" H 7350 3150 60 0000 C CNN + 1 7350 3150 + 1 0 0 1 +$EndComp +Wire Wire Line + 8300 2950 7450 2950 +Connection ~ 8300 2800 +$Comp +L eSim_NPN Q24 +U 1 1 63122A5E +P 8200 3650 +F 0 "Q24" H 8100 3700 50 0000 R CNN +F 1 "eSim_NPN" H 8150 3800 50 0000 R CNN +F 2 "" H 8400 3750 29 0000 C CNN +F 3 "" H 8200 3650 60 0000 C CNN + 1 8200 3650 + 1 0 0 -1 +$EndComp +Connection ~ 8300 2950 +Wire Wire Line + 7450 3350 7450 3750 +Wire Wire Line + 7450 3650 8000 3650 +$Comp +L resistor R10 +U 1 1 63122A5F +P 7400 3850 +F 0 "R10" H 7450 3980 50 0000 C CNN +F 1 "80k" H 7450 3800 50 0000 C CNN +F 2 "" H 7450 3830 30 0000 C CNN +F 3 "" V 7450 3900 30 0000 C CNN + 1 7400 3850 + 0 1 1 0 +$EndComp +Connection ~ 7450 3650 +Wire Wire Line + 7450 4050 7450 4950 +Wire Wire Line + 8300 6350 8300 3850 +Connection ~ 6700 6350 +$Comp +L resistor R11 +U 1 1 63122A60 +P 7400 5050 +F 0 "R11" H 7450 5180 50 0000 C CNN +F 1 "650" H 7450 5000 50 0000 C CNN +F 2 "" H 7450 5030 30 0000 C CNN +F 3 "" V 7450 5100 30 0000 C CNN + 1 7400 5050 + 0 1 1 0 +$EndComp +Connection ~ 7450 4200 +Wire Wire Line + 7450 5250 7450 6350 +Connection ~ 7450 6350 +Wire Wire Line + 5450 6350 5450 6650 +Connection ~ 5450 6350 +Wire Wire Line + 4450 3150 4800 3150 +$Comp +L PORT U1 +U 5 1 63122B87 +P 8950 2550 +F 0 "U1" H 9000 2650 30 0000 C CNN +F 1 "PORT" H 8950 2550 30 0000 C CNN +F 2 "" H 8950 2550 60 0000 C CNN +F 3 "" H 8950 2550 60 0000 C CNN + 5 8950 2550 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 3 1 63122D28 +P 5150 700 +F 0 "U1" H 5200 800 30 0000 C CNN +F 1 "PORT" H 5150 700 30 0000 C CNN +F 2 "" H 5150 700 60 0000 C CNN +F 3 "" H 5150 700 60 0000 C CNN + 3 5150 700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 6312343C +P 850 1000 +F 0 "U1" H 900 1100 30 0000 C CNN +F 1 "PORT" H 850 1000 30 0000 C CNN +F 2 "" H 850 1000 60 0000 C CNN +F 3 "" H 850 1000 60 0000 C CNN + 1 850 1000 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 631234B1 +P 850 1800 +F 0 "U1" H 900 1900 30 0000 C CNN +F 1 "PORT" H 850 1800 30 0000 C CNN +F 2 "" H 850 1800 60 0000 C CNN +F 3 "" H 850 1800 60 0000 C CNN + 2 850 1800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 63123785 +P 5450 6900 +F 0 "U1" H 5500 7000 30 0000 C CNN +F 1 "PORT" H 5450 6900 30 0000 C CNN +F 2 "" H 5450 6900 60 0000 C CNN +F 3 "" H 5450 6900 60 0000 C CNN + 4 5450 6900 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 63123F8A +P 8950 4050 +F 0 "U1" H 9000 4150 30 0000 C CNN +F 1 "PORT" H 8950 4050 30 0000 C CNN +F 2 "" H 8950 4050 60 0000 C CNN +F 3 "" H 8950 4050 60 0000 C CNN + 6 8950 4050 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 7 1 6312402B +P 8950 4350 +F 0 "U1" H 9000 4450 30 0000 C CNN +F 1 "PORT" H 8950 4350 30 0000 C CNN +F 2 "" H 8950 4350 60 0000 C CNN +F 3 "" H 8950 4350 60 0000 C CNN + 7 8950 4350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 8 1 631240CC +P 8950 4650 +F 0 "U1" H 9000 4750 30 0000 C CNN +F 1 "PORT" H 8950 4650 30 0000 C CNN +F 2 "" H 8950 4650 60 0000 C CNN +F 3 "" H 8950 4650 60 0000 C CNN + 8 8950 4650 + -1 0 0 1 +$EndComp +NoConn ~ 8700 4050 +NoConn ~ 8700 4350 +NoConn ~ 8700 4650 +Wire Wire Line + 2900 4900 2900 3000 +Connection ~ 2900 3000 +Wire Wire Line + 6550 1200 6200 1200 +Wire Wire Line + 6200 1200 6200 1500 +Wire Wire Line + 6200 1400 6050 1400 +Wire Wire Line + 6050 1400 6050 1750 +Connection ~ 6200 1400 +Wire Wire Line + 1900 4100 1900 4200 +Connection ~ 1900 4200 +Wire Wire Line + 5450 4450 5350 4450 +Wire Wire Line + 7000 3150 7150 3150 +Connection ~ 7100 3150 +Wire Wire Line + 6100 3150 6000 3150 +Wire Wire Line + 7100 3150 7100 2950 +Wire Wire Line + 7100 2950 6100 2950 +Connection ~ 6100 3150 +Wire Wire Line + 6850 1400 6850 1800 +Connection ~ 6850 1800 +$EndSCHEMATC diff --git a/Failed_subcircuits/LM307/LM307.sub b/Failed_subcircuits/LM307/LM307.sub new file mode 100644 index 000000000..6d3363fd8 --- /dev/null +++ b/Failed_subcircuits/LM307/LM307.sub @@ -0,0 +1,50 @@ +* Subcircuit LM307 +.subckt LM307 net-_q1-pad2_ net-_q9-pad2_ net-_j1-pad1_ net-_j1-pad2_ net-_c2-pad1_ ? ? ? +* c:\fossee\esim\library\subcircuitlibrary\lm307\lm307.cir +.include NPN.lib +.include PNP.lib +.include NJF.lib +q1 net-_j1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q9 net-_j1-pad1_ net-_q9-pad2_ net-_q10-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q10-pad2_ net-_q1-pad3_ Q2N2907A +q5 net-_q10-pad2_ net-_q10-pad2_ net-_q1-pad3_ Q2N2907A +q10 net-_c1-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A +q7 net-_q10-pad2_ net-_q10-pad2_ net-_q10-pad3_ Q2N2907A +q18 net-_q18-pad1_ net-_q13-pad1_ net-_j1-pad1_ Q2N2907A +q17 net-_q13-pad1_ net-_q13-pad1_ net-_j1-pad1_ Q2N2907A +q4 net-_q13-pad1_ net-_q2-pad1_ net-_q11-pad2_ Q2N2222 +q3 net-_q2-pad1_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +r1 net-_q11-pad2_ net-_q11-pad3_ 40k +q11 net-_c1-pad2_ net-_q11-pad2_ net-_q11-pad3_ Q2N2222 +q6 net-_q10-pad2_ net-_q6-pad2_ net-_q6-pad3_ Q2N2222 +q8 net-_q13-pad1_ net-_q12-pad1_ net-_q6-pad2_ Q2N2222 +r2 net-_q6-pad3_ net-_r2-pad2_ 5k +r3 net-_q6-pad2_ net-_r2-pad2_ 20k +r4 net-_r2-pad2_ net-_j1-pad2_ 250 +r7 net-_q14-pad1_ net-_c1-pad2_ 120 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +r5 net-_j1-pad3_ net-_q12-pad1_ 450 +q12 net-_q12-pad1_ net-_q12-pad2_ net-_j1-pad2_ Q2N2222 +q13 net-_q13-pad1_ net-_j1-pad3_ net-_q12-pad2_ Q2N2222 +r6 net-_q12-pad2_ net-_j1-pad2_ 10k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q14 net-_q14-pad1_ net-_q11-pad3_ net-_j1-pad2_ Q2N2222 +q15 net-_q13-pad1_ net-_q14-pad1_ net-_q15-pad3_ Q2N2222 +r8 net-_q11-pad3_ net-_q15-pad3_ 40k +q16 net-_q16-pad1_ net-_q15-pad3_ net-_q11-pad3_ Q2N2222 +q19 net-_q18-pad1_ net-_q18-pad1_ net-_q19-pad3_ Q2N2222 +q21 net-_q18-pad1_ net-_q21-pad2_ net-_c2-pad1_ Q2N2222 +q23 net-_j1-pad1_ net-_q18-pad1_ net-_q21-pad2_ Q2N2222 +r13 net-_c2-pad1_ net-_q21-pad2_ 25 +c2 net-_c2-pad1_ net-_c1-pad1_ 2p +r14 net-_q22-pad3_ net-_q21-pad2_ 65 +r12 net-_c1-pad1_ net-_q22-pad3_ 7.5k +r9 net-_c1-pad1_ net-_q16-pad1_ 620 +q20 net-_j1-pad2_ net-_q16-pad1_ net-_q19-pad3_ Q2N2907A +q22 net-_q22-pad1_ net-_q16-pad1_ net-_q22-pad3_ Q2N2907A +q24 net-_q22-pad3_ net-_q22-pad1_ net-_j1-pad2_ Q2N2222 +r10 net-_q22-pad1_ net-_q11-pad3_ 80k +r11 net-_q11-pad3_ net-_j1-pad2_ 650 +* Control Statements + +.ends LM307 \ No newline at end of file diff --git a/Failed_subcircuits/LM307/LM307_Previous_Values.xml b/Failed_subcircuits/LM307/LM307_Previous_Values.xml new file mode 100644 index 000000000..4f0f16d73 --- /dev/null +++ b/Failed_subcircuits/LM307/LM307_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/Failed_subcircuits/LM307/NJF.lib b/Failed_subcircuits/LM307/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/Failed_subcircuits/LM307/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/Failed_subcircuits/LM307/NPN.lib b/Failed_subcircuits/LM307/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/Failed_subcircuits/LM307/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Failed_subcircuits/LM307/PNP.lib b/Failed_subcircuits/LM307/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/Failed_subcircuits/LM307/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/Failed_subcircuits/LM307/README.md b/Failed_subcircuits/LM307/README.md new file mode 100644 index 000000000..8500bce44 --- /dev/null +++ b/Failed_subcircuits/LM307/README.md @@ -0,0 +1,37 @@ + +# LM307 Operational Amplifier IC + +The LM307 is a linear monolithic general purpose Operational Amplifier IC, with necessary internal frequency compensation built in. + +## Usage/Examples + +Inverting/Non-Inverting Amplifier + +Integrator/Summer + +Differential Amplifier + +Differentiator + +Schmitt Trigger + +Comparators + +## Documentation + +To know the details of LM307 IC please refer to this link [LM307_datasheet.](http://www.suzushoweb.com/pdf_file/569dd4b9e0aa5.pdf) + +## Error Observed + +The output obatined for Inverting/Non-Inverting Amplifier test circuits is not correct. + +## Possible Solution + +The designer is suggested to perform a block level redesign of the IC to obtain the desired results. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 \ No newline at end of file diff --git a/Failed_subcircuits/LM307/analysis b/Failed_subcircuits/LM307/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/Failed_subcircuits/LM307/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/Failed_subcircuits/LM310/D.lib b/Failed_subcircuits/LM310/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/Failed_subcircuits/LM310/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/Failed_subcircuits/LM310/LM310-cache.lib b/Failed_subcircuits/LM310/LM310-cache.lib new file mode 100644 index 000000000..5b1e78bd4 --- /dev/null +++ b/Failed_subcircuits/LM310/LM310-cache.lib @@ -0,0 +1,165 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/Failed_subcircuits/LM310/LM310.cir b/Failed_subcircuits/LM310/LM310.cir new file mode 100644 index 000000000..bf32831f9 --- /dev/null +++ b/Failed_subcircuits/LM310/LM310.cir @@ -0,0 +1,45 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM310\LM310.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/29/22 23:09:57 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +R3 Net-_R1-Pad1_ Net-_J1-Pad1_ 500 +R4 Net-_J1-Pad1_ Net-_R4-Pad2_ 500 +R1 Net-_R1-Pad1_ Net-_Q4-Pad3_ 1k +R5 Net-_R4-Pad2_ Net-_Q5-Pad3_ 1k +Q4 Net-_Q3-Pad1_ Net-_Q4-Pad2_ Net-_Q4-Pad3_ eSim_PNP +Q5 Net-_Q4-Pad2_ Net-_Q4-Pad2_ Net-_Q5-Pad3_ eSim_PNP +Q9 Net-_C1-Pad1_ Net-_Q3-Pad1_ Net-_Q4-Pad2_ eSim_PNP +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p +Q14 Net-_C1-Pad1_ Net-_Q14-Pad2_ Net-_Q10-Pad1_ eSim_NPN +Q17 Net-_J1-Pad1_ Net-_C1-Pad1_ Net-_Q14-Pad2_ eSim_NPN +Q18 Net-_J1-Pad1_ Net-_Q14-Pad2_ Net-_D1-Pad2_ eSim_NPN +R12 Net-_Q14-Pad2_ Net-_D1-Pad2_ 3k +Q16 Net-_C1-Pad1_ Net-_D1-Pad2_ Net-_Q13-Pad1_ eSim_NPN +R13 Net-_D1-Pad2_ Net-_Q13-Pad1_ 25 +R10 Net-_C1-Pad2_ Net-_Q13-Pad1_ 5k +Q12 Net-_Q10-Pad1_ Net-_C1-Pad2_ Net-_Q10-Pad2_ eSim_NPN +R9 Net-_Q10-Pad2_ Net-_Q11-Pad1_ 200k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q7 Net-_D1-Pad2_ Net-_Q6-Pad3_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_NPN +R7 Net-_Q10-Pad3_ Net-_Q11-Pad3_ 150 +Q6 Net-_D1-Pad2_ Net-_D1-Pad1_ Net-_Q6-Pad3_ eSim_NPN +R6 Net-_Q6-Pad3_ Net-_Q11-Pad1_ 200k +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad1_ Net-_D1-Pad1_ eSim_NPN +Q8 Net-_Q11-Pad3_ Net-_J1-Pad3_ Net-_Q8-Pad3_ eSim_NPN +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n +Q3 Net-_Q3-Pad1_ Net-_J1-Pad3_ Net-_Q3-Pad3_ eSim_NPN +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad2_ eSim_NPN +R2 Net-_Q3-Pad3_ Net-_J1-Pad2_ 3k +R8 Net-_Q8-Pad3_ Net-_J1-Pad2_ 1.5k +Q15 Net-_Q13-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R11 Net-_Q15-Pad3_ Net-_J1-Pad2_ 200 +Q2 Net-_Q15-Pad2_ Net-_Q1-Pad1_ Net-_J1-Pad3_ eSim_PNP +U1 Net-_D1-Pad1_ Net-_R1-Pad1_ Net-_R4-Pad2_ Net-_Q15-Pad3_ Net-_J1-Pad2_ ? Net-_J1-Pad1_ Net-_Q13-Pad1_ PORT + +.end diff --git a/Failed_subcircuits/LM310/LM310.cir.out b/Failed_subcircuits/LM310/LM310.cir.out new file mode 100644 index 000000000..96a74e796 --- /dev/null +++ b/Failed_subcircuits/LM310/LM310.cir.out @@ -0,0 +1,50 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm310\lm310.cir + +.include NPN.lib +.include NJF.lib +.include PNP.lib +.include D.lib +r3 net-_r1-pad1_ net-_j1-pad1_ 500 +r4 net-_j1-pad1_ net-_r4-pad2_ 500 +r1 net-_r1-pad1_ net-_q4-pad3_ 1k +r5 net-_r4-pad2_ net-_q5-pad3_ 1k +q4 net-_q3-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A +q5 net-_q4-pad2_ net-_q4-pad2_ net-_q5-pad3_ Q2N2907A +q9 net-_c1-pad1_ net-_q3-pad1_ net-_q4-pad2_ Q2N2907A +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q10-pad1_ Q2N2222 +q17 net-_j1-pad1_ net-_c1-pad1_ net-_q14-pad2_ Q2N2222 +q18 net-_j1-pad1_ net-_q14-pad2_ net-_d1-pad2_ Q2N2222 +r12 net-_q14-pad2_ net-_d1-pad2_ 3k +q16 net-_c1-pad1_ net-_d1-pad2_ net-_q13-pad1_ Q2N2222 +r13 net-_d1-pad2_ net-_q13-pad1_ 25 +r10 net-_c1-pad2_ net-_q13-pad1_ 5k +q12 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +r9 net-_q10-pad2_ net-_q11-pad1_ 200k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q7 net-_d1-pad2_ net-_q6-pad3_ net-_q10-pad3_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222 +r7 net-_q10-pad3_ net-_q11-pad3_ 150 +q6 net-_d1-pad2_ net-_d1-pad1_ net-_q6-pad3_ Q2N2222 +r6 net-_q6-pad3_ net-_q11-pad1_ 200k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q13 net-_q13-pad1_ net-_q13-pad1_ net-_d1-pad1_ Q2N2222 +q8 net-_q11-pad3_ net-_j1-pad3_ net-_q8-pad3_ Q2N2222 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q3 net-_q3-pad1_ net-_j1-pad3_ net-_q3-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad2_ Q2N2222 +r2 net-_q3-pad3_ net-_j1-pad2_ 3k +r8 net-_q8-pad3_ net-_j1-pad2_ 1.5k +q15 net-_q13-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222 +r11 net-_q15-pad3_ net-_j1-pad2_ 200 +q2 net-_q15-pad2_ net-_q1-pad1_ net-_j1-pad3_ Q2N2907A +* u1 net-_d1-pad1_ net-_r1-pad1_ net-_r4-pad2_ net-_q15-pad3_ net-_j1-pad2_ ? net-_j1-pad1_ net-_q13-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/Failed_subcircuits/LM310/LM310.pro b/Failed_subcircuits/LM310/LM310.pro new file mode 100644 index 000000000..d7f78c3b4 --- /dev/null +++ b/Failed_subcircuits/LM310/LM310.pro @@ -0,0 +1,71 @@ +update=22/05/2015 07:44:53 +version=1 +last_client=kicad +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri diff --git a/Failed_subcircuits/LM310/LM310.sch b/Failed_subcircuits/LM310/LM310.sch new file mode 100644 index 000000000..f1bc5cbbd --- /dev/null +++ b/Failed_subcircuits/LM310/LM310.sch @@ -0,0 +1,711 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L resistor R3 +U 1 1 62E4163D +P 2300 1250 +F 0 "R3" H 2350 1380 50 0000 C CNN +F 1 "500" H 2350 1200 50 0000 C CNN +F 2 "" H 2350 1230 30 0000 C CNN +F 3 "" V 2350 1300 30 0000 C CNN + 1 2300 1250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 62E4163E +P 2900 1250 +F 0 "R4" H 2950 1380 50 0000 C CNN +F 1 "500" H 2950 1200 50 0000 C CNN +F 2 "" H 2950 1230 30 0000 C CNN +F 3 "" V 2950 1300 30 0000 C CNN + 1 2900 1250 + 1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 62E4163F +P 2050 1450 +F 0 "R1" H 2100 1580 50 0000 C CNN +F 1 "1k" H 2100 1400 50 0000 C CNN +F 2 "" H 2100 1430 30 0000 C CNN +F 3 "" V 2100 1500 30 0000 C CNN + 1 2050 1450 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 62E41640 +P 3200 1450 +F 0 "R5" H 3250 1580 50 0000 C CNN +F 1 "1k" H 3250 1400 50 0000 C CNN +F 2 "" H 3250 1430 30 0000 C CNN +F 3 "" V 3250 1500 30 0000 C CNN + 1 3200 1450 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 62E41641 +P 2200 1950 +F 0 "Q4" H 2100 2000 50 0000 R CNN +F 1 "eSim_PNP" H 2150 2100 50 0000 R CNN +F 2 "" H 2400 2050 29 0000 C CNN +F 3 "" H 2200 1950 60 0000 C CNN + 1 2200 1950 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 62E41642 +P 3150 1950 +F 0 "Q5" H 3050 2000 50 0000 R CNN +F 1 "eSim_PNP" H 3100 2100 50 0000 R CNN +F 2 "" H 3350 2050 29 0000 C CNN +F 3 "" H 3150 1950 60 0000 C CNN + 1 3150 1950 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 62E41643 +P 3700 2500 +F 0 "Q9" H 3600 2550 50 0000 R CNN +F 1 "eSim_PNP" H 3650 2650 50 0000 R CNN +F 2 "" H 3900 2600 29 0000 C CNN +F 3 "" H 3700 2500 60 0000 C CNN + 1 3700 2500 + 0 1 -1 0 +$EndComp +$Comp +L capacitor C1 +U 1 1 62E41644 +P 4750 2800 +F 0 "C1" H 4775 2900 50 0000 L CNN +F 1 "10p" H 4775 2700 50 0000 L CNN +F 2 "" H 4788 2650 30 0000 C CNN +F 3 "" H 4750 2800 60 0000 C CNN + 1 4750 2800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q14 +U 1 1 62E41645 +P 5300 2700 +F 0 "Q14" H 5200 2750 50 0000 R CNN +F 1 "eSim_NPN" H 5250 2850 50 0000 R CNN +F 2 "" H 5500 2800 29 0000 C CNN +F 3 "" H 5300 2700 60 0000 C CNN + 1 5300 2700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q17 +U 1 1 62E41646 +P 6050 2400 +F 0 "Q17" H 5950 2450 50 0000 R CNN +F 1 "eSim_NPN" H 6000 2550 50 0000 R CNN +F 2 "" H 6250 2500 29 0000 C CNN +F 3 "" H 6050 2400 60 0000 C CNN + 1 6050 2400 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 62E41647 +P 6700 2700 +F 0 "Q18" H 6600 2750 50 0000 R CNN +F 1 "eSim_NPN" H 6650 2850 50 0000 R CNN +F 2 "" H 6900 2800 29 0000 C CNN +F 3 "" H 6700 2700 60 0000 C CNN + 1 6700 2700 + 1 0 0 -1 +$EndComp +$Comp +L resistor R12 +U 1 1 62E41648 +P 6100 2950 +F 0 "R12" H 6150 3080 50 0000 C CNN +F 1 "3k" H 6150 2900 50 0000 C CNN +F 2 "" H 6150 2930 30 0000 C CNN +F 3 "" V 6150 3000 30 0000 C CNN + 1 6100 2950 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q16 +U 1 1 62E41649 +P 5800 3600 +F 0 "Q16" H 5700 3650 50 0000 R CNN +F 1 "eSim_NPN" H 5750 3750 50 0000 R CNN +F 2 "" H 6000 3700 29 0000 C CNN +F 3 "" H 5800 3600 60 0000 C CNN + 1 5800 3600 + -1 0 0 -1 +$EndComp +$Comp +L resistor R13 +U 1 1 62E4164A +P 6100 3800 +F 0 "R13" H 6150 3930 50 0000 C CNN +F 1 "25" H 6150 3750 50 0000 C CNN +F 2 "" H 6150 3780 30 0000 C CNN +F 3 "" V 6150 3850 30 0000 C CNN + 1 6100 3800 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 62E4164B +P 5200 4150 +F 0 "R10" H 5250 4280 50 0000 C CNN +F 1 "5k" H 5250 4100 50 0000 C CNN +F 2 "" H 5250 4130 30 0000 C CNN +F 3 "" V 5250 4200 30 0000 C CNN + 1 5200 4150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 62E4164C +P 4300 4100 +F 0 "Q12" H 4200 4150 50 0000 R CNN +F 1 "eSim_NPN" H 4250 4250 50 0000 R CNN +F 2 "" H 4500 4200 29 0000 C CNN +F 3 "" H 4300 4100 60 0000 C CNN + 1 4300 4100 + -1 0 0 -1 +$EndComp +$Comp +L resistor R9 +U 1 1 62E4164D +P 4150 4550 +F 0 "R9" H 4200 4680 50 0000 C CNN +F 1 "200k" H 4200 4500 50 0000 C CNN +F 2 "" H 4200 4530 30 0000 C CNN +F 3 "" V 4200 4600 30 0000 C CNN + 1 4150 4550 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 62E4164E +P 3900 4350 +F 0 "Q10" H 3800 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4500 50 0000 R CNN +F 2 "" H 4100 4450 29 0000 C CNN +F 3 "" H 3900 4350 60 0000 C CNN + 1 3900 4350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q7 +U 1 1 62E4164F +P 3450 4350 +F 0 "Q7" H 3350 4400 50 0000 R CNN +F 1 "eSim_NPN" H 3400 4500 50 0000 R CNN +F 2 "" H 3650 4450 29 0000 C CNN +F 3 "" H 3450 4350 60 0000 C CNN + 1 3450 4350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 62E41650 +P 4100 5150 +F 0 "Q11" H 4000 5200 50 0000 R CNN +F 1 "eSim_NPN" H 4050 5300 50 0000 R CNN +F 2 "" H 4300 5250 29 0000 C CNN +F 3 "" H 4100 5150 60 0000 C CNN + 1 4100 5150 + 1 0 0 -1 +$EndComp +$Comp +L resistor R7 +U 1 1 62E41651 +P 3500 5050 +F 0 "R7" H 3550 5180 50 0000 C CNN +F 1 "150" H 3550 5000 50 0000 C CNN +F 2 "" H 3550 5030 30 0000 C CNN +F 3 "" V 3550 5100 30 0000 C CNN + 1 3500 5050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 62E41652 +P 3150 3950 +F 0 "Q6" H 3050 4000 50 0000 R CNN +F 1 "eSim_NPN" H 3100 4100 50 0000 R CNN +F 2 "" H 3350 4050 29 0000 C CNN +F 3 "" H 3150 3950 60 0000 C CNN + 1 3150 3950 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 62E41653 +P 3200 4600 +F 0 "R6" H 3250 4730 50 0000 C CNN +F 1 "200k" H 3250 4550 50 0000 C CNN +F 2 "" H 3250 4580 30 0000 C CNN +F 3 "" V 3250 4650 30 0000 C CNN + 1 3200 4600 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 62E41654 +P 2850 3250 +F 0 "D1" H 2850 3350 50 0000 C CNN +F 1 "eSim_Diode" H 2850 3150 50 0000 C CNN +F 2 "" H 2850 3250 60 0000 C CNN +F 3 "" H 2850 3250 60 0000 C CNN + 1 2850 3250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 62E41655 +P 4500 5700 +F 0 "Q13" H 4400 5750 50 0000 R CNN +F 1 "eSim_NPN" H 4450 5850 50 0000 R CNN +F 2 "" H 4700 5800 29 0000 C CNN +F 3 "" H 4500 5700 60 0000 C CNN + 1 4500 5700 + 0 1 -1 0 +$EndComp +Wire Wire Line + 2500 1200 2800 1200 +Wire Wire Line + 2650 1200 2650 950 +Connection ~ 2650 950 +Connection ~ 2650 1200 +Wire Wire Line + 2200 1200 2100 1200 +Wire Wire Line + 2100 700 2100 1350 +Wire Wire Line + 3100 1200 3250 1200 +Wire Wire Line + 3250 700 3250 1350 +Connection ~ 3250 1200 +Connection ~ 2100 1200 +Wire Wire Line + 2100 1750 2100 1650 +Wire Wire Line + 3250 1750 3250 1650 +Wire Wire Line + 2400 1950 2950 1950 +Wire Wire Line + 2850 1950 2850 2250 +Wire Wire Line + 2850 2250 3250 2250 +Wire Wire Line + 3250 2150 3250 2400 +Wire Wire Line + 3250 2400 3500 2400 +Connection ~ 3250 2250 +Wire Wire Line + 3900 2400 5850 2400 +Connection ~ 4750 2400 +Wire Wire Line + 4750 2650 4750 2400 +Connection ~ 5200 2400 +Wire Wire Line + 5200 2500 5200 2400 +Wire Wire Line + 6150 2600 6150 2850 +Wire Wire Line + 5500 2700 6500 2700 +Connection ~ 6150 2700 +Wire Wire Line + 6150 950 6150 2200 +Connection ~ 6150 950 +Wire Wire Line + 6800 950 6800 2500 +Connection ~ 6800 950 +Wire Wire Line + 6150 3150 6150 3700 +Wire Wire Line + 3000 3250 6800 3250 +Wire Wire Line + 6800 3250 6800 2900 +Wire Wire Line + 5700 2400 5700 3400 +Connection ~ 5700 2400 +Wire Wire Line + 6150 3600 6000 3600 +Connection ~ 6150 3250 +Connection ~ 6150 3600 +Wire Wire Line + 5700 3800 5700 6400 +Wire Wire Line + 5400 4100 7150 4100 +Wire Wire Line + 6150 4100 6150 4000 +Connection ~ 6150 4100 +Connection ~ 5700 4100 +Wire Wire Line + 4500 4100 5100 4100 +Wire Wire Line + 4750 2950 4750 4100 +Wire Wire Line + 5200 3750 5200 2900 +Wire Wire Line + 3800 3750 5200 3750 +Wire Wire Line + 4200 3750 4200 3900 +Connection ~ 4750 4100 +Wire Wire Line + 4200 4300 4200 4450 +Wire Wire Line + 4200 4350 4100 4350 +Connection ~ 4200 4350 +Wire Wire Line + 3800 3750 3800 4150 +Connection ~ 4200 3750 +Wire Wire Line + 3550 3250 3550 4150 +Wire Wire Line + 3550 4700 3800 4700 +Wire Wire Line + 3550 4550 3550 4950 +Wire Wire Line + 3800 4700 3800 4550 +Wire Wire Line + 4200 4750 4200 4950 +Wire Wire Line + 3250 4900 4200 4900 +Wire Wire Line + 3900 4900 3900 5150 +Wire Wire Line + 2100 2150 2100 5950 +Wire Wire Line + 2100 2800 3700 2800 +Wire Wire Line + 3700 2800 3700 2700 +Connection ~ 3550 4700 +Wire Wire Line + 3550 5250 3550 5700 +Wire Wire Line + 3550 5400 4200 5400 +Wire Wire Line + 4200 5400 4200 5350 +Connection ~ 3900 4900 +Wire Wire Line + 3250 4150 3250 4500 +Connection ~ 3250 4350 +Wire Wire Line + 3250 4800 3250 4900 +Wire Wire Line + 3250 3250 3250 3750 +Connection ~ 3550 3250 +Connection ~ 3250 3250 +Wire Wire Line + 2700 3250 2450 3250 +Wire Wire Line + 2450 3250 2450 5600 +Wire Wire Line + 1200 3950 2950 3950 +Connection ~ 2450 3950 +Connection ~ 4200 4900 +Wire Wire Line + 4700 5600 5700 5600 +Wire Wire Line + 2450 5600 4300 5600 +Connection ~ 3550 5400 +$Comp +L eSim_NPN Q8 +U 1 1 62E41656 +P 3450 5900 +F 0 "Q8" H 3350 5950 50 0000 R CNN +F 1 "eSim_NPN" H 3400 6050 50 0000 R CNN +F 2 "" H 3650 6000 29 0000 C CNN +F 3 "" H 3450 5900 60 0000 C CNN + 1 3450 5900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4500 5900 4800 5900 +Wire Wire Line + 4800 5900 4800 5600 +Connection ~ 4800 5600 +Wire Wire Line + 1600 950 1600 5450 +$Comp +L jfet_n J1 +U 1 1 62E41657 +P 1500 5650 +F 0 "J1" H 1400 5700 50 0000 R CNN +F 1 "jfet_n" H 1450 5800 50 0000 R CNN +F 2 "" H 1700 5750 29 0000 C CNN +F 3 "" H 1500 5650 60 0000 C CNN + 1 1500 5650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1600 5850 1600 6200 +Wire Wire Line + 1600 5900 3250 5900 +Wire Wire Line + 1600 950 7150 950 +Connection ~ 2100 2800 +$Comp +L eSim_NPN Q3 +U 1 1 62E41658 +P 2000 6150 +F 0 "Q3" H 1900 6200 50 0000 R CNN +F 1 "eSim_NPN" H 1950 6300 50 0000 R CNN +F 2 "" H 2200 6250 29 0000 C CNN +F 3 "" H 2000 6150 60 0000 C CNN + 1 2000 6150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1600 6150 1800 6150 +Connection ~ 1600 5900 +Connection ~ 1600 6150 +$Comp +L eSim_NPN Q1 +U 1 1 62E41659 +P 1100 6600 +F 0 "Q1" H 1000 6650 50 0000 R CNN +F 1 "eSim_NPN" H 1050 6750 50 0000 R CNN +F 2 "" H 1300 6700 29 0000 C CNN +F 3 "" H 1100 6600 60 0000 C CNN + 1 1100 6600 + 1 0 0 -1 +$EndComp +Wire Wire Line + 900 6400 1300 6400 +Wire Wire Line + 900 6400 900 6600 +Connection ~ 1200 6400 +Wire Wire Line + 1200 6800 1200 7350 +Wire Wire Line + 1300 5650 650 5650 +Wire Wire Line + 650 5650 650 7350 +Wire Wire Line + 650 7350 6600 7350 +$Comp +L resistor R2 +U 1 1 62E4165A +P 2050 6950 +F 0 "R2" H 2100 7080 50 0000 C CNN +F 1 "3k" H 2100 6900 50 0000 C CNN +F 2 "" H 2100 6930 30 0000 C CNN +F 3 "" V 2100 7000 30 0000 C CNN + 1 2050 6950 + 0 1 1 0 +$EndComp +Wire Wire Line + 2100 6350 2100 6850 +Connection ~ 1200 7350 +Wire Wire Line + 2100 7150 2100 7350 +Connection ~ 2100 7350 +Wire Wire Line + 1600 6600 5400 6600 +$Comp +L resistor R8 +U 1 1 62E4165B +P 3500 6900 +F 0 "R8" H 3550 7030 50 0000 C CNN +F 1 "1.5k" H 3550 6850 50 0000 C CNN +F 2 "" H 3550 6880 30 0000 C CNN +F 3 "" V 3550 6950 30 0000 C CNN + 1 3500 6900 + 0 1 1 0 +$EndComp +Wire Wire Line + 3550 6100 3550 6800 +Wire Wire Line + 3550 7100 3550 7350 +Connection ~ 3550 7350 +$Comp +L eSim_NPN Q15 +U 1 1 62E4165C +P 5600 6600 +F 0 "Q15" H 5500 6650 50 0000 R CNN +F 1 "eSim_NPN" H 5550 6750 50 0000 R CNN +F 2 "" H 5800 6700 29 0000 C CNN +F 3 "" H 5600 6600 60 0000 C CNN + 1 5600 6600 + 1 0 0 -1 +$EndComp +Connection ~ 5700 5600 +$Comp +L resistor R11 +U 1 1 62E4165D +P 5650 7050 +F 0 "R11" H 5700 7180 50 0000 C CNN +F 1 "200" H 5700 7000 50 0000 C CNN +F 2 "" H 5700 7030 30 0000 C CNN +F 3 "" V 5700 7100 30 0000 C CNN + 1 5650 7050 + 0 1 1 0 +$EndComp +Wire Wire Line + 5700 6800 5700 6950 +Wire Wire Line + 5700 7250 5700 7350 +Connection ~ 5700 7350 +Wire Wire Line + 5700 6900 6600 6900 +Connection ~ 5700 6900 +$Comp +L eSim_PNP Q2 +U 1 1 62E4165E +P 1500 6400 +F 0 "Q2" H 1400 6450 50 0000 R CNN +F 1 "eSim_PNP" H 1450 6550 50 0000 R CNN +F 2 "" H 1700 6500 29 0000 C CNN +F 3 "" H 1500 6400 60 0000 C CNN + 1 1500 6400 + 1 0 0 1 +$EndComp +Connection ~ 2850 1950 +$Comp +L PORT U1 +U 3 1 62E4165F +P 3500 700 +F 0 "U1" H 3550 800 30 0000 C CNN +F 1 "PORT" H 3500 700 30 0000 C CNN +F 2 "" H 3500 700 60 0000 C CNN +F 3 "" H 3500 700 60 0000 C CNN + 3 3500 700 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 2 1 62E41660 +P 1850 700 +F 0 "U1" H 1900 800 30 0000 C CNN +F 1 "PORT" H 1850 700 30 0000 C CNN +F 2 "" H 1850 700 60 0000 C CNN +F 3 "" H 1850 700 60 0000 C CNN + 2 1850 700 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 62E41661 +P 7400 950 +F 0 "U1" H 7450 1050 30 0000 C CNN +F 1 "PORT" H 7400 950 30 0000 C CNN +F 2 "" H 7400 950 60 0000 C CNN +F 3 "" H 7400 950 60 0000 C CNN + 7 7400 950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 1 1 62E41662 +P 1200 3700 +F 0 "U1" H 1250 3800 30 0000 C CNN +F 1 "PORT" H 1200 3700 30 0000 C CNN +F 2 "" H 1200 3700 60 0000 C CNN +F 3 "" H 1200 3700 60 0000 C CNN + 1 1200 3700 + 0 1 1 0 +$EndComp +$Comp +L PORT U1 +U 8 1 62E41663 +P 7400 4100 +F 0 "U1" H 7450 4200 30 0000 C CNN +F 1 "PORT" H 7400 4100 30 0000 C CNN +F 2 "" H 7400 4100 60 0000 C CNN +F 3 "" H 7400 4100 60 0000 C CNN + 8 7400 4100 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62E41664 +P 6850 6900 +F 0 "U1" H 6900 7000 30 0000 C CNN +F 1 "PORT" H 6850 6900 30 0000 C CNN +F 2 "" H 6850 6900 60 0000 C CNN +F 3 "" H 6850 6900 60 0000 C CNN + 4 6850 6900 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62E41665 +P 6850 7350 +F 0 "U1" H 6900 7450 30 0000 C CNN +F 1 "PORT" H 6850 7350 30 0000 C CNN +F 2 "" H 6850 7350 60 0000 C CNN +F 3 "" H 6850 7350 60 0000 C CNN + 5 6850 7350 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 6 1 62E41666 +P 6900 5450 +F 0 "U1" H 6950 5550 30 0000 C CNN +F 1 "PORT" H 6900 5450 30 0000 C CNN +F 2 "" H 6900 5450 60 0000 C CNN +F 3 "" H 6900 5450 60 0000 C CNN + 6 6900 5450 + -1 0 0 1 +$EndComp +NoConn ~ 6650 5450 +$EndSCHEMATC diff --git a/Failed_subcircuits/LM310/LM310.sub b/Failed_subcircuits/LM310/LM310.sub new file mode 100644 index 000000000..77bd9030d --- /dev/null +++ b/Failed_subcircuits/LM310/LM310.sub @@ -0,0 +1,44 @@ +* Subcircuit LM310 +.subckt LM310 net-_d1-pad1_ net-_r1-pad1_ net-_r4-pad2_ net-_q15-pad3_ net-_j1-pad2_ ? net-_j1-pad1_ net-_q13-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\lm310\lm310.cir +.include NPN.lib +.include NJF.lib +.include PNP.lib +.include D.lib +r3 net-_r1-pad1_ net-_j1-pad1_ 500 +r4 net-_j1-pad1_ net-_r4-pad2_ 500 +r1 net-_r1-pad1_ net-_q4-pad3_ 1k +r5 net-_r4-pad2_ net-_q5-pad3_ 1k +q4 net-_q3-pad1_ net-_q4-pad2_ net-_q4-pad3_ Q2N2907A +q5 net-_q4-pad2_ net-_q4-pad2_ net-_q5-pad3_ Q2N2907A +q9 net-_c1-pad1_ net-_q3-pad1_ net-_q4-pad2_ Q2N2907A +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +q14 net-_c1-pad1_ net-_q14-pad2_ net-_q10-pad1_ Q2N2222 +q17 net-_j1-pad1_ net-_c1-pad1_ net-_q14-pad2_ Q2N2222 +q18 net-_j1-pad1_ net-_q14-pad2_ net-_d1-pad2_ Q2N2222 +r12 net-_q14-pad2_ net-_d1-pad2_ 3k +q16 net-_c1-pad1_ net-_d1-pad2_ net-_q13-pad1_ Q2N2222 +r13 net-_d1-pad2_ net-_q13-pad1_ 25 +r10 net-_c1-pad2_ net-_q13-pad1_ 5k +q12 net-_q10-pad1_ net-_c1-pad2_ net-_q10-pad2_ Q2N2222 +r9 net-_q10-pad2_ net-_q11-pad1_ 200k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q7 net-_d1-pad2_ net-_q6-pad3_ net-_q10-pad3_ Q2N2222 +q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2222 +r7 net-_q10-pad3_ net-_q11-pad3_ 150 +q6 net-_d1-pad2_ net-_d1-pad1_ net-_q6-pad3_ Q2N2222 +r6 net-_q6-pad3_ net-_q11-pad1_ 200k +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q13 net-_q13-pad1_ net-_q13-pad1_ net-_d1-pad1_ Q2N2222 +q8 net-_q11-pad3_ net-_j1-pad3_ net-_q8-pad3_ Q2N2222 +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q3 net-_q3-pad1_ net-_j1-pad3_ net-_q3-pad3_ Q2N2222 +q1 net-_q1-pad1_ net-_q1-pad1_ net-_j1-pad2_ Q2N2222 +r2 net-_q3-pad3_ net-_j1-pad2_ 3k +r8 net-_q8-pad3_ net-_j1-pad2_ 1.5k +q15 net-_q13-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222 +r11 net-_q15-pad3_ net-_j1-pad2_ 200 +q2 net-_q15-pad2_ net-_q1-pad1_ net-_j1-pad3_ Q2N2907A +* Control Statements + +.ends LM310 \ No newline at end of file diff --git a/Failed_subcircuits/LM310/LM310_Previous_Values.xml b/Failed_subcircuits/LM310/LM310_Previous_Values.xml new file mode 100644 index 000000000..cc0a54d48 --- /dev/null +++ b/Failed_subcircuits/LM310/LM310_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib \ No newline at end of file diff --git a/Failed_subcircuits/LM310/NJF.lib b/Failed_subcircuits/LM310/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/Failed_subcircuits/LM310/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/Failed_subcircuits/LM310/NPN.lib b/Failed_subcircuits/LM310/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/Failed_subcircuits/LM310/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/Failed_subcircuits/LM310/PNP.lib b/Failed_subcircuits/LM310/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/Failed_subcircuits/LM310/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/Failed_subcircuits/LM310/README.md b/Failed_subcircuits/LM310/README.md new file mode 100644 index 000000000..489ca16c0 --- /dev/null +++ b/Failed_subcircuits/LM310/README.md @@ -0,0 +1,37 @@ + +# LM310 Voltage Follower IC + +The LM310 is a Voltage Follwer IC obtained by internally connecting an operational amplifier with unity gain as in a non inverting amplifier. + + +## Usage/Examples + +Low Pass Active Filter + +High Pass Active Filter + +BandPass/Notch Filter + +Simulated Inductor + +Sample Holds + + +## Documentation + +To know the details of LM310 IC please refer to this link [LM310_datasheet.](https://www.farnell.com/datasheets/105178.pdf) + +## Error Observed + +According to the Frequency response,the HPF using LM310 as mentioned in its datasheet is working fine. But the LPF as mentioned in the datasheet is behaving as HPF with the expected cutoff frequency. If I exchange the capacitors with the resistors, then I am obtaining the desired LPF response, but then I have changed the LPF circuit which is mentioned in the datasheet. I don't know if its an error in this circuit itself or possibly an error in the test circuit given in datasheet. + +## Possible Solution + +The designer is suggested to check and test this circuit with different model files and verify the output. Also the designer may re-verify the subcircuit and the test circuits of the IC in accordance with the datasheet. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 \ No newline at end of file diff --git a/Failed_subcircuits/LM310/analysis b/Failed_subcircuits/LM310/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/Failed_subcircuits/LM310/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/eSim_Subckt.lib b/eSim_Subckt.lib new file mode 100644 index 000000000..076b3daf6 --- /dev/null +++ b/eSim_Subckt.lib @@ -0,0 +1,1085 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# 10bitDAC +# +DEF 10bitDAC X 0 40 Y Y 1 F N +F0 "X" 0 50 60 H V C CNN +F1 "10bitDAC" -50 -50 60 H V C CNN +F2 "" 0 50 60 H I C CNN +F3 "" 0 50 60 H I C CNN +DRAW +S -500 500 400 -600 0 1 0 N +X D0 1 -700 -500 200 R 50 50 1 1 I +X D1 2 -700 -400 200 R 50 50 1 1 I +X D2 3 -700 -300 200 R 50 50 1 1 I +X D3 4 -700 -200 200 R 50 50 1 1 I +X D4 5 -700 -100 200 R 50 50 1 1 I +X D5 6 -700 0 200 R 50 50 1 1 I +X D6 7 -700 100 200 R 50 50 1 1 I +X D7 8 -700 200 200 R 50 50 1 1 I +X D8 9 -700 300 200 R 50 50 1 1 I +X D9 10 -700 400 200 R 50 50 1 1 I +X AnalogOut 11 600 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 2BITMUL +# +DEF 2BITMUL X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "2BITMUL" 0 0 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A0 1 -500 300 200 R 50 50 1 1 I +X A1 2 -500 150 200 R 50 50 1 1 I +X B0 3 -500 -50 200 R 50 50 1 1 I +X B1 4 -500 -250 200 R 50 50 1 1 I +X M0 5 500 250 200 L 50 50 1 1 O +X M1 6 500 100 200 L 50 50 1 1 O +X M2 7 500 -50 200 L 50 50 1 1 O +X M3 8 500 -250 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 3_and +# +DEF 3_and X 0 40 Y Y 1 F N +F0 "X" 100 -50 60 H V C CNN +F1 "3_and" 150 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 150 50 158 716 -716 0 1 0 N 200 200 200 -100 +P 2 0 1 0 -150 200 200 200 N +P 3 0 1 0 -150 200 -150 -100 200 -100 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X out 4 500 50 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_OR +# +DEF 4_OR X 0 40 Y Y 1 F N +F0 "X" 150 -100 60 H V C CNN +F1 "4_OR" 150 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A -800 0 650 226 -226 0 1 0 N -200 250 -200 -250 +A -73 134 444 -599 -176 0 1 0 N 150 -250 350 0 +A -30 -99 393 627 146 0 1 0 N 150 250 350 0 +P 2 0 1 0 -200 -250 150 -250 N +P 2 0 1 0 -200 250 150 250 N +X in1 1 -350 150 200 R 50 50 1 1 I +X in2 2 -350 50 200 R 50 50 1 1 I +X in3 3 -350 -50 200 R 50 50 1 1 I +X in4 4 -350 -150 200 R 50 50 1 1 I +X out 5 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 4_and +# +DEF 4_and X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "4_and" 100 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 206 760 -760 0 1 0 N 150 200 150 -200 +P 2 0 1 0 -200 200 150 200 N +P 4 0 1 0 -200 200 -200 -200 50 -200 150 -200 N +X in1 1 -400 150 200 R 50 50 1 1 I +X in2 2 -400 50 200 R 50 50 1 1 I +X in3 3 -400 -50 200 R 50 50 1 1 I +X in4 4 -400 -150 200 R 50 50 1 1 I +X out 5 500 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# 556 +# +DEF 556 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "556" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 250 -550 0 1 0 N +X dis1 1 -500 150 200 R 50 50 1 1 I +X thr1 2 -500 -150 200 R 50 50 1 1 I +X cv1 3 -150 -750 200 U 50 50 1 1 I +X rst1 4 -200 600 200 D 50 50 1 1 I +X out1 5 -500 0 200 R 50 50 1 1 O +X trig1 6 -500 -300 200 R 50 50 1 1 I +X gnd 7 0 -750 200 U 50 50 1 1 I +X trig2 8 450 -300 200 L 50 50 1 1 I +X out2 9 450 0 200 L 50 50 1 1 O +X rst2 10 100 600 200 D 50 50 1 1 I +X cv2 11 150 -750 200 U 50 50 1 1 I +X thr2 12 450 -150 200 L 50 50 1 1 I +X dis2 13 450 150 200 L 50 50 1 1 I +X vcc 14 -50 600 200 D 50 50 1 1 I +ENDDRAW +ENDDEF +# +# 5_and +# +DEF 5_and X 0 40 Y Y 1 F N +F0 "X" 50 -100 60 H V C CNN +F1 "5_and" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 100 0 255 787 -787 0 1 0 N 150 250 150 -250 +P 2 0 1 0 -250 250 150 250 N +P 3 0 1 0 -250 250 -250 -250 150 -250 N +X in1 1 -450 200 200 R 50 50 1 1 I +X in2 2 -450 100 200 R 50 50 1 1 I +X in3 3 -450 0 200 R 50 50 1 1 I +X in4 4 -450 -100 200 R 50 50 1 1 I +X in5 5 -450 -200 200 R 50 50 1 1 I +X out 6 550 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# CMOS_NAND +# +DEF CMOS_NAND X 0 40 Y Y 1 F N +F0 "X" -100 -150 60 H V C CNN +F1 "CMOS_NAND" 0 -50 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +A 150 -50 381 668 -668 0 1 0 N 300 300 300 -400 +C 550 0 50 0 1 0 N +P 2 0 1 0 -350 300 300 300 N +P 3 0 1 0 -350 300 -350 -400 300 -400 N +X in1 1 -550 250 200 R 50 50 1 1 I +X in2 2 -550 -300 200 R 50 50 1 1 I +X out 3 800 0 279 L 79 79 1 1 I +ENDDRAW +ENDDEF +# +# Clock_pulse_generator +# +DEF Clock_pulse_generator X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "Clock_pulse_generator" 0 -100 60 H V C CNN +F2 "" 0 0 60 H I C CNN +F3 "" 0 0 60 H I C CNN +DRAW +S -550 200 600 -300 0 1 0 N +X Vdd 1 -750 100 200 R 50 50 1 1 I +X R 2 -750 -50 200 R 50 50 1 1 I +X C 3 -750 -200 200 R 50 50 1 1 I +X Clkout 4 800 0 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# ICL8038 +# +DEF ICL8038 X 0 40 N Y 1 F N +F0 "X" 0 200 60 H V C CNN +F1 "ICL8038" 0 -100 60 V V C CNN +F2 "" 0 200 60 H I C CNN +F3 "" 0 200 60 H I C CNN +DRAW +A 0 400 50 -1799 -1 0 1 0 N -50 400 50 400 +S -300 400 300 -400 0 1 0 N +X 9 1 500 -200 200 L 50 50 1 1 O +X 7 2 -500 -300 200 R 50 50 1 1 I +X 8 3 500 -300 200 L 50 50 1 1 I +X 5 4 -500 -100 200 R 50 50 1 1 I +X 4 5 -500 0 200 R 50 50 1 1 I +X 10 6 500 -100 200 L 50 50 1 1 I +X 11 7 500 0 200 L 50 50 1 1 I +X 3 8 -500 100 200 R 50 50 1 1 O +X 2 9 -500 200 200 R 50 50 1 1 O +X 6 10 -500 -200 200 R 50 50 1 1 I +X 1 11 -500 300 200 R 50 50 1 1 I +X 12 12 500 100 200 L 50 50 1 1 I +X 13 13 500 200 200 L 50 50 1 1 N +X 14 14 500 300 200 L 50 50 1 1 N +ENDDRAW +ENDDEF +# +# IC_4002 +# +DEF IC_4002 X 0 40 Y Y 1 F N +F0 "X" 0 150 60 H V C CNN +F1 "IC_4002" 0 0 60 H V C CNN +F2 "" 50 -150 60 H V C CNN +F3 "" 50 -150 60 H V C CNN +DRAW +S -250 350 250 -400 0 1 0 N +X 1Y 1 -450 250 200 R 50 50 1 1 O +X 1A 2 -450 150 200 R 50 50 1 1 I +X 1B 3 -450 50 200 R 50 50 1 1 I +X 1C 4 -450 -50 200 R 50 50 1 1 I +X 1D 5 -450 -150 200 R 50 50 1 1 I +X NC 6 -450 -250 200 R 50 50 1 1 I +X GND 7 -450 -350 200 R 50 50 1 1 I +X NC 8 450 -350 200 L 50 50 1 1 I +X 2A 9 450 -250 200 L 50 50 1 1 I +X 2B 10 450 -150 200 L 50 50 1 1 I +X 2C 11 450 -50 200 L 50 50 1 1 I +X 2D 12 450 50 200 L 50 50 1 1 I +X 2Y 13 450 150 200 L 50 50 1 1 O +X VCC 14 450 250 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4012 +# +DEF IC_4012 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4012" 0 200 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 350 -400 0 1 0 N +X Q1 1 -500 300 200 R 50 50 1 1 O +X A1 2 -500 200 200 R 50 50 1 1 I +X B1 3 -500 100 200 R 50 50 1 1 I +X C1 4 -500 0 200 R 50 50 1 1 I +X D1 5 -500 -100 200 R 50 50 1 1 I +X NC 6 -500 -200 200 R 50 50 1 1 N +X VSS 7 -500 -300 200 R 50 50 1 1 I +X NC 8 550 -300 200 L 50 50 1 1 N +X A2 9 550 -200 200 L 50 50 1 1 I +X B2 10 550 -100 200 L 50 50 1 1 I +X C2 11 550 0 200 L 50 50 1 1 I +X D2 12 550 100 200 L 50 50 1 1 I +X Q2 13 550 200 200 L 50 50 1 1 O +X VDD 14 550 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4017 +# +DEF IC_4017 X 0 40 Y Y 1 F N +F0 "X" 0 0 60 H V C CNN +F1 "IC_4017" 0 0 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -350 850 400 -850 0 1 0 N +X 1 1 600 650 200 L 50 50 1 1 O +X 2 2 600 500 200 L 50 50 1 1 O +X 3 3 600 350 200 L 50 50 1 1 O +X 4 4 600 200 200 L 50 50 1 1 O +X 5 5 600 50 200 L 50 50 1 1 O +X 6 6 600 -100 200 L 50 50 1 1 O +X 7 7 600 -250 200 L 50 50 1 1 O +X 8 8 600 -400 200 L 50 50 1 1 O +X 9 9 600 -600 200 L 50 50 1 1 O +X 10 10 600 -750 200 L 50 50 1 1 O +X RST 11 -550 -400 200 R 50 50 1 1 I +X CLK 12 -550 350 200 R 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4023 +# +DEF IC_4023 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4023" 0 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X C3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X A3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_4028 +# +DEF IC_4028 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4028" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 450 300 -450 0 1 0 N +X Q4 1 -500 350 200 R 50 50 1 1 O +X Q2 2 -500 250 200 R 50 50 1 1 O +X Q0 3 -500 150 200 R 50 50 1 1 O +X Q7 4 -500 50 200 R 50 50 1 1 O +X Q9 5 -500 -50 200 R 50 50 1 1 O +X Q5 6 -500 -150 200 R 50 50 1 1 O +X Q6 7 -500 -250 200 R 50 50 1 1 O +X Vss 8 -500 -350 200 R 50 50 1 1 I +X Q8 9 500 -350 200 L 50 50 1 1 O +X A0 10 500 -250 200 L 50 50 1 1 I +X A3 11 500 -150 200 L 50 50 1 1 I +X A2 12 500 -50 200 L 50 50 1 1 I +X A1 13 500 50 200 L 50 50 1 1 I +X Q1 14 500 150 200 L 50 50 1 1 O +X Q3 15 500 250 200 L 50 50 1 1 O +X Vdd 16 500 350 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_4073 +# +DEF IC_4073 X 0 40 Y Y 1 F N +F0 "X" 0 -100 60 H V C CNN +F1 "IC_4073" 0 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +S -300 400 300 -400 0 1 0 N +X A1 1 -500 300 200 R 50 50 1 1 I +X B1 2 -500 200 200 R 50 50 1 1 I +X A2 3 -500 100 200 R 50 50 1 1 I +X B2 4 -500 0 200 R 50 50 1 1 I +X C2 5 -500 -100 200 R 50 50 1 1 I +X Q2 6 -500 -200 200 R 50 50 1 1 O +X Vss 7 -500 -300 200 R 50 50 1 1 I +X C1 8 500 -300 200 L 50 50 1 1 I +X Q1 9 500 -200 200 L 50 50 1 1 O +X Q3 10 500 -100 200 L 50 50 1 1 O +X A3 11 500 0 200 L 50 50 1 1 I +X B3 12 500 100 200 L 50 50 1 1 I +X C3 13 500 200 200 L 50 50 1 1 I +X Vdd 14 500 300 200 L 50 50 1 1 I +ENDDRAW +ENDDEF +# +# IC_74153 +# +DEF IC_74153 X 0 40 Y Y 1 F N +F0 "X" 100 50 60 H V C CNN +F1 "IC_74153" 100 150 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 100 -200 60 0 0 0 4:1 Normal 0 C C +T 0 100 -100 60 0 0 0 DUAL Normal 0 C C +T 0 100 -300 60 0 0 0 MUX Normal 0 C C +S -200 500 350 -550 0 1 0 N +X a0 1 -400 350 200 R 50 50 1 1 I +X a1 2 -400 250 200 R 50 50 1 1 I +X a2 3 -400 150 200 R 50 50 1 1 I +X a3 4 -400 50 200 R 50 50 1 1 I +X EA 5 0 700 200 D 50 50 1 1 I I +X b0 6 -400 -150 200 R 50 50 1 1 I +X b1 7 -400 -250 200 R 50 50 1 1 I +X b2 8 -400 -350 200 R 50 50 1 1 I +X b3 9 -400 -450 200 R 50 50 1 1 I +X EB 10 200 700 200 D 50 50 1 1 I I +X s1 11 50 -750 200 U 50 50 1 1 I +X s0 12 150 -750 200 U 50 50 1 1 I +X ya 13 550 250 200 L 50 50 1 1 O +X yb 14 550 -300 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_74154 +# +DEF IC_74154 X 0 40 Y Y 1 F N +F0 "X" 0 -200 60 H V C CNN +F1 "IC_74154" 50 -50 60 H V C CNN +F2 "" 0 50 60 H V C CNN +F3 "" 0 50 60 H V C CNN +DRAW +T 0 0 400 60 0 0 0 4:16~ Normal 0 C C +T 0 0 250 60 0 0 0 decoder Normal 0 C C +S -350 700 400 -700 0 0 0 N +X ~Y0 1 -550 550 200 R 50 50 1 1 O I +X ~Y1 2 -550 450 200 R 50 50 1 1 O I +X ~Y2 3 -550 350 200 R 50 50 1 1 O I +X ~Y3 4 -550 250 200 R 50 50 1 1 O I +X ~Y4 5 -550 150 200 R 50 50 1 1 O I +X ~Y5 6 -550 50 200 R 50 50 1 1 O I +X ~Y6 7 -550 -50 200 R 50 50 1 1 O I +X ~Y7 8 -550 -150 200 R 50 50 1 1 O I +X ~Y8 9 -550 -250 200 R 50 50 1 1 O I +X ~Y9 10 -550 -350 200 R 50 50 1 1 O I +X A3 20 600 150 200 L 50 50 1 1 I +X ~Y10 11 -550 -450 200 R 50 50 1 1 O I +X A2 21 600 250 200 L 50 50 1 1 I +X GND 12 -550 -550 200 R 50 50 1 1 I +X A1 22 600 350 200 L 50 50 1 1 I +X ~Y11 13 600 -550 200 L 50 50 1 1 O I +X A0 23 600 450 200 L 50 50 1 1 I +X ~Y12 14 600 -450 200 L 50 50 1 1 O I +X Vcc 24 600 550 200 L 50 50 1 1 I +X ~Y13 15 600 -350 200 L 50 50 1 1 O I +X ~Y14 16 600 -250 200 L 50 50 1 1 O I +X ~Y15 17 600 -150 200 L 50 50 1 1 O I +X ~E0 18 600 -50 200 L 50 50 1 1 I I +X ~E1 19 600 50 200 L 50 50 1 1 I I +ENDDRAW +ENDDEF +# +# IC_74157 +# +DEF IC_74157 X 0 40 Y Y 1 F N +F0 "X" 50 -50 60 H V C CNN +F1 "IC_74157" 50 100 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 50 -300 60 0 0 0 2:1 Normal 0 C C +T 0 50 -400 60 0 0 0 MUX Normal 0 C C +T 0 50 -200 60 0 0 0 QUAD Normal 0 C C +S -350 550 400 -650 0 1 0 N +X a0 1 -550 450 200 R 50 50 1 1 I +X a1 2 -550 300 200 R 50 50 1 1 I +X b0 3 -550 200 200 R 50 50 1 1 I +X b1 4 -550 100 200 R 50 50 1 1 I +X c0 5 -550 0 200 R 50 50 1 1 I +X c1 6 -550 -100 200 R 50 50 1 1 I +X d0 7 -550 -200 200 R 50 50 1 1 I +X d1 8 -550 -300 200 R 50 50 1 1 I +X EN 9 -550 -550 200 R 50 50 1 1 I I +X S 10 -550 -450 200 R 50 50 1 1 I +X Yd 11 600 0 200 L 50 50 1 1 O +X Ya 12 600 300 200 L 50 50 1 1 O +X Yb 13 600 200 200 L 50 50 1 1 O +X Yc 14 600 100 200 L 50 50 1 1 O +ENDDRAW +ENDDEF +# +# IC_7485 +# +DEF IC_7485 X 0 40 Y Y 1 F N +F0 "X" -50 -100 60 H V C CNN +F1 "IC_7485" -50 50 60 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +T 0 0 550 60 0 0 0 4~BIT~comparator Normal 0 C C +S -350 450 400 -400 0 1 0 N +X AB(in) 3 600 -300 200 L 50 50 1 1 I +X A3 4 -550 100 200 R 50 50 1 1 I +X B3 5 -550 -350 200 R 50 50 1 1 I +X A2 6 -550 200 200 R 50 50 1 1 I +X B2 7 -550 -250 200 R 50 50 1 1 I +X A1 8 -550 300 200 R 50 50 1 1 I +X B1 9 -550 -150 200 R 50 50 1 1 I +X A0 10 -550 400 200 R 50 50 1 1 I +X B0 11 -550 -50 200 R 50 50 1 1 I +X A>B(out) 12 600 350 200 L 50 50 1 1 O +X A=B(out) 13 600 250 200 L 50 50 1 1 O +X A plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM13700/LM13700.pro b/library/SubcircuitLibrary/LM13700/LM13700.pro new file mode 100644 index 000000000..b4c76509c --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:32:27 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM13700/LM13700.sch b/library/SubcircuitLibrary/LM13700/LM13700.sch new file mode 100644 index 000000000..cf3353722 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700.sch @@ -0,0 +1,991 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM13700-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q3 +U 1 1 62C1C504 +P 2500 1700 +F 0 "Q3" H 2400 1750 50 0000 R CNN +F 1 "eSim_PNP" H 2450 1850 50 0000 R CNN +F 2 "" H 2700 1800 29 0000 C CNN +F 3 "" H 2500 1700 60 0000 C CNN + 1 2500 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 62C1C505 +P 3200 1450 +F 0 "D4" H 3200 1550 50 0000 C CNN +F 1 "eSim_Diode" H 3200 1350 50 0000 C CNN +F 2 "" H 3200 1450 60 0000 C CNN +F 3 "" H 3200 1450 60 0000 C CNN + 1 3200 1450 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q6 +U 1 1 62C1C506 +P 3100 2250 +F 0 "Q6" H 3000 2300 50 0000 R CNN +F 1 "eSim_PNP" H 3050 2400 50 0000 R CNN +F 2 "" H 3300 2350 29 0000 C CNN +F 3 "" H 3100 2250 60 0000 C CNN + 1 3100 2250 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 62C1C507 +P 3800 1700 +F 0 "Q7" H 3700 1750 50 0000 R CNN +F 1 "eSim_PNP" H 3750 1850 50 0000 R CNN +F 2 "" H 4000 1800 29 0000 C CNN +F 3 "" H 3800 1700 60 0000 C CNN + 1 3800 1700 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D5 +U 1 1 62C1C508 +P 4500 1450 +F 0 "D5" H 4500 1550 50 0000 C CNN +F 1 "eSim_Diode" H 4500 1350 50 0000 C CNN +F 2 "" H 4500 1450 60 0000 C CNN +F 3 "" H 4500 1450 60 0000 C CNN + 1 4500 1450 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 62C1C509 +P 4400 2250 +F 0 "Q9" H 4300 2300 50 0000 R CNN +F 1 "eSim_PNP" H 4350 2400 50 0000 R CNN +F 2 "" H 4600 2350 29 0000 C CNN +F 3 "" H 4400 2250 60 0000 C CNN + 1 4400 2250 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 62C1C50A +P 4950 1500 +F 0 "Q11" H 4850 1550 50 0000 R CNN +F 1 "eSim_NPN" H 4900 1650 50 0000 R CNN +F 2 "" H 5150 1600 29 0000 C CNN +F 3 "" H 4950 1500 60 0000 C CNN + 1 4950 1500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 62C1C50B +P 5600 1700 +F 0 "Q12" H 5500 1750 50 0000 R CNN +F 1 "eSim_NPN" H 5550 1850 50 0000 R CNN +F 2 "" H 5800 1800 29 0000 C CNN +F 3 "" H 5600 1700 60 0000 C CNN + 1 5600 1700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q2 +U 1 1 62C1C50C +P 2300 3350 +F 0 "Q2" H 2200 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2250 3500 50 0000 R CNN +F 2 "" H 2500 3450 29 0000 C CNN +F 3 "" H 2300 3350 60 0000 C CNN + 1 2300 3350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q5 +U 1 1 62C1C50D +P 2850 3350 +F 0 "Q5" H 2750 3400 50 0000 R CNN +F 1 "eSim_NPN" H 2800 3500 50 0000 R CNN +F 2 "" H 3050 3450 29 0000 C CNN +F 3 "" H 2850 3350 60 0000 C CNN + 1 2850 3350 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D3 +U 1 1 62C1C50E +P 3200 3050 +F 0 "D3" H 3200 3150 50 0000 C CNN +F 1 "eSim_Diode" H 3200 2950 50 0000 C CNN +F 2 "" H 3200 3050 60 0000 C CNN +F 3 "" H 3200 3050 60 0000 C CNN + 1 3200 3050 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 62C1C50F +P 2000 3050 +F 0 "D1" H 2000 3150 50 0000 C CNN +F 1 "eSim_Diode" H 2000 2950 50 0000 C CNN +F 2 "" H 2000 3050 60 0000 C CNN +F 3 "" H 2000 3050 60 0000 C CNN + 1 2000 3050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q4 +U 1 1 62C1C510 +P 2500 4250 +F 0 "Q4" H 2400 4300 50 0000 R CNN +F 1 "eSim_NPN" H 2450 4400 50 0000 R CNN +F 2 "" H 2700 4350 29 0000 C CNN +F 3 "" H 2500 4250 60 0000 C CNN + 1 2500 4250 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 62C1C511 +P 2150 4750 +F 0 "Q1" H 2050 4800 50 0000 R CNN +F 1 "eSim_NPN" H 2100 4900 50 0000 R CNN +F 2 "" H 2350 4850 29 0000 C CNN +F 3 "" H 2150 4750 60 0000 C CNN + 1 2150 4750 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 62C1C512 +P 2600 5150 +F 0 "D2" H 2600 5250 50 0000 C CNN +F 1 "eSim_Diode" H 2600 5050 50 0000 C CNN +F 2 "" H 2600 5150 60 0000 C CNN +F 3 "" H 2600 5150 60 0000 C CNN + 1 2600 5150 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 62C1C513 +P 4400 4050 +F 0 "Q10" H 4300 4100 50 0000 R CNN +F 1 "eSim_NPN" H 4350 4200 50 0000 R CNN +F 2 "" H 4600 4150 29 0000 C CNN +F 3 "" H 4400 4050 60 0000 C CNN + 1 4400 4050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 62C1C514 +P 3800 4700 +F 0 "Q8" H 3700 4750 50 0000 R CNN +F 1 "eSim_NPN" H 3750 4850 50 0000 R CNN +F 2 "" H 4000 4800 29 0000 C CNN +F 3 "" H 3800 4700 60 0000 C CNN + 1 3800 4700 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 62C1C515 +P 4500 5150 +F 0 "D6" H 4500 5250 50 0000 C CNN +F 1 "eSim_Diode" H 4500 5050 50 0000 C CNN +F 2 "" H 4500 5150 60 0000 C CNN +F 3 "" H 4500 5150 60 0000 C CNN + 1 4500 5150 + 0 1 1 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7350 2900 +Wire Wire Line + 3200 2800 3200 2900 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM13700/LM13700.sub b/library/SubcircuitLibrary/LM13700/LM13700.sub new file mode 100644 index 000000000..81d112355 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700.sub @@ -0,0 +1,45 @@ +* Subcircuit LM13700 +.subckt LM13700 /v+ /diode_bias /input- /input+ /amp_bias_input /v- /output /diode_bias /input- /input+ /amp_bias_input /buffer_output /buffer_input /output /buffer_output /bufer_input +* c:\fossee\esim\library\subcircuitlibrary\lm13700\lm13700.cir +.include D.lib +.include PNP.lib +.include NPN.lib +q3 net-_q2-pad1_ net-_d4-pad2_ /v+ Q2N2907A +d4 /v+ net-_d4-pad2_ 1N4148 +q6 net-_q10-pad2_ net-_q2-pad1_ net-_d4-pad2_ Q2N2907A +q7 net-_q5-pad1_ net-_d5-pad2_ /v+ Q2N2907A +d5 /v+ net-_d5-pad2_ 1N4148 +q9 /output net-_q5-pad1_ net-_d5-pad2_ Q2N2907A +q11 /v+ /buffer_input net-_q11-pad3_ Q2N2222 +q12 /v+ net-_q11-pad3_ /buffer_output Q2N2222 +q2 net-_q2-pad1_ /input- net-_q2-pad3_ Q2N2222 +q5 net-_q5-pad1_ /input+ net-_q2-pad3_ Q2N2222 +d3 /diode_bias /input+ 1N4148 +d1 /diode_bias /input- 1N4148 +q4 net-_q2-pad3_ /amp_bias_input net-_d2-pad1_ Q2N2222 +q1 /amp_bias_input net-_d2-pad1_ /v- Q2N2222 +d2 net-_d2-pad1_ /v- 1N4148 +q10 /output net-_q10-pad2_ net-_d6-pad1_ Q2N2222 +q8 net-_q10-pad2_ net-_d6-pad1_ /v- Q2N2222 +d6 net-_d6-pad1_ /v- 1N4148 +q15 net-_q14-pad1_ net-_d10-pad2_ /v+ Q2N2907A +d10 /v+ net-_d10-pad2_ 1N4148 +q18 net-_q18-pad1_ net-_q14-pad1_ net-_d10-pad2_ Q2N2907A +q19 net-_q17-pad1_ net-_d11-pad2_ /v+ Q2N2907A +d11 /v+ net-_d11-pad2_ 1N4148 +q21 /output net-_q17-pad1_ net-_d11-pad2_ Q2N2907A +q23 /v+ /bufer_input net-_q23-pad3_ Q2N2222 +q24 /v+ net-_q23-pad3_ /buffer_output Q2N2222 +q14 net-_q14-pad1_ /input- net-_q14-pad3_ Q2N2222 +q17 net-_q17-pad1_ /input+ net-_q14-pad3_ Q2N2222 +d9 /diode_bias /input+ 1N4148 +d7 /diode_bias /input- 1N4148 +q16 net-_q14-pad3_ /amp_bias_input net-_d8-pad1_ Q2N2222 +q13 /amp_bias_input net-_d8-pad1_ /v- Q2N2222 +d8 net-_d8-pad1_ /v- 1N4148 +q22 /output net-_q18-pad1_ net-_d12-pad1_ Q2N2222 +q20 net-_q18-pad1_ net-_d12-pad1_ /v- Q2N2222 +d12 net-_d12-pad1_ /v- 1N4148 +* Control Statements + +.ends LM13700 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM13700/LM13700_Previous_Values.xml b/library/SubcircuitLibrary/LM13700/LM13700_Previous_Values.xml new file mode 100644 index 000000000..68f6df1ff --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/LM13700_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM13700/NPN.lib b/library/SubcircuitLibrary/LM13700/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM13700/PNP.lib b/library/SubcircuitLibrary/LM13700/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM13700/README.md b/library/SubcircuitLibrary/LM13700/README.md new file mode 100644 index 000000000..cca1cfed3 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/README.md @@ -0,0 +1,34 @@ + +# LM13700 Operational Transconductance Amplifier IC + +The LM13700 is a current controlled, additional output buffer-equipped, differential input, transconductance amplifier with two channels. The two amplifiers operate independently, sharing a common supply. It makes use of linearizing diodes, using which higher input levels are permitted with less distortion. It has improved SNR also. + + +## Usage/Examples + +VCA (Voltage Controlled Amplifier) + +ACG (Automatic Gain Contol) Amplifier + +VCO (Voltage controlled Oscillator) + +PLL (Phase Locked loop) + +Four Quadrant Multiplier + +Amplitude Modulator + +## Documentation + +To know the details of LM13700 IC please refer to this link [LM13700_datasheet.](https://www.ti.com/lit/ds/symlink/lm13700.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. Due to the improper modeling of Darlington pair at the output terminals, this IC is producing improper output. The shape of the output waveform is fine but the output is highly DC shifted & also it's peak to peak value is very low. Therefore it is suggested to use this IC only after replacing the subcircuit with a proper working Darlington pair. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/LM13700/analysis b/library/SubcircuitLibrary/LM13700/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/LM13700/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM321/LM321-cache.lib b/library/SubcircuitLibrary/LM321/LM321-cache.lib new file mode 100644 index 000000000..7eda2392c --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321-cache.lib @@ -0,0 +1,141 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM321/LM321.cir b/library/SubcircuitLibrary/LM321/LM321.cir new file mode 100644 index 000000000..365f931d7 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.cir @@ -0,0 +1,48 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM321\LM321.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 08/04/22 16:17:25 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_Q12-Pad2_ Net-_Q3-Pad2_ Net-_J1-Pad1_ Net-_Q24-Pad3_ Net-_J1-Pad2_ PORT +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q14 Net-_Q14-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q19 Net-_Q1-Pad2_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q4 Net-_Q3-Pad3_ Net-_Q3-Pad3_ Net-_Q11-Pad3_ eSim_PNP +Q11 Net-_Q11-Pad1_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_PNP +Q3 Net-_J1-Pad2_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_PNP +Q12 Net-_J1-Pad2_ Net-_Q12-Pad2_ Net-_Q11-Pad1_ eSim_PNP +Q2 Net-_J1-Pad2_ Net-_Q2-Pad2_ Net-_Q1-Pad1_ eSim_PNP +Q9 Net-_C1-Pad2_ Net-_Q2-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q5 Net-_Q2-Pad2_ Net-_Q2-Pad2_ Net-_J1-Pad2_ eSim_NPN +Q13 Net-_J1-Pad2_ Net-_C1-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q15 Net-_Q14-Pad1_ Net-_Q10-Pad1_ Net-_Q15-Pad3_ eSim_NPN +Q17 Net-_Q15-Pad3_ Net-_Q16-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q18 Net-_J1-Pad2_ Net-_Q16-Pad1_ Net-_Q14-Pad1_ eSim_PNP +Q20 Net-_Q16-Pad1_ Net-_Q16-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q21 Net-_C1-Pad1_ Net-_Q15-Pad3_ Net-_J1-Pad2_ eSim_NPN +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 5p +Q24 Net-_C1-Pad1_ Net-_Q24-Pad2_ Net-_Q24-Pad3_ eSim_NPN +R1 Net-_Q23-Pad3_ Net-_Q24-Pad2_ 40k +Q23 Net-_J1-Pad1_ Net-_C1-Pad1_ Net-_Q23-Pad3_ eSim_NPN +Q25 Net-_J1-Pad1_ Net-_Q23-Pad3_ Net-_Q24-Pad2_ eSim_NPN +R2 Net-_Q24-Pad2_ Net-_Q24-Pad3_ 25 +Q26 Net-_J1-Pad2_ Net-_C1-Pad1_ Net-_Q24-Pad3_ eSim_PNP +Q27 Net-_Q24-Pad3_ Net-_Q16-Pad1_ Net-_J1-Pad2_ eSim_NPN +Q28 Net-_Q1-Pad2_ Net-_Q28-Pad2_ Net-_Q28-Pad3_ eSim_NPN +R3 Net-_Q28-Pad3_ Net-_J1-Pad2_ 2k +J1 Net-_J1-Pad1_ Net-_J1-Pad2_ Net-_J1-Pad3_ jfet_n +Q31 Net-_J1-Pad1_ Net-_J1-Pad3_ Net-_Q30-Pad2_ eSim_NPN +Q29 Net-_J1-Pad3_ Net-_J1-Pad3_ Net-_Q28-Pad2_ eSim_NPN +Q30 Net-_Q28-Pad2_ Net-_Q30-Pad2_ Net-_J1-Pad2_ eSim_NPN +R4 Net-_Q30-Pad2_ Net-_J1-Pad2_ 2.4k +Q7 Net-_Q11-Pad3_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q16 Net-_Q16-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +Q6 Net-_Q2-Pad2_ Net-_Q3-Pad3_ Net-_Q11-Pad3_ eSim_PNP +Q8 Net-_C1-Pad2_ Net-_Q11-Pad1_ Net-_Q11-Pad3_ eSim_PNP +Q22 Net-_C1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP + +.end diff --git a/library/SubcircuitLibrary/LM321/LM321.cir.out b/library/SubcircuitLibrary/LM321/LM321.cir.out new file mode 100644 index 000000000..17548c8fc --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.cir.out @@ -0,0 +1,52 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm321\lm321.cir + +.include PNP.lib +.include NPN.lib +.include NJF.lib +* u1 net-_q12-pad2_ net-_q3-pad2_ net-_j1-pad1_ net-_q24-pad3_ net-_j1-pad2_ port +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q19 net-_q1-pad2_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_q3-pad3_ net-_q3-pad3_ net-_q11-pad3_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2907A +q3 net-_j1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2907A +q12 net-_j1-pad2_ net-_q12-pad2_ net-_q11-pad1_ Q2N2907A +q2 net-_j1-pad2_ net-_q2-pad2_ net-_q1-pad1_ Q2N2907A +q9 net-_c1-pad2_ net-_q2-pad2_ net-_j1-pad2_ Q2N2222 +q5 net-_q2-pad2_ net-_q2-pad2_ net-_j1-pad2_ Q2N2222 +q13 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +q15 net-_q14-pad1_ net-_q10-pad1_ net-_q15-pad3_ Q2N2222 +q17 net-_q15-pad3_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q18 net-_j1-pad2_ net-_q16-pad1_ net-_q14-pad1_ Q2N2907A +q20 net-_q16-pad1_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q21 net-_c1-pad1_ net-_q15-pad3_ net-_j1-pad2_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 5p +q24 net-_c1-pad1_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222 +r1 net-_q23-pad3_ net-_q24-pad2_ 40k +q23 net-_j1-pad1_ net-_c1-pad1_ net-_q23-pad3_ Q2N2222 +q25 net-_j1-pad1_ net-_q23-pad3_ net-_q24-pad2_ Q2N2222 +r2 net-_q24-pad2_ net-_q24-pad3_ 25 +q26 net-_j1-pad2_ net-_c1-pad1_ net-_q24-pad3_ Q2N2907A +q27 net-_q24-pad3_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q28 net-_q1-pad2_ net-_q28-pad2_ net-_q28-pad3_ Q2N2222 +r3 net-_q28-pad3_ net-_j1-pad2_ 2k +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q31 net-_j1-pad1_ net-_j1-pad3_ net-_q30-pad2_ Q2N2222 +q29 net-_j1-pad3_ net-_j1-pad3_ net-_q28-pad2_ Q2N2222 +q30 net-_q28-pad2_ net-_q30-pad2_ net-_j1-pad2_ Q2N2222 +r4 net-_q30-pad2_ net-_j1-pad2_ 2.4k +q7 net-_q11-pad3_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q16 net-_q16-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q6 net-_q2-pad2_ net-_q3-pad3_ net-_q11-pad3_ Q2N2907A +q8 net-_c1-pad2_ net-_q11-pad1_ net-_q11-pad3_ Q2N2907A +q22 net-_c1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM321/LM321.pro b/library/SubcircuitLibrary/LM321/LM321.pro new file mode 100644 index 000000000..ef711b9b9 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:32:10 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM321/LM321.sch b/library/SubcircuitLibrary/LM321/LM321.sch new file mode 100644 index 000000000..b7b739243 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.sch @@ -0,0 +1,821 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM321-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L PORT U1 +U 3 1 62DAF186 +P 10300 950 +F 0 "U1" H 10350 1050 30 0000 C CNN +F 1 "PORT" H 10300 950 30 0000 C CNN +F 2 "" H 10300 950 60 0000 C CNN +F 3 "" H 10300 950 60 0000 C CNN + 3 10300 950 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 4 1 62DAF1ED +P 10300 3200 +F 0 "U1" H 10350 3300 30 0000 C CNN +F 1 "PORT" H 10300 3200 30 0000 C CNN +F 2 "" H 10300 3200 60 0000 C CNN +F 3 "" H 10300 3200 60 0000 C CNN + 4 10300 3200 + -1 0 0 1 +$EndComp +$Comp +L PORT U1 +U 5 1 62DAF4F7 +P 10350 6000 +F 0 "U1" H 10400 6100 30 0000 C CNN +F 1 "PORT" H 10350 6000 30 0000 C CNN +F 2 "" H 10350 6000 60 0000 C CNN +F 3 "" H 10350 6000 60 0000 C CNN + 5 10350 6000 + -1 0 0 1 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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/library/SubcircuitLibrary/LM321/LM321.sub b/library/SubcircuitLibrary/LM321/LM321.sub new file mode 100644 index 000000000..4a888591c --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321.sub @@ -0,0 +1,46 @@ +* Subcircuit LM321 +.subckt LM321 net-_q12-pad2_ net-_q3-pad2_ net-_j1-pad1_ net-_q24-pad3_ net-_j1-pad2_ +* c:\fossee\esim\library\subcircuitlibrary\lm321\lm321.cir +.include PNP.lib +.include NPN.lib +.include NJF.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q19 net-_q1-pad2_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q4 net-_q3-pad3_ net-_q3-pad3_ net-_q11-pad3_ Q2N2907A +q11 net-_q11-pad1_ net-_q11-pad1_ net-_q11-pad3_ Q2N2907A +q3 net-_j1-pad2_ net-_q3-pad2_ net-_q3-pad3_ Q2N2907A +q12 net-_j1-pad2_ net-_q12-pad2_ net-_q11-pad1_ Q2N2907A +q2 net-_j1-pad2_ net-_q2-pad2_ net-_q1-pad1_ Q2N2907A +q9 net-_c1-pad2_ net-_q2-pad2_ net-_j1-pad2_ Q2N2222 +q5 net-_q2-pad2_ net-_q2-pad2_ net-_j1-pad2_ Q2N2222 +q13 net-_j1-pad2_ net-_c1-pad2_ net-_q10-pad1_ Q2N2907A +q15 net-_q14-pad1_ net-_q10-pad1_ net-_q15-pad3_ Q2N2222 +q17 net-_q15-pad3_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q18 net-_j1-pad2_ net-_q16-pad1_ net-_q14-pad1_ Q2N2907A +q20 net-_q16-pad1_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q21 net-_c1-pad1_ net-_q15-pad3_ net-_j1-pad2_ Q2N2222 +c1 net-_c1-pad1_ net-_c1-pad2_ 5p +q24 net-_c1-pad1_ net-_q24-pad2_ net-_q24-pad3_ Q2N2222 +r1 net-_q23-pad3_ net-_q24-pad2_ 40k +q23 net-_j1-pad1_ net-_c1-pad1_ net-_q23-pad3_ Q2N2222 +q25 net-_j1-pad1_ net-_q23-pad3_ net-_q24-pad2_ Q2N2222 +r2 net-_q24-pad2_ net-_q24-pad3_ 25 +q26 net-_j1-pad2_ net-_c1-pad1_ net-_q24-pad3_ Q2N2907A +q27 net-_q24-pad3_ net-_q16-pad1_ net-_j1-pad2_ Q2N2222 +q28 net-_q1-pad2_ net-_q28-pad2_ net-_q28-pad3_ Q2N2222 +r3 net-_q28-pad3_ net-_j1-pad2_ 2k +j1 net-_j1-pad1_ net-_j1-pad2_ net-_j1-pad3_ J2N3819 +q31 net-_j1-pad1_ net-_j1-pad3_ net-_q30-pad2_ Q2N2222 +q29 net-_j1-pad3_ net-_j1-pad3_ net-_q28-pad2_ Q2N2222 +q30 net-_q28-pad2_ net-_q30-pad2_ net-_j1-pad2_ Q2N2222 +r4 net-_q30-pad2_ net-_j1-pad2_ 2.4k +q7 net-_q11-pad3_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q16 net-_q16-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +q6 net-_q2-pad2_ net-_q3-pad3_ net-_q11-pad3_ Q2N2907A +q8 net-_c1-pad2_ net-_q11-pad1_ net-_q11-pad3_ Q2N2907A +q22 net-_c1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +* Control Statements + +.ends LM321 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM321/LM321_Previous_Values.xml b/library/SubcircuitLibrary/LM321/LM321_Previous_Values.xml new file mode 100644 index 000000000..8b38814c4 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/LM321_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM321/NJF.lib b/library/SubcircuitLibrary/LM321/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM321/NPN.lib b/library/SubcircuitLibrary/LM321/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LM321/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM321/PNP.lib b/library/SubcircuitLibrary/LM321/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/LM321/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM321/README.md b/library/SubcircuitLibrary/LM321/README.md new file mode 100644 index 000000000..ad011f2a9 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/README.md @@ -0,0 +1,35 @@ + +# LM321 Operational Amplifier IC + +LM321 is a 5 pin Op-Amp IC. It has differential input, is internally compensated. Supply voltage ranges from 3V to 32V. Output is short circuit protected. Its output stage is class B, comprising of push-pull transistors. Hence output contains crossover distortion near mid-rail where neither push or pull transistor is conducting. + + +## Usage/Examples + +Inverting/Non-Inverting Amplifier + +Integrator/Summer + +Differential Amplifier + +Differentiator + +Schmitt Trigger + +Comparators + + +## Documentation + +To know the details of LM321 IC please refer to this link [LM321_datasheet.](https://www.onsemi.com/pdf/datasheet/lm321-d.pdf) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/LM321/analysis b/library/SubcircuitLibrary/LM321/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/LM321/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM393/D.lib b/library/SubcircuitLibrary/LM393/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM393/LM393-cache.lib b/library/SubcircuitLibrary/LM393/LM393-cache.lib new file mode 100644 index 000000000..8ff65b6b3 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393-cache.lib @@ -0,0 +1,146 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM393/LM393.cir b/library/SubcircuitLibrary/LM393/LM393.cir new file mode 100644 index 000000000..4d9c6b46b --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.cir @@ -0,0 +1,61 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM393\LM393.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 08/29/22 20:35:27 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_J1-Pad1_ eSim_PNP +R2 Net-_Q1-Pad2_ Net-_Q1-Pad1_ 2k +Q4 Net-_J1-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q5 Net-_Q2-Pad3_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q8 Net-_D4-Pad1_ Net-_Q1-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q10 Net-_Q10-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q14 Net-_Q14-Pad1_ Net-_Q1-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q2 Net-_Q1-Pad1_ Net-_J1-Pad3_ Net-_Q2-Pad3_ eSim_NPN +R1 Net-_Q2-Pad3_ Net-_D3-Pad2_ 4.6k +J1 Net-_J1-Pad1_ Net-_D3-Pad2_ Net-_J1-Pad3_ jfet_n +Q3 Net-_J1-Pad3_ Net-_Q2-Pad3_ Net-_D3-Pad2_ eSim_NPN +D2 Net-_D2-Pad1_ Net-_D1-Pad2_ eSim_Diode +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q6 Net-_D3-Pad2_ Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q9 Net-_D3-Pad1_ Net-_D1-Pad2_ Net-_Q10-Pad1_ eSim_PNP +Q12 Net-_Q11-Pad1_ Net-_D4-Pad2_ Net-_Q10-Pad1_ eSim_PNP +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q11 Net-_Q11-Pad1_ Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_NPN +D4 Net-_D4-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q13 Net-_D3-Pad2_ Net-_D5-Pad1_ Net-_D4-Pad2_ eSim_PNP +D5 Net-_D5-Pad1_ Net-_D4-Pad2_ eSim_Diode +Q15 Net-_Q14-Pad1_ Net-_Q11-Pad1_ Net-_D3-Pad2_ eSim_NPN +Q16 Net-_Q16-Pad1_ Net-_Q14-Pad1_ Net-_D3-Pad2_ eSim_NPN +R3 Net-_J1-Pad1_ Net-_Q7-Pad3_ 2.1k +U1 Net-_J1-Pad1_ Net-_D1-Pad1_ Net-_D5-Pad1_ Net-_Q16-Pad1_ Net-_D3-Pad2_ Net-_D6-Pad1_ Net-_D10-Pad1_ Net-_Q32-Pad1_ PORT +Q7 Net-_D2-Pad1_ Net-_Q1-Pad1_ Net-_Q7-Pad3_ eSim_PNP +Q17 Net-_Q17-Pad1_ Net-_Q17-Pad2_ Net-_J1-Pad1_ eSim_PNP +R5 Net-_Q17-Pad2_ Net-_Q17-Pad1_ 2k +Q20 Net-_J2-Pad3_ Net-_Q17-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q21 Net-_Q18-Pad3_ Net-_Q17-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q24 Net-_D9-Pad1_ Net-_Q17-Pad1_ Net-_Q23-Pad3_ eSim_PNP +Q26 Net-_Q25-Pad3_ Net-_Q17-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q30 Net-_Q30-Pad1_ Net-_Q17-Pad1_ Net-_J1-Pad1_ eSim_PNP +Q18 Net-_Q17-Pad1_ Net-_J2-Pad3_ Net-_Q18-Pad3_ eSim_NPN +R4 Net-_Q18-Pad3_ Net-_D3-Pad2_ 4.6k +J2 Net-_J1-Pad1_ Net-_D3-Pad2_ Net-_J2-Pad3_ jfet_n +Q19 Net-_J2-Pad3_ Net-_Q18-Pad3_ Net-_D3-Pad2_ eSim_NPN +D7 Net-_D7-Pad1_ Net-_D6-Pad2_ eSim_Diode +D6 Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_Diode +Q22 Net-_D3-Pad2_ Net-_D6-Pad1_ Net-_D6-Pad2_ eSim_PNP +Q25 Net-_D8-Pad1_ Net-_D6-Pad2_ Net-_Q25-Pad3_ eSim_PNP +Q28 Net-_Q27-Pad1_ Net-_D10-Pad2_ Net-_Q25-Pad3_ eSim_PNP +D8 Net-_D8-Pad1_ Net-_D3-Pad2_ eSim_Diode +Q27 Net-_Q27-Pad1_ Net-_D8-Pad1_ Net-_D3-Pad2_ eSim_NPN +D9 Net-_D9-Pad1_ Net-_D10-Pad2_ eSim_Diode +Q29 Net-_D3-Pad2_ Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_PNP +D10 Net-_D10-Pad1_ Net-_D10-Pad2_ eSim_Diode +Q31 Net-_Q30-Pad1_ Net-_Q27-Pad1_ Net-_D3-Pad2_ eSim_NPN +Q32 Net-_Q32-Pad1_ Net-_Q30-Pad1_ Net-_D3-Pad2_ eSim_NPN +R6 Net-_J1-Pad1_ Net-_Q23-Pad3_ 2.1k +Q23 Net-_D7-Pad1_ Net-_Q17-Pad1_ Net-_Q23-Pad3_ eSim_PNP + +.end diff --git a/library/SubcircuitLibrary/LM393/LM393.cir.out b/library/SubcircuitLibrary/LM393/LM393.cir.out new file mode 100644 index 000000000..57a7fed16 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.cir.out @@ -0,0 +1,66 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm393\lm393.cir + +.include PNP.lib +.include NPN.lib +.include NJF.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +r2 net-_q1-pad2_ net-_q1-pad1_ 2k +q4 net-_j1-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q5 net-_q2-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q8 net-_d4-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q2 net-_q1-pad1_ net-_j1-pad3_ net-_q2-pad3_ Q2N2222 +r1 net-_q2-pad3_ net-_d3-pad2_ 4.6k +j1 net-_j1-pad1_ net-_d3-pad2_ net-_j1-pad3_ J2N3819 +q3 net-_j1-pad3_ net-_q2-pad3_ net-_d3-pad2_ Q2N2222 +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q6 net-_d3-pad2_ net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_d3-pad1_ net-_d1-pad2_ net-_q10-pad1_ Q2N2907A +q12 net-_q11-pad1_ net-_d4-pad2_ net-_q10-pad1_ Q2N2907A +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q11 net-_q11-pad1_ net-_d3-pad1_ net-_d3-pad2_ Q2N2222 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q13 net-_d3-pad2_ net-_d5-pad1_ net-_d4-pad2_ Q2N2907A +d5 net-_d5-pad1_ net-_d4-pad2_ 1N4148 +q15 net-_q14-pad1_ net-_q11-pad1_ net-_d3-pad2_ Q2N2222 +q16 net-_q16-pad1_ net-_q14-pad1_ net-_d3-pad2_ Q2N2222 +r3 net-_j1-pad1_ net-_q7-pad3_ 2.1k +* u1 net-_j1-pad1_ net-_d1-pad1_ net-_d5-pad1_ net-_q16-pad1_ net-_d3-pad2_ net-_d6-pad1_ net-_d10-pad1_ net-_q32-pad1_ port +q7 net-_d2-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q17 net-_q17-pad1_ net-_q17-pad2_ net-_j1-pad1_ Q2N2907A +r5 net-_q17-pad2_ net-_q17-pad1_ 2k +q20 net-_j2-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q21 net-_q18-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q24 net-_d9-pad1_ net-_q17-pad1_ net-_q23-pad3_ Q2N2907A +q26 net-_q25-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q30 net-_q30-pad1_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q18 net-_q17-pad1_ net-_j2-pad3_ net-_q18-pad3_ Q2N2222 +r4 net-_q18-pad3_ net-_d3-pad2_ 4.6k +j2 net-_j1-pad1_ net-_d3-pad2_ net-_j2-pad3_ J2N3819 +q19 net-_j2-pad3_ net-_q18-pad3_ net-_d3-pad2_ Q2N2222 +d7 net-_d7-pad1_ net-_d6-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148 +q22 net-_d3-pad2_ net-_d6-pad1_ net-_d6-pad2_ Q2N2907A +q25 net-_d8-pad1_ net-_d6-pad2_ net-_q25-pad3_ Q2N2907A +q28 net-_q27-pad1_ net-_d10-pad2_ net-_q25-pad3_ Q2N2907A +d8 net-_d8-pad1_ net-_d3-pad2_ 1N4148 +q27 net-_q27-pad1_ net-_d8-pad1_ net-_d3-pad2_ Q2N2222 +d9 net-_d9-pad1_ net-_d10-pad2_ 1N4148 +q29 net-_d3-pad2_ net-_d10-pad1_ net-_d10-pad2_ Q2N2907A +d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148 +q31 net-_q30-pad1_ net-_q27-pad1_ net-_d3-pad2_ Q2N2222 +q32 net-_q32-pad1_ net-_q30-pad1_ net-_d3-pad2_ Q2N2222 +r6 net-_j1-pad1_ net-_q23-pad3_ 2.1k +q23 net-_d7-pad1_ net-_q17-pad1_ net-_q23-pad3_ Q2N2907A +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM393/LM393.pro b/library/SubcircuitLibrary/LM393/LM393.pro new file mode 100644 index 000000000..fd0582ba8 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:31:43 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM393/LM393.sch b/library/SubcircuitLibrary/LM393/LM393.sch new file mode 100644 index 000000000..5fe92798a --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.sch @@ -0,0 +1,1033 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM393-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +Wire Wire Line + 450 5800 11150 5800 +Wire Wire Line + 6000 5800 6000 6300 +$Comp +L PORT U1 +U 5 1 62EFFD91 +P 5750 6300 +F 0 "U1" H 5800 6400 30 0000 C CNN +F 1 "PORT" H 5750 6300 30 0000 C CNN +F 2 "" H 5750 6300 60 0000 C CNN +F 3 "" H 5750 6300 60 0000 C CNN + 5 5750 6300 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 1 1 62EFFD92 +P 350 1900 +F 0 "U1" H 400 2000 30 0000 C CNN +F 1 "PORT" H 350 1900 30 0000 C CNN +F 2 "" H 350 1900 60 0000 C CNN +F 3 "" H 350 1900 60 0000 C CNN + 1 350 1900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q17 +U 1 1 630DA5A7 +P 6450 2000 +F 0 "Q17" H 6350 2050 50 0000 R CNN +F 1 "eSim_PNP" H 6400 2150 50 0000 R CNN +F 2 "" H 6650 2100 29 0000 C CNN +F 3 "" H 6450 2000 60 0000 C CNN + 1 6450 2000 + -1 0 0 1 +$EndComp +$Comp +L resistor R5 +U 1 1 630DA5AD +P 6750 2050 +F 0 "R5" H 6800 2180 50 0000 C CNN +F 1 "2k" H 6800 2000 50 0000 C CNN +F 2 "" H 6800 2030 30 0000 C CNN +F 3 "" V 6800 2100 30 0000 C CNN + 1 6750 2050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q20 +U 1 1 630DA5B3 +P 7100 2550 +F 0 "Q20" H 7000 2600 50 0000 R CNN +F 1 "eSim_PNP" H 7050 2700 50 0000 R CNN +F 2 "" H 7300 2650 29 0000 C CNN +F 3 "" H 7100 2550 60 0000 C CNN + 1 7100 2550 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q21 +U 1 1 630DA5B9 +P 7600 2550 +F 0 "Q21" H 7500 2600 50 0000 R CNN +F 1 "eSim_PNP" H 7900 2800 50 0000 R CNN +F 2 "" H 7800 2650 29 0000 C CNN +F 3 "" H 7600 2550 60 0000 C CNN + 1 7600 2550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q24 +U 1 1 630DA5BF +P 8900 2550 +F 0 "Q24" H 8800 2600 50 0000 R CNN +F 1 "eSim_PNP" H 9150 2800 50 0000 R CNN +F 2 "" H 9100 2650 29 0000 C CNN +F 3 "" H 8900 2550 60 0000 C CNN + 1 8900 2550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q26 +U 1 1 630DA5C5 +P 9300 2550 +F 0 "Q26" H 9200 2600 50 0000 R CNN +F 1 "eSim_PNP" H 9550 2800 50 0000 R CNN +F 2 "" H 9500 2650 29 0000 C CNN +F 3 "" H 9300 2550 60 0000 C CNN + 1 9300 2550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q30 +U 1 1 630DA5CB +P 10650 2300 +F 0 "Q30" H 10550 2350 50 0000 R CNN +F 1 "eSim_PNP" H 10800 2450 50 0000 R CNN +F 2 "" H 10850 2400 29 0000 C CNN +F 3 "" H 10650 2300 60 0000 C CNN + 1 10650 2300 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q18 +U 1 1 630DA5D1 +P 6450 4400 +F 0 "Q18" H 6350 4450 50 0000 R CNN +F 1 "eSim_NPN" H 6400 4550 50 0000 R CNN +F 2 "" H 6650 4500 29 0000 C CNN +F 3 "" H 6450 4400 60 0000 C CNN + 1 6450 4400 + -1 0 0 -1 +$EndComp +$Comp +L resistor R4 +U 1 1 630DA5D7 +P 6300 5250 +F 0 "R4" H 6350 5380 50 0000 C CNN +F 1 "4.6k" H 6350 5200 50 0000 C CNN +F 2 "" H 6350 5230 30 0000 C CNN +F 3 "" V 6350 5300 30 0000 C CNN + 1 6300 5250 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J2 +U 1 1 630DA5DD +P 6050 3550 +F 0 "J2" H 5950 3600 50 0000 R CNN +F 1 "jfet_n" H 6000 3700 50 0000 R CNN +F 2 "" H 6250 3650 29 0000 C CNN +F 3 "" H 6050 3550 60 0000 C CNN + 1 6050 3550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 630DA5E3 +P 6900 4900 +F 0 "Q19" H 6800 4950 50 0000 R CNN +F 1 "eSim_NPN" H 6850 5050 50 0000 R CNN +F 2 "" H 7100 5000 29 0000 C CNN +F 3 "" H 6900 4900 60 0000 C CNN + 1 6900 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D7 +U 1 1 630DA5E9 +P 8300 3250 +F 0 "D7" H 8300 3350 50 0000 C CNN +F 1 "eSim_Diode" H 8300 3150 50 0000 C CNN +F 2 "" H 8300 3250 60 0000 C CNN +F 3 "" H 8300 3250 60 0000 C CNN + 1 8300 3250 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D6 +U 1 1 630DA5EF +P 8050 3700 +F 0 "D6" H 8050 3800 50 0000 C CNN +F 1 "eSim_Diode" H 8050 3600 50 0000 C CNN +F 2 "" H 8050 3700 60 0000 C CNN +F 3 "" H 8050 3700 60 0000 C CNN + 1 8050 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q22 +U 1 1 630DA5F5 +P 8050 4500 +F 0 "Q22" H 7950 4550 50 0000 R CNN +F 1 "eSim_PNP" H 8000 4650 50 0000 R CNN +F 2 "" H 8250 4600 29 0000 C CNN +F 3 "" H 8050 4500 60 0000 C CNN + 1 8050 4500 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q25 +U 1 1 630DA5FB +P 8900 4100 +F 0 "Q25" H 8800 4150 50 0000 R CNN +F 1 "eSim_PNP" H 8850 4250 50 0000 R CNN +F 2 "" H 9100 4200 29 0000 C CNN +F 3 "" H 8900 4100 60 0000 C CNN + 1 8900 4100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q28 +U 1 1 630DA601 +P 9600 4100 +F 0 "Q28" H 9500 4150 50 0000 R CNN +F 1 "eSim_PNP" H 9550 4250 50 0000 R CNN +F 2 "" H 9800 4200 29 0000 C CNN +F 3 "" H 9600 4100 60 0000 C CNN + 1 9600 4100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D8 +U 1 1 630DA607 +P 9000 5450 +F 0 "D8" H 9000 5550 50 0000 C CNN +F 1 "eSim_Diode" H 9000 5350 50 0000 C CNN +F 2 "" H 9000 5450 60 0000 C CNN +F 3 "" H 9000 5450 60 0000 C CNN + 1 9000 5450 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q27 +U 1 1 630DA60D +P 9400 5150 +F 0 "Q27" H 9300 5200 50 0000 R CNN +F 1 "eSim_NPN" H 9450 5300 50 0000 R CNN +F 2 "" H 9600 5250 29 0000 C CNN +F 3 "" H 9400 5150 60 0000 C CNN + 1 9400 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D9 +U 1 1 630DA613 +P 9900 3250 +F 0 "D9" H 9900 3350 50 0000 C CNN +F 1 "eSim_Diode" H 9900 3150 50 0000 C CNN +F 2 "" H 9900 3250 60 0000 C CNN +F 3 "" H 9900 3250 60 0000 C CNN + 1 9900 3250 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q29 +U 1 1 630DA619 +P 10200 4450 +F 0 "Q29" H 10100 4500 50 0000 R CNN +F 1 "eSim_PNP" H 10150 4600 50 0000 R CNN +F 2 "" H 10400 4550 29 0000 C CNN +F 3 "" H 10200 4450 60 0000 C CNN + 1 10200 4450 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D10 +U 1 1 630DA61F +P 10200 3650 +F 0 "D10" H 10200 3750 50 0000 C CNN +F 1 "eSim_Diode" H 10200 3550 50 0000 C CNN +F 2 "" H 10200 3650 60 0000 C CNN +F 3 "" H 10200 3650 60 0000 C CNN + 1 10200 3650 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q31 +U 1 1 630DA625 +P 10650 4800 +F 0 "Q31" H 10550 4850 50 0000 R CNN +F 1 "eSim_NPN" H 10700 4950 50 0000 R CNN +F 2 "" H 10850 4900 29 0000 C CNN +F 3 "" H 10650 4800 60 0000 C CNN + 1 10650 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q32 +U 1 1 630DA62B +P 11050 4400 +F 0 "Q32" H 10950 4450 50 0000 R CNN +F 1 "eSim_NPN" H 11100 4550 50 0000 R CNN +F 2 "" H 11250 4500 29 0000 C CNN +F 3 "" H 11050 4400 60 0000 C CNN + 1 11050 4400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 630DA631 +P 8650 1900 +F 0 "R6" H 8700 2030 50 0000 C CNN +F 1 "2.1k" H 8700 1850 50 0000 C CNN +F 2 "" H 8700 1880 30 0000 C CNN +F 3 "" V 8700 1950 30 0000 C CNN + 1 8650 1900 + 0 1 1 0 +$EndComp +Wire Wire Line + 6650 2000 6650 2000 +Wire Wire Line + 6950 2000 6950 2300 +Wire Wire Line + 6950 2300 6350 2300 +Wire Wire Line + 6350 2200 6350 4200 +Wire Wire Line + 6350 1650 6350 1800 +Wire Wire Line + 350 1650 10750 1650 +Wire Wire Line + 7000 2750 7000 4700 +Wire Wire Line + 7700 4900 7700 2750 +Wire Wire Line + 8300 2750 8300 3100 +Wire Wire Line + 9400 1650 9400 2350 +Wire Wire Line + 9400 2750 9400 3900 +Wire Wire Line + 10750 1650 10750 2100 +Connection ~ 9400 1650 +Wire Wire Line + 10750 2500 10750 4600 +Connection ~ 6350 2300 +Wire Wire Line + 6350 4600 6350 5150 +Wire Wire Line + 6350 5450 6350 5800 +Wire Wire Line + 6150 3750 6150 4400 +Wire Wire Line + 5850 5800 5850 3550 +Wire Wire Line + 6150 1650 6150 3350 +Connection ~ 6350 1650 +Connection ~ 7000 4400 +Wire Wire Line + 6150 4400 7000 4400 +Connection ~ 6650 4400 +Wire Wire Line + 6350 4900 7700 4900 +Connection ~ 6350 4900 +Wire Wire Line + 7000 5800 7000 5100 +Connection ~ 6350 5800 +Connection ~ 6700 4900 +Wire Wire Line + 8300 3400 8300 4100 +Wire Wire Line + 7850 1400 7850 4500 +Wire Wire Line + 8200 3700 8300 3700 +Connection ~ 8300 3700 +Wire Wire Line + 7900 3700 7850 3700 +Connection ~ 7850 3700 +Wire Wire Line + 8150 4300 8150 4100 +Wire Wire Line + 8150 4100 8700 4100 +Wire Wire Line + 8150 5800 8150 4700 +Connection ~ 7000 5800 +Connection ~ 8300 4100 +Wire Wire Line + 9000 3900 9500 3900 +Connection ~ 9400 3900 +Wire Wire Line + 9000 4300 9000 5300 +Wire Wire Line + 9000 5800 9000 5600 +Connection ~ 8150 5800 +Wire Wire Line + 9000 5150 9200 5150 +Connection ~ 9000 5150 +Wire Wire Line + 9500 5800 9500 5350 +Connection ~ 9000 5800 +Wire Wire Line + 9500 4300 9500 4950 +Wire Wire Line + 9900 2900 9900 3100 +Wire Wire Line + 9800 4100 10100 4100 +Wire Wire Line + 10100 4100 10100 4250 +Wire Wire Line + 9900 3400 9900 4100 +Connection ~ 9900 4100 +Wire Wire Line + 10100 5800 10100 4650 +Connection ~ 9500 5800 +Wire Wire Line + 10050 3650 9900 3650 +Connection ~ 9900 3650 +Wire Wire Line + 10500 4450 10400 4450 +Wire Wire Line + 10500 1400 10500 4450 +Wire Wire Line + 10500 3650 10350 3650 +Connection ~ 10500 3650 +Wire Wire Line + 10450 4800 9500 4800 +Connection ~ 9500 4800 +Wire Wire Line + 10750 5800 10750 5000 +Connection ~ 10100 5800 +Wire Wire Line + 10850 4400 10750 4400 +Connection ~ 10750 4400 +Wire Wire Line + 11150 5800 11150 4600 +Connection ~ 10750 5800 +Wire Wire Line + 11150 4200 11150 1500 +Connection ~ 6150 1650 +$Comp +L PORT U1 +U 6 1 630DA691 +P 7600 1400 +F 0 "U1" H 7650 1500 30 0000 C CNN +F 1 "PORT" H 7600 1400 30 0000 C CNN +F 2 "" H 7600 1400 60 0000 C CNN +F 3 "" H 7600 1400 60 0000 C CNN + 6 7600 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 7 1 630DA697 +P 10250 1400 +F 0 "U1" H 10300 1500 30 0000 C CNN +F 1 "PORT" H 10250 1400 30 0000 C CNN +F 2 "" H 10250 1400 60 0000 C CNN +F 3 "" H 10250 1400 60 0000 C CNN + 7 10250 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 630DA69D +P 11150 1250 +F 0 "U1" H 11200 1350 30 0000 C CNN +F 1 "PORT" H 11150 1250 30 0000 C CNN +F 2 "" H 11150 1250 60 0000 C CNN +F 3 "" H 11150 1250 60 0000 C CNN + 8 11150 1250 + 0 1 1 0 +$EndComp +Wire Wire Line + 7000 2350 7000 1900 +Wire Wire Line + 7000 1900 7700 1900 +Wire Wire Line + 7700 1900 7700 2350 +Wire Wire Line + 7400 1900 7400 1650 +Connection ~ 7400 1650 +Connection ~ 7400 1900 +Wire Wire Line + 7300 2550 7400 2550 +Wire Wire Line + 6950 2150 7350 2150 +Wire Wire Line + 7350 2150 7350 2550 +Connection ~ 7350 2550 +Connection ~ 6950 2150 +$Comp +L eSim_PNP Q23 +U 1 1 630DA6AE +P 8400 2550 +F 0 "Q23" H 8300 2600 50 0000 R CNN +F 1 "eSim_PNP" H 8700 2800 50 0000 R CNN +F 2 "" H 8600 2650 29 0000 C CNN +F 3 "" H 8400 2550 60 0000 C CNN + 1 8400 2550 + -1 0 0 1 +$EndComp +Wire Wire Line + 8600 2550 8700 2550 +Wire Wire Line + 7350 2300 10450 2300 +Wire Wire Line + 8650 2300 8650 2550 +Connection ~ 8650 2550 +Connection ~ 7350 2300 +Wire Wire Line + 8700 1800 8700 1650 +Connection ~ 8700 1650 +Wire Wire Line + 8300 2350 8300 2200 +Wire Wire Line + 8300 2200 9000 2200 +Wire Wire Line + 9000 2200 9000 2350 +Wire Wire Line + 8700 2200 8700 2100 +Connection ~ 8700 2200 +Wire Wire Line + 9900 2900 9000 2900 +Wire Wire Line + 9000 2900 9000 2750 +Wire Wire Line + 9100 2300 9100 2550 +Connection ~ 8650 2300 +Connection ~ 9100 2300 +Connection ~ 5850 5800 +$Comp +L eSim_PNP Q? +U 1 1 632F6C1E +P 1050 2000 +F 0 "Q?" H 950 2050 50 0000 R CNN +F 1 "eSim_PNP" H 1000 2150 50 0000 R CNN +F 2 "" H 1250 2100 29 0000 C CNN +F 3 "" H 1050 2000 60 0000 C CNN + 1 1050 2000 + -1 0 0 1 +$EndComp +$Comp +L resistor R? +U 1 1 632F6C24 +P 1350 2050 +F 0 "R?" H 1400 2180 50 0000 C CNN +F 1 "2k" H 1400 2000 50 0000 C CNN +F 2 "" H 1400 2030 30 0000 C CNN +F 3 "" V 1400 2100 30 0000 C CNN + 1 1350 2050 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C2A +P 1700 2550 +F 0 "Q?" H 1600 2600 50 0000 R CNN +F 1 "eSim_PNP" H 1650 2700 50 0000 R CNN +F 2 "" H 1900 2650 29 0000 C CNN +F 3 "" H 1700 2550 60 0000 C CNN + 1 1700 2550 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C30 +P 2200 2550 +F 0 "Q?" H 2100 2600 50 0000 R CNN +F 1 "eSim_PNP" H 2500 2800 50 0000 R CNN +F 2 "" H 2400 2650 29 0000 C CNN +F 3 "" H 2200 2550 60 0000 C CNN + 1 2200 2550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C36 +P 3500 2550 +F 0 "Q?" H 3400 2600 50 0000 R CNN +F 1 "eSim_PNP" H 3750 2800 50 0000 R CNN +F 2 "" H 3700 2650 29 0000 C CNN +F 3 "" H 3500 2550 60 0000 C CNN + 1 3500 2550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C3C +P 3900 2550 +F 0 "Q?" H 3800 2600 50 0000 R CNN +F 1 "eSim_PNP" H 4150 2800 50 0000 R CNN +F 2 "" H 4100 2650 29 0000 C CNN +F 3 "" H 3900 2550 60 0000 C CNN + 1 3900 2550 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C42 +P 5250 2300 +F 0 "Q?" H 5150 2350 50 0000 R CNN +F 1 "eSim_PNP" H 5400 2450 50 0000 R CNN +F 2 "" H 5450 2400 29 0000 C CNN +F 3 "" H 5250 2300 60 0000 C CNN + 1 5250 2300 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q? +U 1 1 632F6C48 +P 1050 4400 +F 0 "Q?" H 950 4450 50 0000 R CNN +F 1 "eSim_NPN" H 1000 4550 50 0000 R CNN +F 2 "" H 1250 4500 29 0000 C CNN +F 3 "" H 1050 4400 60 0000 C CNN + 1 1050 4400 + -1 0 0 -1 +$EndComp +$Comp +L resistor R? +U 1 1 632F6C4E +P 900 5250 +F 0 "R?" H 950 5380 50 0000 C CNN +F 1 "4.6k" H 950 5200 50 0000 C CNN +F 2 "" H 950 5230 30 0000 C CNN +F 3 "" V 950 5300 30 0000 C CNN + 1 900 5250 + 0 1 1 0 +$EndComp +$Comp +L jfet_n J? +U 1 1 632F6C54 +P 650 3550 +F 0 "J?" H 550 3600 50 0000 R CNN +F 1 "jfet_n" H 600 3700 50 0000 R CNN +F 2 "" H 850 3650 29 0000 C CNN +F 3 "" H 650 3550 60 0000 C CNN + 1 650 3550 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q? +U 1 1 632F6C5A +P 1500 4900 +F 0 "Q?" H 1400 4950 50 0000 R CNN +F 1 "eSim_NPN" H 1450 5050 50 0000 R CNN +F 2 "" H 1700 5000 29 0000 C CNN +F 3 "" H 1500 4900 60 0000 C CNN + 1 1500 4900 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D? +U 1 1 632F6C60 +P 2900 3250 +F 0 "D?" H 2900 3350 50 0000 C CNN +F 1 "eSim_Diode" H 2900 3150 50 0000 C CNN +F 2 "" H 2900 3250 60 0000 C CNN +F 3 "" H 2900 3250 60 0000 C CNN + 1 2900 3250 + 0 1 1 0 +$EndComp +$Comp +L eSim_Diode D? +U 1 1 632F6C66 +P 2650 3700 +F 0 "D?" H 2650 3800 50 0000 C CNN +F 1 "eSim_Diode" H 2650 3600 50 0000 C CNN +F 2 "" H 2650 3700 60 0000 C CNN +F 3 "" H 2650 3700 60 0000 C CNN + 1 2650 3700 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C6C +P 2650 4500 +F 0 "Q?" H 2550 4550 50 0000 R CNN +F 1 "eSim_PNP" H 2600 4650 50 0000 R CNN +F 2 "" H 2850 4600 29 0000 C CNN +F 3 "" H 2650 4500 60 0000 C CNN + 1 2650 4500 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C72 +P 3500 4100 +F 0 "Q?" H 3400 4150 50 0000 R CNN +F 1 "eSim_PNP" H 3450 4250 50 0000 R CNN +F 2 "" H 3700 4200 29 0000 C CNN +F 3 "" H 3500 4100 60 0000 C CNN + 1 3500 4100 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C78 +P 4200 4100 +F 0 "Q?" H 4100 4150 50 0000 R CNN +F 1 "eSim_PNP" H 4150 4250 50 0000 R CNN +F 2 "" H 4400 4200 29 0000 C CNN +F 3 "" H 4200 4100 60 0000 C CNN + 1 4200 4100 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D? +U 1 1 632F6C7E +P 3600 5450 +F 0 "D?" H 3600 5550 50 0000 C CNN +F 1 "eSim_Diode" H 3600 5350 50 0000 C CNN +F 2 "" H 3600 5450 60 0000 C CNN +F 3 "" H 3600 5450 60 0000 C CNN + 1 3600 5450 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q? +U 1 1 632F6C84 +P 4000 5150 +F 0 "Q?" H 3900 5200 50 0000 R CNN +F 1 "eSim_NPN" H 4050 5300 50 0000 R CNN +F 2 "" H 4200 5250 29 0000 C CNN +F 3 "" H 4000 5150 60 0000 C CNN + 1 4000 5150 + 1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D? +U 1 1 632F6C8A +P 4500 3250 +F 0 "D?" H 4500 3350 50 0000 C CNN +F 1 "eSim_Diode" H 4500 3150 50 0000 C CNN +F 2 "" H 4500 3250 60 0000 C CNN +F 3 "" H 4500 3250 60 0000 C CNN + 1 4500 3250 + 0 1 1 0 +$EndComp +$Comp +L eSim_PNP Q? +U 1 1 632F6C90 +P 4800 4450 +F 0 "Q?" H 4700 4500 50 0000 R CNN +F 1 "eSim_PNP" H 4750 4600 50 0000 R CNN +F 2 "" H 5000 4550 29 0000 C CNN +F 3 "" H 4800 4450 60 0000 C CNN + 1 4800 4450 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D? +U 1 1 632F6C96 +P 4800 3650 +F 0 "D?" H 4800 3750 50 0000 C CNN +F 1 "eSim_Diode" H 4800 3550 50 0000 C CNN +F 2 "" H 4800 3650 60 0000 C CNN +F 3 "" H 4800 3650 60 0000 C CNN + 1 4800 3650 + -1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q? +U 1 1 632F6C9C +P 5250 4800 +F 0 "Q?" H 5150 4850 50 0000 R CNN +F 1 "eSim_NPN" H 5300 4950 50 0000 R CNN +F 2 "" H 5450 4900 29 0000 C CNN +F 3 "" H 5250 4800 60 0000 C CNN + 1 5250 4800 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q? +U 1 1 632F6CA2 +P 5650 4400 +F 0 "Q?" H 5550 4450 50 0000 R CNN +F 1 "eSim_NPN" H 5700 4550 50 0000 R CNN +F 2 "" H 5850 4500 29 0000 C CNN +F 3 "" H 5650 4400 60 0000 C CNN + 1 5650 4400 + 1 0 0 -1 +$EndComp +$Comp +L resistor R? +U 1 1 632F6CA8 +P 3250 1900 +F 0 "R?" H 3300 2030 50 0000 C CNN +F 1 "2.1k" H 3300 1850 50 0000 C CNN +F 2 "" H 3300 1880 30 0000 C CNN +F 3 "" V 3300 1950 30 0000 C CNN + 1 3250 1900 + 0 1 1 0 +$EndComp +Wire Wire Line + 1250 2000 1250 2000 +Wire Wire Line + 1550 2000 1550 2300 +Wire Wire Line + 1550 2300 950 2300 +Wire Wire Line + 950 2200 950 4200 +Wire Wire Line + 950 1650 950 1800 +Wire Wire Line + 1600 2750 1600 4700 +Wire Wire Line + 2300 4900 2300 2750 +Wire Wire Line + 2900 2750 2900 3100 +Wire Wire Line + 4000 1650 4000 2350 +Wire Wire Line + 4000 2750 4000 3900 +Wire Wire Line + 5350 1650 5350 2100 +Connection ~ 4000 1650 +Wire Wire Line + 5350 2500 5350 4600 +Connection ~ 950 2300 +Wire Wire Line + 950 4600 950 5150 +Wire Wire Line + 950 5450 950 5800 +Wire Wire Line + 750 3750 750 4400 +Wire Wire Line + 450 5800 450 3550 +Wire Wire Line + 750 1650 750 3350 +Connection ~ 950 1650 +Connection ~ 1600 4400 +Wire Wire Line + 750 4400 1600 4400 +Connection ~ 1250 4400 +Wire Wire Line + 950 4900 2300 4900 +Connection ~ 950 4900 +Wire Wire Line + 1600 5800 1600 5100 +Connection ~ 950 5800 +Connection ~ 1300 4900 +Wire Wire Line + 2900 3400 2900 4100 +Wire Wire Line + 2450 1400 2450 4500 +Wire Wire Line + 2800 3700 2900 3700 +Connection ~ 2900 3700 +Wire Wire Line + 2500 3700 2450 3700 +Connection ~ 2450 3700 +Wire Wire Line + 2750 4300 2750 4100 +Wire Wire Line + 2750 4100 3300 4100 +Wire Wire Line + 2750 5800 2750 4700 +Connection ~ 1600 5800 +Connection ~ 2900 4100 +Wire Wire Line + 3600 3900 4100 3900 +Connection ~ 4000 3900 +Wire Wire Line + 3600 4300 3600 5300 +Wire Wire Line + 3600 5800 3600 5600 +Connection ~ 2750 5800 +Wire Wire Line + 3600 5150 3800 5150 +Connection ~ 3600 5150 +Wire Wire Line + 4100 5800 4100 5350 +Connection ~ 3600 5800 +Wire Wire Line + 4100 4300 4100 4950 +Wire Wire Line + 4500 2900 4500 3100 +Wire Wire Line + 4400 4100 4700 4100 +Wire Wire Line + 4700 4100 4700 4250 +Wire Wire Line + 4500 3400 4500 4100 +Connection ~ 4500 4100 +Wire Wire Line + 4700 5800 4700 4650 +Connection ~ 4100 5800 +Wire Wire Line + 4650 3650 4500 3650 +Connection ~ 4500 3650 +Wire Wire Line + 5100 4450 5000 4450 +Wire Wire Line + 5100 1400 5100 4450 +Wire Wire Line + 5100 3650 4950 3650 +Connection ~ 5100 3650 +Wire Wire Line + 5050 4800 4100 4800 +Connection ~ 4100 4800 +Wire Wire Line + 5350 5800 5350 5000 +Connection ~ 4700 5800 +Wire Wire Line + 5450 4400 5350 4400 +Connection ~ 5350 4400 +Wire Wire Line + 5750 5800 5750 4600 +Connection ~ 5350 5800 +Wire Wire Line + 5750 4200 5750 1500 +Connection ~ 750 1650 +$Comp +L PORT U? +U 1 1 632F6D0D +P 2200 1400 +F 0 "U?" H 2250 1500 30 0000 C CNN +F 1 "PORT" H 2200 1400 30 0000 C CNN +F 2 "" H 2200 1400 60 0000 C CNN +F 3 "" H 2200 1400 60 0000 C CNN + 1 2200 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U? +U 1 1 632F6D13 +P 4850 1400 +F 0 "U?" H 4900 1500 30 0000 C CNN +F 1 "PORT" H 4850 1400 30 0000 C CNN +F 2 "" H 4850 1400 60 0000 C CNN +F 3 "" H 4850 1400 60 0000 C CNN + 1 4850 1400 + 1 0 0 -1 +$EndComp +$Comp +L PORT U? +U 1 1 632F6D19 +P 5750 1250 +F 0 "U?" H 5800 1350 30 0000 C CNN +F 1 "PORT" H 5750 1250 30 0000 C CNN +F 2 "" H 5750 1250 60 0000 C CNN +F 3 "" H 5750 1250 60 0000 C CNN + 1 5750 1250 + 0 1 1 0 +$EndComp +Wire Wire Line + 1600 2350 1600 1900 +Wire Wire Line + 1600 1900 2300 1900 +Wire Wire Line + 2300 1900 2300 2350 +Wire Wire Line + 2000 1900 2000 1650 +Connection ~ 2000 1650 +Connection ~ 2000 1900 +Wire Wire Line + 1900 2550 2000 2550 +Wire Wire Line + 1550 2150 1950 2150 +Wire Wire Line + 1950 2150 1950 2550 +Connection ~ 1950 2550 +Connection ~ 1550 2150 +$Comp +L eSim_PNP Q? +U 1 1 632F6D2D +P 3000 2550 +F 0 "Q?" H 2900 2600 50 0000 R CNN +F 1 "eSim_PNP" H 3300 2800 50 0000 R CNN +F 2 "" H 3200 2650 29 0000 C CNN +F 3 "" H 3000 2550 60 0000 C CNN + 1 3000 2550 + -1 0 0 1 +$EndComp +Wire Wire Line + 3200 2550 3300 2550 +Wire Wire Line + 1950 2300 5050 2300 +Wire Wire Line + 3250 2300 3250 2550 +Connection ~ 3250 2550 +Connection ~ 1950 2300 +Wire Wire Line + 3300 1800 3300 1650 +Connection ~ 3300 1650 +Wire Wire Line + 2900 2350 2900 2200 +Wire Wire Line + 2900 2200 3600 2200 +Wire Wire Line + 3600 2200 3600 2350 +Wire Wire Line + 3300 2200 3300 2100 +Connection ~ 3300 2200 +Wire Wire Line + 4500 2900 3600 2900 +Wire Wire Line + 3600 2900 3600 2750 +Wire Wire Line + 3700 2300 3700 2550 +Connection ~ 3250 2300 +Connection ~ 3700 2300 +Connection ~ 5350 1650 +Connection ~ 5750 5800 +Connection ~ 6000 5800 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM393/LM393.sub b/library/SubcircuitLibrary/LM393/LM393.sub new file mode 100644 index 000000000..b854038fb --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393.sub @@ -0,0 +1,60 @@ +* Subcircuit LM393 +.subckt LM393 net-_j1-pad1_ net-_d1-pad1_ net-_d5-pad1_ net-_q16-pad1_ net-_d3-pad2_ net-_d6-pad1_ net-_d10-pad1_ net-_q32-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\lm393\lm393.cir +.include PNP.lib +.include NPN.lib +.include NJF.lib +.include D.lib +q1 net-_q1-pad1_ net-_q1-pad2_ net-_j1-pad1_ Q2N2907A +r2 net-_q1-pad2_ net-_q1-pad1_ 2k +q4 net-_j1-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q5 net-_q2-pad3_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q8 net-_d4-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q10 net-_q10-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q14 net-_q14-pad1_ net-_q1-pad1_ net-_j1-pad1_ Q2N2907A +q2 net-_q1-pad1_ net-_j1-pad3_ net-_q2-pad3_ Q2N2222 +r1 net-_q2-pad3_ net-_d3-pad2_ 4.6k +j1 net-_j1-pad1_ net-_d3-pad2_ net-_j1-pad3_ J2N3819 +q3 net-_j1-pad3_ net-_q2-pad3_ net-_d3-pad2_ Q2N2222 +d2 net-_d2-pad1_ net-_d1-pad2_ 1N4148 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q6 net-_d3-pad2_ net-_d1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_d3-pad1_ net-_d1-pad2_ net-_q10-pad1_ Q2N2907A +q12 net-_q11-pad1_ net-_d4-pad2_ net-_q10-pad1_ Q2N2907A +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +q11 net-_q11-pad1_ net-_d3-pad1_ net-_d3-pad2_ Q2N2222 +d4 net-_d4-pad1_ net-_d4-pad2_ 1N4148 +q13 net-_d3-pad2_ net-_d5-pad1_ net-_d4-pad2_ Q2N2907A +d5 net-_d5-pad1_ net-_d4-pad2_ 1N4148 +q15 net-_q14-pad1_ net-_q11-pad1_ net-_d3-pad2_ Q2N2222 +q16 net-_q16-pad1_ net-_q14-pad1_ net-_d3-pad2_ Q2N2222 +r3 net-_j1-pad1_ net-_q7-pad3_ 2.1k +q7 net-_d2-pad1_ net-_q1-pad1_ net-_q7-pad3_ Q2N2907A +q17 net-_q17-pad1_ net-_q17-pad2_ net-_j1-pad1_ Q2N2907A +r5 net-_q17-pad2_ net-_q17-pad1_ 2k +q20 net-_j2-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q21 net-_q18-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q24 net-_d9-pad1_ net-_q17-pad1_ net-_q23-pad3_ Q2N2907A +q26 net-_q25-pad3_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q30 net-_q30-pad1_ net-_q17-pad1_ net-_j1-pad1_ Q2N2907A +q18 net-_q17-pad1_ net-_j2-pad3_ net-_q18-pad3_ Q2N2222 +r4 net-_q18-pad3_ net-_d3-pad2_ 4.6k +j2 net-_j1-pad1_ net-_d3-pad2_ net-_j2-pad3_ J2N3819 +q19 net-_j2-pad3_ net-_q18-pad3_ net-_d3-pad2_ Q2N2222 +d7 net-_d7-pad1_ net-_d6-pad2_ 1N4148 +d6 net-_d6-pad1_ net-_d6-pad2_ 1N4148 +q22 net-_d3-pad2_ net-_d6-pad1_ net-_d6-pad2_ Q2N2907A +q25 net-_d8-pad1_ net-_d6-pad2_ net-_q25-pad3_ Q2N2907A +q28 net-_q27-pad1_ net-_d10-pad2_ net-_q25-pad3_ Q2N2907A +d8 net-_d8-pad1_ net-_d3-pad2_ 1N4148 +q27 net-_q27-pad1_ net-_d8-pad1_ net-_d3-pad2_ Q2N2222 +d9 net-_d9-pad1_ net-_d10-pad2_ 1N4148 +q29 net-_d3-pad2_ net-_d10-pad1_ net-_d10-pad2_ Q2N2907A +d10 net-_d10-pad1_ net-_d10-pad2_ 1N4148 +q31 net-_q30-pad1_ net-_q27-pad1_ net-_d3-pad2_ Q2N2222 +q32 net-_q32-pad1_ net-_q30-pad1_ net-_d3-pad2_ Q2N2222 +r6 net-_j1-pad1_ net-_q23-pad3_ 2.1k +q23 net-_d7-pad1_ net-_q17-pad1_ net-_q23-pad3_ Q2N2907A +* Control Statements + +.ends LM393 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM393/LM393_Previous_Values.xml b/library/SubcircuitLibrary/LM393/LM393_Previous_Values.xml new file mode 100644 index 000000000..babb60e4c --- /dev/null +++ b/library/SubcircuitLibrary/LM393/LM393_Previous_Values.xml @@ -0,0 +1 @@ +C:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM393/NJF.lib b/library/SubcircuitLibrary/LM393/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM393/NPN.lib b/library/SubcircuitLibrary/LM393/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LM393/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM393/PNP.lib b/library/SubcircuitLibrary/LM393/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/LM393/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM393/README.md b/library/SubcircuitLibrary/LM393/README.md new file mode 100644 index 000000000..d0b0abaf1 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/README.md @@ -0,0 +1,35 @@ + +# LM393 Comparator IC + +LM393 is a Low power, low offset voltage comparator IC. It has two channels sharing common biasing. It is a high precision comparator with a low offset voltage of 2 mV. It has various applications such as in limit comparators, A/D convertors, wave shaping circuits etc. + + +## Usage/Examples + +Basic Comparator + +CMOS/TTL Driver + +Pulse Train Generator + +Crystal Controlled Oscillator + +Positive/Negative Floating Regulator + +Two-Decade High Frequency VCO + + +## Documentation + +To know the details of LM393 IC please refer to this link [LM393_datasheet.](https://www.ti.com/lit/ds/symlink/lm393-n.pdf?ts=1665939843518&ref_url=https%253A%252F%252Fwww.google.com%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/LM393/analysis b/library/SubcircuitLibrary/LM393/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/LM393/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM723/D.lib b/library/SubcircuitLibrary/LM723/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/LM723/LM723-cache.lib b/library/SubcircuitLibrary/LM723/LM723-cache.lib new file mode 100644 index 000000000..3dddd3f67 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723-cache.lib @@ -0,0 +1,182 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NJF +# +DEF eSim_NJF J 0 0 Y N 1 F N +F0 "J" -100 50 50 H V R CNN +F1 "eSim_NJF" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS jfet_n +DRAW +C 50 0 111 0 1 10 N +P 3 0 1 10 10 75 10 -75 10 -75 N +P 3 0 1 0 100 -100 100 -50 10 -50 N +P 3 0 1 0 100 100 100 55 10 55 N +P 4 0 1 0 0 0 -40 15 -40 -15 0 0 F +X D 1 100 200 100 D 50 50 1 1 P +X G 2 -200 0 210 R 50 50 1 1 P +X S 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +# zener +# +DEF zener U 0 40 Y Y 1 F N +F0 "U" -50 -100 60 H V C CNN +F1 "zener" 0 100 60 H V C CNN +F2 "" 50 0 60 H V C CNN +F3 "" 50 0 60 H V C CNN +DRAW +P 2 0 1 0 100 -50 50 -100 N +P 2 0 1 0 100 50 100 -50 N +P 2 0 1 0 100 50 150 100 N +P 4 0 1 0 0 50 0 -50 100 0 0 50 N +X ~ IN -200 0 200 R 50 43 1 1 I +X ~ OUT 300 0 200 L 50 43 1 1 O +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/LM723/LM723.cir b/library/SubcircuitLibrary/LM723/LM723.cir new file mode 100644 index 000000000..d513ed3eb --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.cir @@ -0,0 +1,69 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\LM723\LM723.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 07/28/22 22:27:49 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +U1 Net-_J1-Pad3_ /V+ zener +R2 /V+ Net-_Q4-Pad3_ 900 +R5 Net-_Q25-Pad3_ /V+ 550 +Q4 Net-_Q14-Pad2_ Net-_Q14-Pad2_ Net-_Q4-Pad3_ eSim_PNP +Q5 Net-_C1-Pad2_ Net-_Q14-Pad2_ Net-_Q25-Pad3_ eSim_PNP +R3 Net-_Q14-Pad2_ Net-_J1-Pad3_ 22k +Q8 /V+ Net-_C1-Pad2_ /Vref eSim_NPN +Q2 /V- Net-_D1-Pad1_ Net-_Q2-Pad3_ eSim_PNP +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +Q7 /V- Net-_C1-Pad1_ Net-_D1-Pad2_ eSim_PNP +Q9 Net-_C1-Pad1_ Net-_Q11-Pad1_ /Vref eSim_PNP +Q11 Net-_Q11-Pad1_ Net-_C2-Pad1_ /Vref eSim_PNP +R8 Net-_Q11-Pad1_ Net-_C2-Pad1_ 1.8k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 10p +C2 Net-_C2-Pad1_ Net-_C1-Pad2_ 5p +U2 /V- Net-_C1-Pad2_ zener +R16 /V+ Net-_Q14-Pad3_ 1.8k +R18 Net-_Q16-Pad3_ /V+ 1.8k +Q14 Net-_Q14-Pad1_ Net-_Q14-Pad2_ Net-_Q14-Pad3_ eSim_PNP +Q16 /Compensation Net-_Q14-Pad2_ Net-_Q16-Pad3_ eSim_PNP +Q19 /V+ /Compensation Net-_Q19-Pad3_ eSim_NPN +Q23 /Vc Net-_Q19-Pad3_ /Vout eSim_NPN +R21 Net-_Q19-Pad3_ /Vout 15k +U3 /Vz /Vout zener +Q12 Net-_Q11-Pad1_ Net-_D2-Pad2_ Net-_Q12-Pad3_ eSim_NPN +Q10 Net-_C1-Pad1_ Net-_D2-Pad2_ Net-_D2-Pad1_ eSim_NPN +D2 Net-_D2-Pad1_ Net-_D2-Pad2_ eSim_Diode +R9 Net-_D2-Pad1_ Net-_Q12-Pad3_ 2k +R6 Net-_D2-Pad1_ Net-_R6-Pad2_ 11k +R7 Net-_R6-Pad2_ /V- 1k +Q6 Net-_J1-Pad3_ Net-_Q17-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q3 Net-_J1-Pad3_ Net-_J1-Pad1_ Net-_Q1-Pad2_ eSim_NPN +Q1 Net-_J1-Pad1_ Net-_Q1-Pad2_ /V- eSim_NPN +R1 Net-_Q1-Pad2_ /V- 2.4k +R4 Net-_Q6-Pad3_ /V- 160 +R10 /Vref Net-_Q13-Pad1_ 409 +R11 Net-_Q13-Pad1_ Net-_D2-Pad2_ 11.89k +R12 Net-_D2-Pad2_ Net-_Q15-Pad2_ 1.1k +R13 Net-_Q15-Pad2_ Net-_Q13-Pad2_ 380 +R14 Net-_Q13-Pad2_ /V- 1.1k +Q15 Net-_Q13-Pad1_ Net-_Q15-Pad2_ Net-_Q15-Pad3_ eSim_NPN +R17 Net-_Q15-Pad3_ /V- 1.1k +Q13 Net-_Q13-Pad1_ Net-_Q13-Pad2_ Net-_Q13-Pad3_ eSim_NPN +R15 Net-_Q13-Pad3_ /V- 1.7k +Q17 Net-_Q14-Pad1_ Net-_Q17-Pad2_ Net-_Q17-Pad3_ eSim_NPN +R19 Net-_Q17-Pad3_ /V- 300 +Q18 /Vref Net-_Q14-Pad1_ Net-_Q17-Pad2_ eSim_NPN +R20 Net-_Q17-Pad2_ /V- 10k +Q24 /Compensation Net-_Q24-Pad2_ /Current_sense eSim_NPN +R24 /Current_limit Net-_Q24-Pad2_ 400 +Q22 /Compensation /Inverting_input Net-_Q20-Pad3_ eSim_NPN +Q20 /Vref /Non-inverting_input Net-_Q20-Pad3_ eSim_NPN +Q21 Net-_Q20-Pad3_ Net-_Q17-Pad2_ Net-_Q21-Pad3_ eSim_NPN +R22 Net-_Q21-Pad3_ /V- 300 +R23 Net-_Q26-Pad3_ /V- 300 +U4 /V+ /Vc /Vout /Vz /Vref /Compensation /Current_limit /Current_sense /Inverting_input /Non-inverting_input ? ? ? /V- PORT +J1 Net-_J1-Pad1_ /V- Net-_J1-Pad3_ jfet_n +Q25 Net-_Q2-Pad3_ Net-_Q14-Pad2_ Net-_Q25-Pad3_ eSim_PNP +Q26 Net-_Q20-Pad3_ Net-_Q17-Pad2_ Net-_Q26-Pad3_ eSim_NPN + +.end diff --git a/library/SubcircuitLibrary/LM723/LM723.cir.out b/library/SubcircuitLibrary/LM723/LM723.cir.out new file mode 100644 index 000000000..6530b650b --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.cir.out @@ -0,0 +1,83 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm723\lm723.cir + +.include D.lib +.include PNP.lib +.include NJF.lib +.include NPN.lib +* u1 net-_j1-pad3_ /v+ zener +r2 /v+ net-_q4-pad3_ 900 +r5 net-_q25-pad3_ /v+ 550 +q4 net-_q14-pad2_ net-_q14-pad2_ net-_q4-pad3_ Q2N2907A +q5 net-_c1-pad2_ net-_q14-pad2_ net-_q25-pad3_ Q2N2907A +r3 net-_q14-pad2_ net-_j1-pad3_ 22k +q8 /v+ net-_c1-pad2_ /vref Q2N2222 +q2 /v- net-_d1-pad1_ net-_q2-pad3_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q7 /v- net-_c1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_c1-pad1_ net-_q11-pad1_ /vref Q2N2907A +q11 net-_q11-pad1_ net-_c2-pad1_ /vref Q2N2907A +r8 net-_q11-pad1_ net-_c2-pad1_ 1.8k +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +c2 net-_c2-pad1_ net-_c1-pad2_ 5p +* u2 /v- net-_c1-pad2_ zener +r16 /v+ net-_q14-pad3_ 1.8k +r18 net-_q16-pad3_ /v+ 1.8k +q14 net-_q14-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2907A +q16 /compensation net-_q14-pad2_ net-_q16-pad3_ Q2N2907A +q19 /v+ /compensation net-_q19-pad3_ Q2N2222 +q23 /vc net-_q19-pad3_ /vout Q2N2222 +r21 net-_q19-pad3_ /vout 15k +* u3 /vz /vout zener +q12 net-_q11-pad1_ net-_d2-pad2_ net-_q12-pad3_ Q2N2222 +q10 net-_c1-pad1_ net-_d2-pad2_ net-_d2-pad1_ Q2N2222 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r9 net-_d2-pad1_ net-_q12-pad3_ 2k +r6 net-_d2-pad1_ net-_r6-pad2_ 11k +r7 net-_r6-pad2_ /v- 1k +q6 net-_j1-pad3_ net-_q17-pad2_ net-_q6-pad3_ Q2N2222 +q3 net-_j1-pad3_ net-_j1-pad1_ net-_q1-pad2_ Q2N2222 +q1 net-_j1-pad1_ net-_q1-pad2_ /v- Q2N2222 +r1 net-_q1-pad2_ /v- 2.4k +r4 net-_q6-pad3_ /v- 160 +r10 /vref net-_q13-pad1_ 409 +r11 net-_q13-pad1_ net-_d2-pad2_ 11.89k +r12 net-_d2-pad2_ net-_q15-pad2_ 1.1k +r13 net-_q15-pad2_ net-_q13-pad2_ 380 +r14 net-_q13-pad2_ /v- 1.1k +q15 net-_q13-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222 +r17 net-_q15-pad3_ /v- 1.1k +q13 net-_q13-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +r15 net-_q13-pad3_ /v- 1.7k +q17 net-_q14-pad1_ net-_q17-pad2_ net-_q17-pad3_ Q2N2222 +r19 net-_q17-pad3_ /v- 300 +q18 /vref net-_q14-pad1_ net-_q17-pad2_ Q2N2222 +r20 net-_q17-pad2_ /v- 10k +q24 /compensation net-_q24-pad2_ /current_sense Q2N2222 +r24 /current_limit net-_q24-pad2_ 400 +q22 /compensation /inverting_input net-_q20-pad3_ Q2N2222 +q20 /vref /non-inverting_input net-_q20-pad3_ Q2N2222 +q21 net-_q20-pad3_ net-_q17-pad2_ net-_q21-pad3_ Q2N2222 +r22 net-_q21-pad3_ /v- 300 +r23 net-_q26-pad3_ /v- 300 +* u4 /v+ /vc /vout /vz /vref /compensation /current_limit /current_sense /inverting_input /non-inverting_input ? ? ? /v- port +j1 net-_j1-pad1_ /v- net-_j1-pad3_ J2N3819 +q25 net-_q2-pad3_ net-_q14-pad2_ net-_q25-pad3_ Q2N2907A +q26 net-_q20-pad3_ net-_q17-pad2_ net-_q26-pad3_ Q2N2222 +a1 net-_j1-pad3_ /v+ u1 +a2 /v- net-_c1-pad2_ u2 +a3 /vz /vout u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.7 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/LM723/LM723.pro b/library/SubcircuitLibrary/LM723/LM723.pro new file mode 100644 index 000000000..b033facd5 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:28:26 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/LM723/LM723.sch b/library/SubcircuitLibrary/LM723/LM723.sch new file mode 100644 index 000000000..98e57d334 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.sch @@ -0,0 +1,1388 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:LM723-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L zener U1 +U 1 1 62BC8919 +P 900 1400 +F 0 "U1" H 850 1300 60 0000 C CNN +F 1 "zener" H 900 1500 60 0000 C CNN +F 2 "" H 950 1400 60 0000 C CNN +F 3 "" H 950 1400 60 0000 C CNN + 1 900 1400 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 62BC891A +P 1550 800 +F 0 "R2" H 1600 930 50 0000 C CNN +F 1 "900" H 1600 750 50 0000 C CNN +F 2 "" H 1600 780 30 0000 C CNN +F 3 "" V 1600 850 30 0000 C CNN + 1 1550 800 + 0 1 1 0 +$EndComp +$Comp +L resistor R5 +U 1 1 62BC891B +P 2650 900 +F 0 "R5" H 2700 1030 50 0000 C CNN +F 1 "550" H 2700 850 50 0000 C CNN +F 2 "" H 2700 880 30 0000 C CNN +F 3 "" V 2700 950 30 0000 C CNN + 1 2650 900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q4 +U 1 1 62BC891C +P 1700 1400 +F 0 "Q4" H 1600 1450 50 0000 R CNN +F 1 "eSim_PNP" H 1650 1550 50 0000 R CNN +F 2 "" H 1900 1500 29 0000 C CNN +F 3 "" H 1700 1400 60 0000 C CNN + 1 1700 1400 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q5 +U 1 1 62BC891D +P 2500 1400 +F 0 "Q5" H 2400 1450 50 0000 R CNN +F 1 "eSim_PNP" H 2450 1550 50 0000 R CNN +F 2 "" H 2700 1500 29 0000 C CNN +F 3 "" H 2500 1400 60 0000 C CNN + 1 2500 1400 + 1 0 0 1 +$EndComp +$Comp +L resistor R3 +U 1 1 62BC891E +P 1550 1800 +F 0 "R3" H 1600 1930 50 0000 C CNN +F 1 "22k" H 1600 1750 50 0000 C CNN +F 2 "" H 1600 1780 30 0000 C CNN +F 3 "" V 1600 1850 30 0000 C CNN + 1 1550 1800 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q8 +U 1 1 62BC891F +P 3000 1650 +F 0 "Q8" H 2900 1700 50 0000 R CNN +F 1 "eSim_NPN" H 2950 1800 50 0000 R CNN +F 2 "" H 3200 1750 29 0000 C CNN +F 3 "" H 3000 1650 60 0000 C CNN + 1 3000 1650 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q2 +U 1 1 62BC8920 +P 1300 2500 +F 0 "Q2" H 1200 2550 50 0000 R CNN +F 1 "eSim_PNP" H 1250 2650 50 0000 R CNN +F 2 "" H 1500 2600 29 0000 C CNN +F 3 "" H 1300 2500 60 0000 C CNN + 1 1300 2500 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D1 +U 1 1 62BC8921 +P 1900 2500 +F 0 "D1" H 1900 2600 50 0000 C CNN +F 1 "eSim_Diode" H 1900 2400 50 0000 C CNN +F 2 "" H 1900 2500 60 0000 C CNN +F 3 "" H 1900 2500 60 0000 C CNN + 1 1900 2500 + 1 0 0 -1 +$EndComp +$Comp +L eSim_PNP Q7 +U 1 1 62BC8922 +P 2700 2750 +F 0 "Q7" H 2600 2800 50 0000 R CNN +F 1 "eSim_PNP" H 2650 2900 50 0000 R CNN +F 2 "" H 2900 2850 29 0000 C CNN +F 3 "" H 2700 2750 60 0000 C CNN + 1 2700 2750 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 62BC8923 +P 3550 2150 +F 0 "Q9" H 3450 2200 50 0000 R CNN +F 1 "eSim_PNP" H 3500 2300 50 0000 R CNN +F 2 "" H 3750 2250 29 0000 C CNN +F 3 "" H 3550 2150 60 0000 C CNN + 1 3550 2150 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q11 +U 1 1 62BC8924 +P 4500 2150 +F 0 "Q11" H 4400 2200 50 0000 R CNN +F 1 "eSim_PNP" H 4450 2300 50 0000 R CNN +F 2 "" H 4700 2250 29 0000 C CNN +F 3 "" H 4500 2150 60 0000 C CNN + 1 4500 2150 + 1 0 0 1 +$EndComp +$Comp +L resistor R8 +U 1 1 62BC8925 +P 4000 2200 +F 0 "R8" H 4050 2330 50 0000 C CNN +F 1 "1.8k" H 4050 2150 50 0000 C CNN +F 2 "" H 4050 2180 30 0000 C CNN +F 3 "" V 4050 2250 30 0000 C CNN + 1 4000 2200 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C1 +U 1 1 62BC8926 +P 3250 2900 +F 0 "C1" H 3275 3000 50 0000 L CNN +F 1 "10p" H 3275 2800 50 0000 L CNN +F 2 "" H 3288 2750 30 0000 C CNN +F 3 "" H 3250 2900 60 0000 C CNN + 1 3250 2900 + 1 0 0 -1 +$EndComp +$Comp +L capacitor C2 +U 1 1 62BC8927 +P 4300 2900 +F 0 "C2" H 4325 3000 50 0000 L CNN +F 1 "5p" H 4325 2800 50 0000 L CNN +F 2 "" H 4338 2750 30 0000 C CNN +F 3 "" H 4300 2900 60 0000 C CNN + 1 4300 2900 + 1 0 0 -1 +$EndComp +$Comp +L zener U2 +U 1 1 62BC8928 +P 2900 3500 +F 0 "U2" H 2850 3400 60 0000 C CNN +F 1 "zener" H 2900 3600 60 0000 C CNN +F 2 "" H 2950 3500 60 0000 C CNN +F 3 "" H 2950 3500 60 0000 C CNN + 1 2900 3500 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R16 +U 1 1 62BC8929 +P 6050 800 +F 0 "R16" H 6100 930 50 0000 C CNN +F 1 "1.8k" H 6100 750 50 0000 C CNN +F 2 "" H 6100 780 30 0000 C CNN +F 3 "" V 6100 850 30 0000 C CNN + 1 6050 800 + 0 1 1 0 +$EndComp +$Comp +L resistor R18 +U 1 1 62BC892A +P 6950 900 +F 0 "R18" H 7000 1030 50 0000 C CNN +F 1 "1.8k" H 7000 850 50 0000 C CNN +F 2 "" H 7000 880 30 0000 C CNN +F 3 "" V 7000 950 30 0000 C CNN + 1 6950 900 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_PNP Q14 +U 1 1 62BC892B +P 6000 1350 +F 0 "Q14" H 5900 1400 50 0000 R CNN +F 1 "eSim_PNP" H 5950 1500 50 0000 R CNN +F 2 "" H 6200 1450 29 0000 C CNN +F 3 "" H 6000 1350 60 0000 C CNN + 1 6000 1350 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q16 +U 1 1 62BC892C +P 6800 1350 +F 0 "Q16" H 6700 1400 50 0000 R CNN +F 1 "eSim_PNP" H 6750 1500 50 0000 R CNN +F 2 "" H 7000 1450 29 0000 C CNN +F 3 "" H 6800 1350 60 0000 C CNN + 1 6800 1350 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q19 +U 1 1 62BC892D +P 7750 1350 +F 0 "Q19" H 7650 1400 50 0000 R CNN +F 1 "eSim_NPN" H 7700 1500 50 0000 R CNN +F 2 "" H 7950 1450 29 0000 C CNN +F 3 "" H 7750 1350 60 0000 C CNN + 1 7750 1350 + 1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q23 +U 1 1 62BC892E +P 8700 1350 +F 0 "Q23" H 8600 1400 50 0000 R CNN +F 1 "eSim_NPN" H 8650 1500 50 0000 R CNN +F 2 "" H 8900 1450 29 0000 C CNN +F 3 "" H 8700 1350 60 0000 C CNN + 1 8700 1350 + 1 0 0 -1 +$EndComp +$Comp +L resistor R21 +U 1 1 62BC892F +P 7800 1900 +F 0 "R21" H 7850 2030 50 0000 C CNN +F 1 "15k" H 7850 1850 50 0000 C CNN +F 2 "" H 7850 1880 30 0000 C CNN +F 3 "" V 7850 1950 30 0000 C CNN + 1 7800 1900 + 0 1 1 0 +$EndComp +$Comp +L zener U3 +U 1 1 62BC8930 +P 8850 2150 +F 0 "U3" H 8800 2050 60 0000 C CNN +F 1 "zener" H 8850 2250 60 0000 C CNN +F 2 "" H 8900 2150 60 0000 C CNN +F 3 "" H 8900 2150 60 0000 C CNN + 1 8850 2150 + 0 -1 -1 0 +$EndComp +$Comp +L eSim_NPN Q12 +U 1 1 62BC8931 +P 4700 4500 +F 0 "Q12" H 4600 4550 50 0000 R CNN +F 1 "eSim_NPN" H 4650 4650 50 0000 R CNN +F 2 "" H 4900 4600 29 0000 C CNN +F 3 "" H 4700 4500 60 0000 C CNN + 1 4700 4500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q10 +U 1 1 62BC8932 +P 3550 4500 +F 0 "Q10" H 3450 4550 50 0000 R CNN +F 1 "eSim_NPN" H 3500 4650 50 0000 R CNN +F 2 "" H 3750 4600 29 0000 C CNN +F 3 "" H 3550 4500 60 0000 C CNN + 1 3550 4500 + -1 0 0 -1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 62BC8933 +P 3850 4800 +F 0 "D2" H 3850 4900 50 0000 C CNN +F 1 "eSim_Diode" H 3850 4700 50 0000 C CNN +F 2 "" H 3850 4800 60 0000 C CNN +F 3 "" H 3850 4800 60 0000 C CNN + 1 3850 4800 + 0 -1 -1 0 +$EndComp +$Comp +L resistor R9 +U 1 1 62BC8934 +P 4200 5000 +F 0 "R9" H 4250 5130 50 0000 C CNN +F 1 "2k" H 4250 4950 50 0000 C CNN +F 2 "" H 4250 4980 30 0000 C CNN +F 3 "" V 4250 5050 30 0000 C CNN + 1 4200 5000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R6 +U 1 1 62BC8935 +P 3400 5250 +F 0 "R6" H 3450 5380 50 0000 C CNN +F 1 "11k" H 3450 5200 50 0000 C CNN +F 2 "" H 3450 5230 30 0000 C CNN +F 3 "" V 3450 5300 30 0000 C CNN + 1 3400 5250 + 0 1 1 0 +$EndComp +$Comp +L resistor R7 +U 1 1 62BC8936 +P 3400 6050 +F 0 "R7" H 3450 6180 50 0000 C CNN +F 1 "1k" H 3450 6000 50 0000 C CNN +F 2 "" H 3450 6030 30 0000 C CNN +F 3 "" V 3450 6100 30 0000 C CNN + 1 3400 6050 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q6 +U 1 1 62BC8937 +P 2600 5600 +F 0 "Q6" H 2500 5650 50 0000 R CNN +F 1 "eSim_NPN" H 2550 5750 50 0000 R CNN +F 2 "" H 2800 5700 29 0000 C CNN +F 3 "" H 2600 5600 60 0000 C CNN + 1 2600 5600 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q3 +U 1 1 62BC8938 +P 1650 5400 +F 0 "Q3" H 1550 5450 50 0000 R CNN +F 1 "eSim_NPN" H 1600 5550 50 0000 R CNN +F 2 "" H 1850 5500 29 0000 C CNN +F 3 "" H 1650 5400 60 0000 C CNN + 1 1650 5400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 62BC8939 +P 1000 5800 +F 0 "Q1" H 900 5850 50 0000 R CNN +F 1 "eSim_NPN" H 950 5950 50 0000 R CNN +F 2 "" H 1200 5900 29 0000 C CNN +F 3 "" H 1000 5800 60 0000 C CNN + 1 1000 5800 + -1 0 0 -1 +$EndComp +$Comp +L resistor R1 +U 1 1 62BC893B +P 1500 6050 +F 0 "R1" H 1550 6180 50 0000 C CNN +F 1 "2.4k" H 1550 6000 50 0000 C CNN +F 2 "" H 1550 6030 30 0000 C CNN +F 3 "" V 1550 6100 30 0000 C CNN + 1 1500 6050 + 0 1 1 0 +$EndComp +$Comp +L resistor R4 +U 1 1 62BC893C +P 2450 6050 +F 0 "R4" H 2500 6180 50 0000 C CNN +F 1 "160" H 2500 6000 50 0000 C CNN +F 2 "" H 2500 6030 30 0000 C CNN +F 3 "" V 2500 6100 30 0000 C CNN + 1 2450 6050 + 0 1 1 0 +$EndComp +$Comp +L resistor R10 +U 1 1 62BC893D +P 5250 3150 +F 0 "R10" H 5300 3280 50 0000 C CNN +F 1 "409" H 5300 3100 50 0000 C CNN +F 2 "" H 5300 3130 30 0000 C CNN +F 3 "" V 5300 3200 30 0000 C CNN + 1 5250 3150 + 0 1 1 0 +$EndComp +$Comp +L resistor R11 +U 1 1 62BC893E +P 5250 3650 +F 0 "R11" H 5300 3780 50 0000 C CNN +F 1 "11.89k" H 5300 3600 50 0000 C CNN +F 2 "" H 5300 3630 30 0000 C CNN +F 3 "" V 5300 3700 30 0000 C CNN + 1 5250 3650 + 0 1 1 0 +$EndComp +$Comp +L resistor R12 +U 1 1 62BC893F +P 5250 4650 +F 0 "R12" H 5300 4780 50 0000 C CNN +F 1 "1.1k" H 5300 4600 50 0000 C CNN +F 2 "" H 5300 4630 30 0000 C CNN +F 3 "" V 5300 4700 30 0000 C CNN + 1 5250 4650 + 0 1 1 0 +$EndComp +$Comp +L resistor R13 +U 1 1 62BC8940 +P 5250 5250 +F 0 "R13" H 5300 5380 50 0000 C CNN +F 1 "380" H 5300 5200 50 0000 C CNN +F 2 "" H 5300 5230 30 0000 C CNN +F 3 "" V 5300 5300 30 0000 C CNN + 1 5250 5250 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 62BC8941 +P 5250 6000 +F 0 "R14" H 5300 6130 50 0000 C CNN +F 1 "1.1k" H 5300 5950 50 0000 C CNN +F 2 "" H 5300 5980 30 0000 C CNN +F 3 "" V 5300 6050 30 0000 C CNN + 1 5250 6000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q15 +U 1 1 62BC8942 +P 6450 5000 +F 0 "Q15" H 6350 5050 50 0000 R CNN +F 1 "eSim_NPN" H 6400 5150 50 0000 R CNN +F 2 "" H 6650 5100 29 0000 C CNN +F 3 "" H 6450 5000 60 0000 C CNN + 1 6450 5000 + 1 0 0 -1 +$EndComp +$Comp +L resistor R17 +U 1 1 62BC8943 +P 6500 6000 +F 0 "R17" H 6550 6130 50 0000 C CNN +F 1 "1.1k" H 6550 5950 50 0000 C CNN +F 2 "" H 6550 5980 30 0000 C CNN +F 3 "" V 6550 6050 30 0000 C CNN + 1 6500 6000 + 0 1 1 0 +$EndComp +$Comp +L eSim_NPN Q13 +U 1 1 62BC8944 +P 5850 5550 +F 0 "Q13" H 5750 5600 50 0000 R CNN +F 1 "eSim_NPN" H 5800 5700 50 0000 R CNN +F 2 "" H 6050 5650 29 0000 C CNN +F 3 "" H 5850 5550 60 0000 C CNN + 1 5850 5550 + 1 0 0 -1 +$EndComp +Wire Wire Line + 900 600 1600 600 +Wire Wire Line + 1600 600 2600 600 +Wire Wire Line + 2600 600 3100 600 +Wire Wire Line + 3100 600 6100 600 +Wire Wire Line + 6100 600 6900 600 +Wire Wire Line + 6900 600 7850 600 +Wire Wire Line + 7850 600 9700 600 +Connection ~ 2600 600 +Wire Wire Line + 2600 700 2600 600 +Wire Wire Line + 1600 700 1600 600 +Wire Wire Line + 900 600 900 1100 +Connection ~ 1600 600 +Wire Wire Line + 1600 1200 1600 1000 +Wire Wire Line + 2600 1000 2600 1100 +Wire Wire Line + 2600 1100 2600 1200 +Wire Wire Line + 1900 1400 2000 1400 +Wire Wire Line + 2000 1400 2050 1400 +Wire Wire Line + 2050 1400 2100 1400 +Wire Wire Line + 2100 1400 2300 1400 +Wire Wire Line + 1600 1600 1600 1650 +Wire Wire Line + 1600 1650 1600 1700 +Wire Wire Line + 1600 2150 1600 2000 +Wire Wire Line + 1600 1650 2000 1650 +Wire Wire Line + 2000 1650 2000 1400 +Connection ~ 2000 1400 +Connection ~ 1600 1650 +Wire Wire Line + 2600 1600 2600 1650 +Wire Wire Line + 2600 1650 2600 2250 +Wire Wire Line + 2600 1650 2800 1650 +Wire Wire Line + 3750 2150 3800 2150 +Wire Wire Line + 3800 2150 3900 2150 +Wire Wire Line + 4200 2150 4300 2150 +Wire Wire Line + 4300 2150 4300 2750 +Wire Wire Line + 2900 3200 3250 3200 +Wire Wire Line + 3250 3200 4300 3200 +Wire Wire Line + 2600 2250 2900 2350 +Connection ~ 2600 1650 +Wire Wire Line + 1200 2250 1200 2300 +Wire Wire Line + 1500 2500 1750 2500 +Wire Wire Line + 2050 2500 2600 2500 +Wire Wire Line + 2900 2750 3250 2750 +Wire Wire Line + 3250 2750 3250 2550 +Wire Wire Line + 3250 2550 3450 2550 +Wire Wire Line + 3100 1850 3450 1850 +Wire Wire Line + 3450 1850 4600 1850 +Wire Wire Line + 4600 1850 5300 1850 +Wire Wire Line + 4600 2500 3800 2500 +Wire Wire Line + 1200 2700 1200 3100 +Wire Wire Line + 1200 3100 2600 3100 +Wire Wire Line + 2600 2950 2600 3100 +Wire Wire Line + 2600 3100 2600 3700 +Connection ~ 3250 3200 +Wire Wire Line + 2900 2350 2900 3200 +Wire Wire Line + 2600 3700 2900 3700 +Wire Wire Line + 2900 3700 4050 3700 +Wire Wire Line + 6900 700 6900 600 +Connection ~ 6900 600 +Wire Wire Line + 6100 700 6100 600 +Connection ~ 6100 600 +Wire Wire Line + 6100 1150 6100 1000 +Wire Wire Line + 6900 1150 6900 1000 +Connection ~ 2100 1400 +Wire Wire Line + 6900 1550 6900 1850 +Wire Wire Line + 6900 1850 6900 2600 +Wire Wire Line + 6900 1850 7300 1850 +Wire Wire Line + 7300 1850 7300 1350 +Wire Wire Line + 7300 1350 7550 1350 +Wire Wire Line + 7850 1550 7850 1650 +Wire Wire Line + 7850 1650 7850 1800 +Wire Wire Line + 7850 1650 8250 1650 +Wire Wire Line + 8250 1650 8250 1350 +Wire Wire Line + 8250 1350 8500 1350 +Connection ~ 7850 1650 +Wire Wire Line + 7850 1150 7850 600 +Connection ~ 7850 600 +Wire Wire Line + 7850 2100 7850 2250 +Wire Wire Line + 7850 2250 8350 2250 +Wire Wire Line + 8350 2250 8350 1850 +Wire Wire Line + 8350 1850 8800 1850 +Wire Wire Line + 8800 1850 8850 1850 +Wire Wire Line + 8850 1850 9700 1850 +Connection ~ 8850 1850 +Wire Wire Line + 8850 2350 8850 2400 +Wire Wire Line + 8850 2400 9700 2400 +Wire Wire Line + 3450 2350 3450 2550 +Wire Wire Line + 3450 2550 3450 4300 +Wire Wire Line + 3800 2500 3800 2150 +Connection ~ 3800 2150 +Wire Wire Line + 2600 2500 2600 2550 +Wire Wire Line + 3250 3200 3250 3050 +Wire Wire Line + 4300 3200 4300 3050 +Connection ~ 2600 3100 +Wire Wire Line + 2100 1400 2100 1150 +Wire Wire Line + 2100 1150 2850 1150 +Wire Wire Line + 2850 1150 2850 1350 +Wire Wire Line + 4600 2350 4600 2500 +Wire Wire Line + 4600 2500 4600 4300 +Wire Wire Line + 3100 1450 3100 600 +Connection ~ 3100 600 +Wire Wire Line + 3450 1850 3450 1950 +Wire Wire Line + 4600 1850 4600 1950 +Connection ~ 3450 1850 +Wire Wire Line + 5300 1850 5300 2900 +Wire Wire Line + 5300 2900 5300 3050 +Wire Wire Line + 5300 2900 7600 2900 +Wire Wire Line + 7600 2900 9700 2900 +Connection ~ 4600 1850 +Wire Wire Line + 6100 1550 6100 3150 +Wire Wire Line + 6900 2600 8400 2600 +Wire Wire Line + 8400 2600 8400 3250 +Wire Wire Line + 8400 3250 8400 3450 +Wire Wire Line + 8400 3450 8400 4050 +Connection ~ 6900 1850 +Wire Wire Line + 8400 3250 9700 3250 +Connection ~ 8400 3250 +Wire Wire Line + 8800 1550 8800 1850 +Connection ~ 8800 1850 +Wire Wire Line + 2850 1350 5700 1350 +Wire Wire Line + 5700 1350 5800 1350 +Wire Wire Line + 5700 1350 5700 1150 +Wire Wire Line + 5700 1150 6600 1150 +Wire Wire Line + 6600 1150 6600 1350 +Connection ~ 5700 1350 +Connection ~ 4600 2500 +Connection ~ 3450 2550 +Wire Wire Line + 900 1600 900 2150 +Wire Wire Line + 900 2150 900 4250 +Wire Wire Line + 3750 4500 3850 4500 +Wire Wire Line + 3850 4500 4450 4500 +Wire Wire Line + 4450 4500 4900 4500 +Wire Wire Line + 3850 4650 3850 4500 +Connection ~ 3850 4500 +Wire Wire Line + 4600 4700 4600 4950 +Wire Wire Line + 4600 4950 4400 4950 +Wire Wire Line + 3450 4950 3850 4950 +Wire Wire Line + 3850 4950 4100 4950 +Wire Wire Line + 3450 4700 3450 4950 +Wire Wire Line + 3450 4950 3450 5150 +Connection ~ 3850 4950 +Connection ~ 3450 4950 +Wire Wire Line + 3450 5950 3450 5450 +Wire Wire Line + 3450 6450 3450 6250 +Wire Wire Line + 900 4250 1400 4250 +Wire Wire Line + 1400 4250 1700 4250 +Wire Wire Line + 1700 4250 2500 4250 +Wire Wire Line + 2500 4250 2500 5400 +Wire Wire Line + 1700 4350 1700 4250 +Connection ~ 1700 4250 +Wire Wire Line + 1700 4750 1850 4750 +Wire Wire Line + 1850 4750 1850 5000 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6450 +Connection ~ 2500 6450 +Wire Wire Line + 2800 5600 3050 5600 +Wire Wire Line + 3050 5600 3050 4050 +Wire Wire Line + 3050 4050 7350 4050 +Connection ~ 3450 6450 +Wire Wire Line + 4450 4500 4450 4300 +Wire Wire Line + 4450 4300 5300 4300 +Connection ~ 4450 4500 +Connection ~ 5300 2900 +Wire Wire Line + 5300 3350 5300 3450 +Wire Wire Line + 5300 3450 5300 3550 +Wire Wire Line + 5300 3850 5300 4300 +Wire Wire Line + 5300 4300 5300 4550 +Connection ~ 5300 4300 +Wire Wire Line + 5300 4850 5300 5000 +Wire Wire Line + 5300 5000 5300 5150 +Wire Wire Line + 5300 5450 5300 5550 +Wire Wire Line + 5300 5550 5300 5900 +Wire Wire Line + 5300 6200 5300 6450 +Connection ~ 5300 6450 +Wire Wire Line + 4050 3700 4050 6450 +Connection ~ 4050 6450 +Connection ~ 2900 3700 +Wire Wire Line + 5300 3450 6250 3450 +Wire Wire Line + 6250 3450 6250 4250 +Connection ~ 5300 3450 +Wire Wire Line + 6550 4250 6550 4800 +Wire Wire Line + 5950 4250 6250 4250 +Wire Wire Line + 6250 4250 6550 4250 +Wire Wire Line + 6550 5900 6550 5200 +Wire Wire Line + 6250 5000 5300 5000 +Connection ~ 5300 5000 +Wire Wire Line + 5950 4250 5950 5350 +Connection ~ 6250 4250 +Wire Wire Line + 5650 5550 5300 5550 +Connection ~ 5300 5550 +$Comp +L resistor R15 +U 1 1 62BC8945 +P 5900 6000 +F 0 "R15" H 5950 6130 50 0000 C CNN +F 1 "1.7k" H 5950 5950 50 0000 C CNN +F 2 "" H 5950 5980 30 0000 C CNN +F 3 "" V 5950 6050 30 0000 C CNN + 1 5900 6000 + 0 1 1 0 +$EndComp +Wire Wire Line + 5950 5750 5950 5900 +Wire Wire Line + 5950 6200 5950 6450 +Connection ~ 5950 6450 +Wire Wire Line + 6550 6200 6550 6450 +Connection ~ 6550 6450 +Wire Wire Line + 6100 3150 7000 3150 +Wire Wire Line + 7000 3150 7000 5100 +Wire Wire Line + 7000 5100 7000 5250 +$Comp +L eSim_NPN Q17 +U 1 1 62BC8946 +P 7100 5450 +F 0 "Q17" H 7000 5500 50 0000 R CNN +F 1 "eSim_NPN" H 7050 5600 50 0000 R CNN +F 2 "" H 7300 5550 29 0000 C CNN +F 3 "" H 7100 5450 60 0000 C CNN + 1 7100 5450 + -1 0 0 -1 +$EndComp +$Comp +L resistor R19 +U 1 1 62BC8947 +P 6950 6000 +F 0 "R19" H 7000 6130 50 0000 C CNN +F 1 "300" H 7000 5950 50 0000 C CNN +F 2 "" H 7000 5980 30 0000 C CNN +F 3 "" V 7000 6050 30 0000 C CNN + 1 6950 6000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7000 5900 7000 5650 +Wire Wire Line + 7000 6200 7000 6450 +Connection ~ 7000 6450 +Wire Wire Line + 7600 2900 7600 3850 +Wire Wire Line + 7600 3850 7600 4900 +Connection ~ 7600 2900 +$Comp +L eSim_NPN Q18 +U 1 1 62BC8948 +P 7500 5100 +F 0 "Q18" H 7400 5150 50 0000 R CNN +F 1 "eSim_NPN" H 7450 5250 50 0000 R CNN +F 2 "" H 7700 5200 29 0000 C CNN +F 3 "" H 7500 5100 60 0000 C CNN + 1 7500 5100 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 5100 7000 5100 +Connection ~ 7000 5100 +Wire Wire Line + 7600 5300 7600 5450 +Wire Wire Line + 7600 5450 7600 5500 +Wire Wire Line + 7600 5500 7600 5900 +Wire Wire Line + 7300 5450 7350 5450 +Wire Wire Line + 7350 5450 7600 5450 +Connection ~ 7600 5450 +$Comp +L resistor R20 +U 1 1 62BC8949 +P 7550 6000 +F 0 "R20" H 7600 6130 50 0000 C CNN +F 1 "10k" H 7600 5950 50 0000 C CNN +F 2 "" H 7600 5980 30 0000 C CNN +F 3 "" V 7600 6050 30 0000 C CNN + 1 7550 6000 + 0 1 1 0 +$EndComp +Wire Wire Line + 7600 6200 7600 6450 +Connection ~ 7600 6450 +$Comp +L eSim_NPN Q24 +U 1 1 62BC894A +P 8750 3650 +F 0 "Q24" H 8650 3700 50 0000 R CNN +F 1 "eSim_NPN" H 8700 3800 50 0000 R CNN +F 2 "" H 8950 3750 29 0000 C CNN +F 3 "" H 8750 3650 60 0000 C CNN + 1 8750 3650 + -1 0 0 -1 +$EndComp +Wire Wire Line + 8400 3450 8650 3450 +Wire Wire Line + 8650 3950 9700 3950 +$Comp +L resistor R24 +U 1 1 62BC894B +P 9150 3600 +F 0 "R24" H 9200 3730 50 0000 C CNN +F 1 "400" H 9200 3550 50 0000 C CNN +F 2 "" H 9200 3580 30 0000 C CNN +F 3 "" V 9200 3650 30 0000 C CNN + 1 9150 3600 + -1 0 0 1 +$EndComp +Wire Wire Line + 8950 3650 8950 3650 +Wire Wire Line + 9250 3650 9700 3650 +Connection ~ 8400 3450 +Wire Wire Line + 7350 4050 7350 5450 +Connection ~ 7350 5450 +$Comp +L eSim_NPN Q22 +U 1 1 62BC894C +P 8500 4250 +F 0 "Q22" H 8400 4300 50 0000 R CNN +F 1 "eSim_NPN" H 8450 4400 50 0000 R CNN +F 2 "" H 8700 4350 29 0000 C CNN +F 3 "" H 8500 4250 60 0000 C CNN + 1 8500 4250 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q20 +U 1 1 62BC894D +P 8000 4250 +F 0 "Q20" H 7900 4300 50 0000 R CNN +F 1 "eSim_NPN" H 7950 4400 50 0000 R CNN +F 2 "" H 8200 4350 29 0000 C CNN +F 3 "" H 8000 4250 60 0000 C CNN + 1 8000 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7800 4250 7800 4600 +Wire Wire Line + 7800 4600 9700 4600 +Wire Wire Line + 8700 4250 9700 4250 +Wire Wire Line + 8100 4450 8100 4500 +Wire Wire Line + 8100 4500 8250 4500 +Wire Wire Line + 8250 4500 8400 4500 +Wire Wire Line + 8400 4500 8400 4450 +Wire Wire Line + 8100 4050 8100 3850 +Wire Wire Line + 8100 3850 7600 3850 +Connection ~ 7600 3850 +$Comp +L eSim_NPN Q21 +U 1 1 62BC894E +P 8150 5500 +F 0 "Q21" H 8050 5550 50 0000 R CNN +F 1 "eSim_NPN" H 8100 5650 50 0000 R CNN +F 2 "" H 8350 5600 29 0000 C CNN +F 3 "" H 8150 5500 60 0000 C CNN + 1 8150 5500 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8250 4500 8250 4950 +Wire Wire Line + 8250 4950 8250 5300 +Connection ~ 8250 4500 +Wire Wire Line + 7600 5500 7900 5500 +Wire Wire Line + 7900 5500 7950 5500 +Connection ~ 7600 5500 +Wire Wire Line + 8250 5700 8250 5750 +Wire Wire Line + 8250 5750 8250 5900 +Wire Wire Line + 8800 5350 8800 5900 +Connection ~ 8250 5750 +$Comp +L resistor R22 +U 1 1 62BC894F +P 8200 6000 +F 0 "R22" H 8250 6130 50 0000 C CNN +F 1 "300" H 8250 5950 50 0000 C CNN +F 2 "" H 8250 5980 30 0000 C CNN +F 3 "" V 8250 6050 30 0000 C CNN + 1 8200 6000 + 0 1 1 0 +$EndComp +$Comp +L resistor R23 +U 1 1 62BC8950 +P 8750 6000 +F 0 "R23" H 8800 6130 50 0000 C CNN +F 1 "300" H 8800 5950 50 0000 C CNN +F 2 "" H 8800 5980 30 0000 C CNN +F 3 "" V 8800 6050 30 0000 C CNN + 1 8750 6000 + 0 1 1 0 +$EndComp +Wire Wire Line + 8250 6200 8250 6450 +Connection ~ 8250 6450 +Wire Wire Line + 8800 6200 8800 6450 +Connection ~ 8800 6450 +Wire Wire Line + 1400 4250 1400 5150 +Wire Wire Line + 1400 5150 1550 5150 +Wire Wire Line + 1550 5150 1550 5200 +Connection ~ 1400 4250 +Wire Wire Line + 8650 3950 8650 3850 +Wire Wire Line + 8800 1150 8800 1000 +Wire Wire Line + 8800 1000 9700 1000 +Text Label 9200 600 0 60 ~ 0 +V+ +Text Label 9200 1000 0 60 ~ 0 +Vc +Text Label 9200 1850 0 60 ~ 0 +Vout +Text Label 9200 2400 0 60 ~ 0 +Vz +Text Label 9200 2900 0 60 ~ 0 +Vref +Text Label 9050 3250 0 60 ~ 0 +Compensation +Text Label 9250 3650 0 60 ~ 0 +Current_limit +Text Label 9050 3950 0 60 ~ 0 +Current_sense +Text Label 9050 4250 0 60 ~ 0 +Inverting_input +Text Label 8800 4600 0 60 ~ 0 +Non-inverting_input +Text Label 9350 6450 0 60 ~ 0 +V- +$Comp +L PORT U4 +U 1 1 62BC8951 +P 9950 600 +F 0 "U4" H 10000 700 30 0000 C CNN +F 1 "PORT" H 9950 600 30 0000 C CNN +F 2 "" H 9950 600 60 0000 C CNN +F 3 "" H 9950 600 60 0000 C CNN + 1 9950 600 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 2 1 62BC8952 +P 9950 1000 +F 0 "U4" H 10000 1100 30 0000 C CNN +F 1 "PORT" H 9950 1000 30 0000 C CNN +F 2 "" H 9950 1000 60 0000 C CNN +F 3 "" H 9950 1000 60 0000 C CNN + 2 9950 1000 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 3 1 62BC8953 +P 9950 1850 +F 0 "U4" H 10000 1950 30 0000 C CNN +F 1 "PORT" H 9950 1850 30 0000 C CNN +F 2 "" H 9950 1850 60 0000 C CNN +F 3 "" H 9950 1850 60 0000 C CNN + 3 9950 1850 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 4 1 62BC8954 +P 9950 2400 +F 0 "U4" H 10000 2500 30 0000 C CNN +F 1 "PORT" H 9950 2400 30 0000 C CNN +F 2 "" H 9950 2400 60 0000 C CNN +F 3 "" H 9950 2400 60 0000 C CNN + 4 9950 2400 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 5 1 62BC8955 +P 9950 2900 +F 0 "U4" H 10000 3000 30 0000 C CNN +F 1 "PORT" H 9950 2900 30 0000 C CNN +F 2 "" H 9950 2900 60 0000 C CNN +F 3 "" H 9950 2900 60 0000 C CNN + 5 9950 2900 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 6 1 62BC8956 +P 9950 3250 +F 0 "U4" H 10000 3350 30 0000 C CNN +F 1 "PORT" H 9950 3250 30 0000 C CNN +F 2 "" H 9950 3250 60 0000 C CNN +F 3 "" H 9950 3250 60 0000 C CNN + 6 9950 3250 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 7 1 62BC8957 +P 9950 3650 +F 0 "U4" H 10000 3750 30 0000 C CNN +F 1 "PORT" H 9950 3650 30 0000 C CNN +F 2 "" H 9950 3650 60 0000 C CNN +F 3 "" H 9950 3650 60 0000 C CNN + 7 9950 3650 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 8 1 62BC8958 +P 9950 3950 +F 0 "U4" H 10000 4050 30 0000 C CNN +F 1 "PORT" H 9950 3950 30 0000 C CNN +F 2 "" H 9950 3950 60 0000 C CNN +F 3 "" H 9950 3950 60 0000 C CNN + 8 9950 3950 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 9 1 62BC8959 +P 9950 4250 +F 0 "U4" H 10000 4350 30 0000 C CNN +F 1 "PORT" H 9950 4250 30 0000 C CNN +F 2 "" H 9950 4250 60 0000 C CNN +F 3 "" H 9950 4250 60 0000 C CNN + 9 9950 4250 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 10 1 62BC895A +P 9950 4600 +F 0 "U4" H 10000 4700 30 0000 C CNN +F 1 "PORT" H 9950 4600 30 0000 C CNN +F 2 "" H 9950 4600 60 0000 C CNN +F 3 "" H 9950 4600 60 0000 C CNN + 10 9950 4600 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 11 1 62BC895B +P 9950 5000 +F 0 "U4" H 10000 5100 30 0000 C CNN +F 1 "PORT" H 9950 5000 30 0000 C CNN +F 2 "" H 9950 5000 60 0000 C CNN +F 3 "" H 9950 5000 60 0000 C CNN + 11 9950 5000 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 12 1 62BC895C +P 9950 5300 +F 0 "U4" H 10000 5400 30 0000 C CNN +F 1 "PORT" H 9950 5300 30 0000 C CNN +F 2 "" H 9950 5300 60 0000 C CNN +F 3 "" H 9950 5300 60 0000 C CNN + 12 9950 5300 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 13 1 62BC895D +P 9950 5600 +F 0 "U4" H 10000 5700 30 0000 C CNN +F 1 "PORT" H 9950 5600 30 0000 C CNN +F 2 "" H 9950 5600 60 0000 C CNN +F 3 "" H 9950 5600 60 0000 C CNN + 13 9950 5600 + -1 0 0 1 +$EndComp +$Comp +L PORT U4 +U 14 1 62BC895E +P 9950 6450 +F 0 "U4" H 10000 6550 30 0000 C CNN +F 1 "PORT" H 9950 6450 30 0000 C CNN +F 2 "" H 9950 6450 60 0000 C CNN +F 3 "" H 9950 6450 60 0000 C CNN + 14 9950 6450 + -1 0 0 1 +$EndComp +$Comp +L jfet_n J1 +U 1 1 62BE9EF0 +P 1800 4550 +F 0 "J1" H 1700 4600 50 0000 R CNN +F 1 "jfet_n" H 1750 4700 50 0000 R CNN +F 2 "" H 2000 4650 29 0000 C CNN +F 3 "" H 1800 4550 60 0000 C CNN + 1 1800 4550 + -1 0 0 1 +$EndComp +Wire Wire Line + 1600 2150 900 2150 +Connection ~ 900 2150 +$Comp +L eSim_PNP Q25 +U 1 1 62E05DAD +P 2250 1850 +F 0 "Q25" H 2150 1900 50 0000 R CNN +F 1 "eSim_PNP" H 2200 2000 50 0000 R CNN +F 2 "" H 2450 1950 29 0000 C CNN +F 3 "" H 2250 1850 60 0000 C CNN + 1 2250 1850 + 1 0 0 1 +$EndComp +Wire Wire Line + 2350 1650 2350 1100 +Wire Wire Line + 2350 1100 2600 1100 +Connection ~ 2600 1100 +Wire Wire Line + 2050 1850 2050 1400 +Connection ~ 2050 1400 +Wire Wire Line + 2350 2050 2350 2250 +Wire Wire Line + 2350 2250 1200 2250 +$Comp +L eSim_NPN Q26 +U 1 1 62E06C82 +P 8700 5150 +F 0 "Q26" H 8600 5200 50 0000 R CNN +F 1 "eSim_NPN" H 8650 5300 50 0000 R CNN +F 2 "" H 8900 5250 29 0000 C CNN +F 3 "" H 8700 5150 60 0000 C CNN + 1 8700 5150 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7900 5150 7900 5500 +Connection ~ 7900 5500 +Wire Wire Line + 8800 4950 8250 4950 +Connection ~ 8250 4950 +Wire Wire Line + 7900 5150 8500 5150 +NoConn ~ 9700 5000 +NoConn ~ 9700 5300 +NoConn ~ 9700 5600 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/LM723/LM723.sub b/library/SubcircuitLibrary/LM723/LM723.sub new file mode 100644 index 000000000..2d8b199b3 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723.sub @@ -0,0 +1,77 @@ +* Subcircuit LM723 +.subckt LM723 /v+ /vc /vout /vz /vref /compensation /current_limit /current_sense /inverting_input /non-inverting_input ? ? ? /v- +* c:\fossee\esim\library\subcircuitlibrary\lm723\lm723.cir +.include D.lib +.include PNP.lib +.include NJF.lib +.include NPN.lib +* u1 net-_j1-pad3_ /v+ zener +r2 /v+ net-_q4-pad3_ 900 +r5 net-_q25-pad3_ /v+ 550 +q4 net-_q14-pad2_ net-_q14-pad2_ net-_q4-pad3_ Q2N2907A +q5 net-_c1-pad2_ net-_q14-pad2_ net-_q25-pad3_ Q2N2907A +r3 net-_q14-pad2_ net-_j1-pad3_ 22k +q8 /v+ net-_c1-pad2_ /vref Q2N2222 +q2 /v- net-_d1-pad1_ net-_q2-pad3_ Q2N2907A +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +q7 /v- net-_c1-pad1_ net-_d1-pad2_ Q2N2907A +q9 net-_c1-pad1_ net-_q11-pad1_ /vref Q2N2907A +q11 net-_q11-pad1_ net-_c2-pad1_ /vref Q2N2907A +r8 net-_q11-pad1_ net-_c2-pad1_ 1.8k +c1 net-_c1-pad1_ net-_c1-pad2_ 10p +c2 net-_c2-pad1_ net-_c1-pad2_ 5p +* u2 /v- net-_c1-pad2_ zener +r16 /v+ net-_q14-pad3_ 1.8k +r18 net-_q16-pad3_ /v+ 1.8k +q14 net-_q14-pad1_ net-_q14-pad2_ net-_q14-pad3_ Q2N2907A +q16 /compensation net-_q14-pad2_ net-_q16-pad3_ Q2N2907A +q19 /v+ /compensation net-_q19-pad3_ Q2N2222 +q23 /vc net-_q19-pad3_ /vout Q2N2222 +r21 net-_q19-pad3_ /vout 15k +* u3 /vz /vout zener +q12 net-_q11-pad1_ net-_d2-pad2_ net-_q12-pad3_ Q2N2222 +q10 net-_c1-pad1_ net-_d2-pad2_ net-_d2-pad1_ Q2N2222 +d2 net-_d2-pad1_ net-_d2-pad2_ 1N4148 +r9 net-_d2-pad1_ net-_q12-pad3_ 2k +r6 net-_d2-pad1_ net-_r6-pad2_ 11k +r7 net-_r6-pad2_ /v- 1k +q6 net-_j1-pad3_ net-_q17-pad2_ net-_q6-pad3_ Q2N2222 +q3 net-_j1-pad3_ net-_j1-pad1_ net-_q1-pad2_ Q2N2222 +q1 net-_j1-pad1_ net-_q1-pad2_ /v- Q2N2222 +r1 net-_q1-pad2_ /v- 2.4k +r4 net-_q6-pad3_ /v- 160 +r10 /vref net-_q13-pad1_ 409 +r11 net-_q13-pad1_ net-_d2-pad2_ 11.89k +r12 net-_d2-pad2_ net-_q15-pad2_ 1.1k +r13 net-_q15-pad2_ net-_q13-pad2_ 380 +r14 net-_q13-pad2_ /v- 1.1k +q15 net-_q13-pad1_ net-_q15-pad2_ net-_q15-pad3_ Q2N2222 +r17 net-_q15-pad3_ /v- 1.1k +q13 net-_q13-pad1_ net-_q13-pad2_ net-_q13-pad3_ Q2N2222 +r15 net-_q13-pad3_ /v- 1.7k +q17 net-_q14-pad1_ net-_q17-pad2_ net-_q17-pad3_ Q2N2222 +r19 net-_q17-pad3_ /v- 300 +q18 /vref net-_q14-pad1_ net-_q17-pad2_ Q2N2222 +r20 net-_q17-pad2_ /v- 10k +q24 /compensation net-_q24-pad2_ /current_sense Q2N2222 +r24 /current_limit net-_q24-pad2_ 400 +q22 /compensation /inverting_input net-_q20-pad3_ Q2N2222 +q20 /vref /non-inverting_input net-_q20-pad3_ Q2N2222 +q21 net-_q20-pad3_ net-_q17-pad2_ net-_q21-pad3_ Q2N2222 +r22 net-_q21-pad3_ /v- 300 +r23 net-_q26-pad3_ /v- 300 +j1 net-_j1-pad1_ /v- net-_j1-pad3_ J2N3819 +q25 net-_q2-pad3_ net-_q14-pad2_ net-_q25-pad3_ Q2N2907A +q26 net-_q20-pad3_ net-_q17-pad2_ net-_q26-pad3_ Q2N2222 +a1 net-_j1-pad3_ /v+ u1 +a2 /v- net-_c1-pad2_ u2 +a3 /vz /vout u3 +* Schematic Name: zener, NgSpice Name: zener +.model u1 zener(v_breakdown=6.2 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u2 zener(v_breakdown=5.7 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Schematic Name: zener, NgSpice Name: zener +.model u3 zener(v_breakdown=5.6 i_breakdown=2.0e-2 i_sat=1.0e-12 n_forward=1.0 limit_switch=FALSE ) +* Control Statements + +.ends LM723 \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM723/LM723_Previous_Values.xml b/library/SubcircuitLibrary/LM723/LM723_Previous_Values.xml new file mode 100644 index 000000000..730dd7300 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/LM723_Previous_Values.xml @@ -0,0 +1 @@ +zener6.2zener5.7zenerC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\JFET\NJF.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libtruefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSec \ No newline at end of file diff --git a/library/SubcircuitLibrary/LM723/NJF.lib b/library/SubcircuitLibrary/LM723/NJF.lib new file mode 100644 index 000000000..dbb2cbae5 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/NJF.lib @@ -0,0 +1,4 @@ +.model J2N3819 NJF(Beta=1.304m Betatce=-.5 Rd=1 Rs=1 Lambda=2.25m Vto=-3 ++ Vtotc=-2.5m Is=33.57f Isr=322.4f N=1 Nr=2 Xti=3 Alpha=311.7u ++ Vk=243.6 Cgd=1.6p M=.3622 Pb=1 Fc=.5 Cgs=2.414p Kf=9.882E-18 ++ Af=1) diff --git a/library/SubcircuitLibrary/LM723/NMOS-180nm.lib b/library/SubcircuitLibrary/LM723/NMOS-180nm.lib new file mode 100644 index 000000000..51e9b1196 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/NMOS-180nm.lib @@ -0,0 +1,13 @@ +.model CMOSN NMOS (LEVEL=8 VERSION=3.2 TNOM=27 TOX=4.1E-9 XJ=1E-7 NCH=2.3549E17 VTH0=0.3823463 K1=0.5810697 ++ K2=4.774618E-3 K3=0.0431669 K3B=1.1498346 W0=1E-7 NLX=1.910552E-7 DVT0W=0 DVT1W=0 DVT2W=0 ++ DVT0=1.2894824 DVT1=0.3622063 DVT2=0.0713729 U0=280.633249 UA=-1.208537E-9 UB=2.158625E-18 ++ UC=5.342807E-11 VSAT=9.366802E4 A0=1.7593146 AGS=0.3939741 B0=-6.413949E-9 B1=-1E-7 KETA=-5.180424E-4 ++ A1=0 A2=1 RDSW=105.5517558 PRWG=0.5 PRWB=-0.1998871 WR=1 WINT=7.904732E-10 LINT=1.571424E-8 XL=0 ++ XW=-1E-8 DWG=1.297221E-9 DWB=1.479041E-9 VOFF=-0.0955434 NFACTOR=2.4358891 CIT=0 CDSC=2.4E-4 CDSCD=0 ++ CDSCB=0 ETA0=3.104851E-3 ETAB=-2.512384E-5 DSUB=0.0167075 PCLM=0.8073191 PDIBLC1=0.1666161 PDIBLC2=3.112892E-3 ++ PDIBLCB=-0.1 DROUT=0.7875618 PSCBE1=8E10 PSCBE2=9.213635E-10 PVAG=3.85243E-3 DELTA=0.01 RSH=6.7 MOBMOD=1 ++ PRT=0 UTE=-1.5 KT1=-0.11 KT1L=0 KT2=0.022 UA1=4.31E-9 UB1=-7.61E-18 UC1=-5.6E-11 AT=3.3E4 WL=0 WLN=1 ++ WW=0 WWN=1 WWL=0 LL=0 LLN=1 LW=0 LWN=1 LWL=0 CAPMOD=2 XPART=0.5 CGDO=7.08E-10 CGSO=7.08E-10 CGBO=1E-12 ++ CJ=9.68858E-4 PB=0.8 MJ=0.3864502 CJSW=2.512138E-10 PBSW=0.809286 MJSW=0.1060414 CJSWG=3.3E-10 PBSWG=0.809286 ++ MJSWG=0.1060414 CF=0 PVTH0=-1.192722E-3 PRDSW=-5 PK2=6.450505E-5 WKETA=-4.27294E-4 LKETA=-0.0104078 ++ PU0=6.3268729 PUA=2.226552E-11 PUB=0 PVSAT=969.1480157 PETA0=1E-4 PKETA=-1.049509E-3) diff --git a/library/SubcircuitLibrary/LM723/NPN.lib b/library/SubcircuitLibrary/LM723/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/LM723/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/LM723/PNP.lib b/library/SubcircuitLibrary/LM723/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/LM723/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/LM723/README.md b/library/SubcircuitLibrary/LM723/README.md new file mode 100644 index 000000000..291d0bd9f --- /dev/null +++ b/library/SubcircuitLibrary/LM723/README.md @@ -0,0 +1,36 @@ + +# LM723 Adjustable Voltage Regulator IC + +LM723 is an adjustable voltage regulator IC. It’s regulated output can be determined, by the external circuitry. It’s output can range from 2V to 37V. It can be used either as a linear regulator or a switching regulator. The Line Regulation & Load Regulation observed for this IC is 0.089% and 0.351% respectively. + + +## Usage/Examples + +Basic High Voltage Regulator + +Positive/Negative Voltage Regulator + +Positive/Negative Switching Regulator + +Foldback Current Limiting + +Positive/Negative Floating Regulator + +Shunt Regulator + + +## Documentation + +To know the details of LM723 IC please refer to this link [LM723_datasheet.](https://www.ti.com/lit/ds/symlink/lm723.pdf?ts=1665878014301&ref_url=https%253A%252F%252Fwww.google.com%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 + diff --git a/library/SubcircuitLibrary/LM723/analysis b/library/SubcircuitLibrary/LM723/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/LM723/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/lm1458/D.lib b/library/SubcircuitLibrary/lm1458/D.lib new file mode 100644 index 000000000..f53bf3e03 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/D.lib @@ -0,0 +1,2 @@ +.model 1N4148 D(is=2.495E-09 rs=4.755E-01 n=1.679E+00 tt=3.030E-09 cjo=1.700E-12 vj=1 m=1.959E-01 bv=1.000E+02 ibv=1.000E-04) + diff --git a/library/SubcircuitLibrary/lm1458/NPN.lib b/library/SubcircuitLibrary/lm1458/NPN.lib new file mode 100644 index 000000000..be5f3073a --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/NPN.lib @@ -0,0 +1,4 @@ +.model Q2N2222 NPN( Is=14.34f Xti=3 Eg=1.11 Vaf=74.03 Bf=400 Ne=1.307 ++ Ise=14.34f Ikf=0.2847 Xtb=1.5 Br=6.092 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=7.306p ++ Mjc=0.3416 Vjc=0.75 Fc=0.5 Cje=22.01p Mje=0.377 Vje=0.75 Tr=46.91n Tf=411.1p ++ Itf=0.6 Vtf=1.7 Xtf=3 Rb=10) diff --git a/library/SubcircuitLibrary/lm1458/PNP.lib b/library/SubcircuitLibrary/lm1458/PNP.lib new file mode 100644 index 000000000..7edda0eab --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/PNP.lib @@ -0,0 +1,4 @@ +.model Q2N2907A PNP(Is=650.6E-18 Xti=3 Eg=1.11 Vaf=115.7 Bf=231.7 Ne=1.829 ++ Ise=54.81f Ikf=1.079 Xtb=1.5 Br=3.563 Nc=2 Isc=0 Ikr=0 Rc=.715 ++ Cjc=14.76p Mjc=.5383 Vjc=.75 Fc=.5 Cje=19.82p Mje=.3357 Vje=.75 ++ Tr=111.3n Tf=603.7p Itf=.65 Vtf=5 Xtf=1.7 Rb=10) diff --git a/library/SubcircuitLibrary/lm1458/README.md b/library/SubcircuitLibrary/lm1458/README.md new file mode 100644 index 000000000..e3ed0ae98 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/README.md @@ -0,0 +1,35 @@ + +# LM1458 Dual Operational Amplifier IC + +LM1458 is a general purpose, Dual Channel Operational Amplifier IC. Both the Amplifiers operate independently but they share common supply. It has inbuilt short circuit protection & offers low power consumption. No frequency compensation is needed. + + +## Usage/Examples + +Inverting/Non-Inverting Amplifier + +Integrator/Summer + +Differential Amplifier + +Differentiator + +Schmitt Trigger + +Comparators + + +## Documentation + +To know the details of LM1458 IC please refer to this link [LM1458_datasheet.](https://www.ti.com/lit/ds/symlink/lm1458.pdf?ts=1665941946373&ref_url=https%253A%252F%252Fwww.google.com%252F) + +## Comments/Notes + +Please note this is a complete analog IC. It works fine at the time of simulation. + +## Contributor + +Name: Arpit Sharma +Email: arpitniraliya306@gmail.com +Year: 2022 +Position: FOSSEE Summer Fellowship Intern 2022 diff --git a/library/SubcircuitLibrary/lm1458/analysis b/library/SubcircuitLibrary/lm1458/analysis new file mode 100644 index 000000000..ebd5c0a94 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/analysis @@ -0,0 +1 @@ +.tran 0e-00 0e-00 0e-00 \ No newline at end of file diff --git a/library/SubcircuitLibrary/lm1458/lm1458-cache.lib b/library/SubcircuitLibrary/lm1458/lm1458-cache.lib new file mode 100644 index 000000000..d80602ef3 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458-cache.lib @@ -0,0 +1,145 @@ +EESchema-LIBRARY Version 2.3 +#encoding utf-8 +# +# PORT +# +DEF PORT U 0 40 Y Y 26 F N +F0 "U" 50 100 30 H V C CNN +F1 "PORT" 0 0 30 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +A 325 225 285 -1421 -1278 0 1 0 N 100 50 150 0 +A 376 -275 356 1294 1408 0 1 0 N 150 0 100 -50 +S -100 50 100 -50 0 1 0 N +X ~ 1 250 0 100 L 30 30 1 1 B +X ~ 2 250 0 100 L 30 30 2 1 B +X ~ 3 250 0 100 L 30 30 3 1 B +X ~ 4 250 0 100 L 30 30 4 1 B +X ~ 5 250 0 100 L 30 30 5 1 B +X ~ 6 250 0 100 L 30 30 6 1 B +X ~ 7 250 0 100 L 30 30 7 1 B +X ~ 8 250 0 100 L 30 30 8 1 B +X ~ 9 250 0 100 L 30 30 9 1 B +X ~ 10 250 0 100 L 30 30 10 1 B +X ~ 11 250 0 100 L 30 30 11 1 B +X ~ 12 250 0 100 L 30 30 12 1 B +X ~ 13 250 0 100 L 30 30 13 1 B +X ~ 14 250 0 100 L 30 30 14 1 B +X ~ 15 250 0 100 L 30 30 15 1 B +X ~ 16 250 0 100 L 30 30 16 1 B +X ~ 17 250 0 100 L 30 30 17 1 B +X ~ 18 250 0 100 L 30 30 18 1 B +X ~ 19 250 0 100 L 30 30 19 1 B +X ~ 20 250 0 100 L 30 30 20 1 B +X ~ 21 250 0 100 L 30 30 21 1 B +X ~ 22 250 0 100 L 30 30 22 1 B +X ~ 23 250 0 100 L 30 30 23 1 B +X ~ 24 250 0 100 L 30 30 24 1 B +X ~ 25 250 0 100 L 30 30 25 1 B +X ~ 26 250 0 100 L 30 30 26 1 B +ENDDRAW +ENDDEF +# +# eSim_C +# +DEF eSim_C C 0 10 N Y 1 F N +F0 "C" 25 100 50 H V L CNN +F1 "eSim_C" 25 -100 50 H V L CNN +F2 "" 38 -150 30 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS capacitor +$FPLIST + C_* +$ENDFPLIST +DRAW +P 2 0 1 20 -80 -30 80 -30 N +P 2 0 1 20 -80 30 80 30 N +X ~ 1 0 150 110 D 40 40 1 1 P +X ~ 2 0 -150 110 U 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_Diode +# +DEF eSim_Diode D 0 40 N N 1 F N +F0 "D" 0 100 50 H V C CNN +F1 "eSim_Diode" 0 -100 50 H V C CNN +F2 "" 0 0 60 H V C CNN +F3 "" 0 0 60 H V C CNN +$FPLIST + TO-???* + *SingleDiode + *_Diode_* + *SingleDiode* + D_* +$ENDFPLIST +DRAW +T 0 -100 50 60 0 0 0 A Normal 0 C C +T 0 100 50 60 0 0 0 K Normal 0 C C +P 2 0 1 6 50 50 50 -50 N +P 3 0 1 0 -50 50 50 0 -50 -50 F +X A 1 -150 0 100 R 40 40 1 1 P +X K 2 150 0 100 L 40 40 1 1 P +ENDDRAW +ENDDEF +# +# eSim_NPN +# +DEF eSim_NPN Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_NPN" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +ALIAS BC547 Q2N2222 +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 50 -70 70 -50 90 -90 50 -70 50 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_PNP +# +DEF eSim_PNP Q 0 0 Y N 1 F N +F0 "Q" -100 50 50 H V R CNN +F1 "eSim_PNP" -50 150 50 H V R CNN +F2 "" 200 100 29 H V C CNN +F3 "" 0 0 60 H V C CNN +DRAW +C 50 0 111 0 1 10 N +P 2 0 1 0 25 25 100 100 N +P 3 0 1 0 25 -25 100 -100 100 -100 N +P 3 0 1 20 25 75 25 -75 25 -75 N +P 5 0 1 0 90 -70 70 -90 50 -50 90 -70 90 -70 F +X C 1 100 200 100 D 50 50 1 1 P +X B 2 -200 0 225 R 50 50 1 1 P +X E 3 100 -200 100 U 50 50 1 1 P +ENDDRAW +ENDDEF +# +# eSim_R +# +DEF eSim_R R 0 0 N Y 1 F N +F0 "R" 50 130 50 H V C CNN +F1 "eSim_R" 50 -50 50 H V C CNN +F2 "" 50 -20 30 H V C CNN +F3 "" 50 50 30 V V C CNN +ALIAS resistor +$FPLIST + R_* + Resistor_* +$ENDFPLIST +DRAW +S 150 10 -50 90 0 1 10 N +X ~ 1 -100 50 50 R 60 60 1 1 P +X ~ 2 200 50 50 L 60 60 1 1 P +ENDDRAW +ENDDEF +# +#End Library diff --git a/library/SubcircuitLibrary/lm1458/lm1458.cir b/library/SubcircuitLibrary/lm1458/lm1458.cir new file mode 100644 index 000000000..a870732e5 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.cir @@ -0,0 +1,81 @@ +* C:\FOSSEE\eSim\library\SubcircuitLibrary\lm1458\lm1458.cir + +* EESchema Netlist Version 1.1 (Spice format) creation date: 09/09/22 23:07:58 + +* To exclude a component from the Spice Netlist add [Spice_Netlist_Enabled] user FIELD set to: N +* To reorder the component spice node sequence add [Spice_Node_Sequence] user FIELD and define sequence: 2,1,0 + +* Sheet Name: / +Q5 Net-_Q1-Pad1_ Net-_Q1-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q9 Net-_Q10-Pad1_ Net-_Q1-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q12 Net-_Q12-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q15 Net-_C1-Pad1_ Net-_Q12-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q1 Net-_Q1-Pad1_ Net-_Q1-Pad2_ Net-_Q1-Pad3_ eSim_NPN +Q2 Net-_Q2-Pad1_ Net-_Q10-Pad1_ Net-_Q1-Pad3_ eSim_PNP +Q8 Net-_Q1-Pad1_ Net-_Q8-Pad2_ Net-_Q6-Pad3_ eSim_NPN +Q6 Net-_C1-Pad2_ Net-_Q10-Pad1_ Net-_Q6-Pad3_ eSim_PNP +Q4 Net-_Q12-Pad3_ Net-_Q2-Pad1_ Net-_Q3-Pad2_ eSim_NPN +Q3 Net-_Q2-Pad1_ Net-_Q3-Pad2_ Net-_Q3-Pad3_ eSim_NPN +Q7 Net-_C1-Pad2_ Net-_Q3-Pad2_ Net-_Q7-Pad3_ eSim_NPN +R1 Net-_Q3-Pad3_ Net-_Q11-Pad3_ 1k +R2 Net-_Q3-Pad2_ Net-_Q11-Pad3_ 50k +R3 Net-_Q7-Pad3_ Net-_Q11-Pad3_ 1k +R5 Net-_Q12-Pad1_ Net-_R5-Pad2_ 19.5k +R6 Net-_R5-Pad2_ Net-_Q10-Pad2_ 19.5k +Q10 Net-_Q10-Pad1_ Net-_Q10-Pad2_ Net-_Q10-Pad3_ eSim_NPN +Q11 Net-_Q10-Pad2_ Net-_Q10-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R4 Net-_Q10-Pad3_ Net-_Q11-Pad3_ 5k +C1 Net-_C1-Pad1_ Net-_C1-Pad2_ 30p +Q13 Net-_C1-Pad2_ Net-_Q13-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q14 Net-_D1-Pad2_ Net-_C1-Pad2_ Net-_Q14-Pad3_ eSim_NPN +R7 Net-_Q14-Pad3_ Net-_Q11-Pad3_ 50k +Q16 Net-_C1-Pad1_ Net-_Q16-Pad2_ Net-_D1-Pad2_ eSim_NPN +Q17 Net-_D1-Pad2_ Net-_Q14-Pad3_ Net-_Q13-Pad2_ eSim_NPN +R10 Net-_Q13-Pad2_ Net-_Q11-Pad3_ 50 +R8 Net-_C1-Pad1_ Net-_Q16-Pad2_ 4.5k +R9 Net-_D1-Pad2_ Net-_Q16-Pad2_ 7.5k +Q18 Net-_C1-Pad1_ Net-_Q18-Pad2_ Net-_D2-Pad1_ eSim_NPN +Q19 Net-_Q12-Pad3_ Net-_C1-Pad1_ Net-_Q18-Pad2_ eSim_NPN +R11 Net-_Q18-Pad2_ Net-_D2-Pad1_ 25 +D1 Net-_D1-Pad1_ Net-_D1-Pad2_ eSim_Diode +D2 Net-_D2-Pad1_ Net-_D1-Pad1_ eSim_Diode +R12 Net-_D2-Pad1_ Net-_Q20-Pad3_ 50 +Q20 Net-_Q11-Pad3_ Net-_D1-Pad2_ Net-_Q20-Pad3_ eSim_PNP +Q25 Net-_Q21-Pad1_ Net-_Q21-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q29 Net-_Q22-Pad2_ Net-_Q21-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q32 Net-_Q32-Pad1_ Net-_Q32-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q35 Net-_C2-Pad1_ Net-_Q32-Pad1_ Net-_Q12-Pad3_ eSim_PNP +Q21 Net-_Q21-Pad1_ Net-_Q21-Pad2_ Net-_Q21-Pad3_ eSim_NPN +Q22 Net-_Q22-Pad1_ Net-_Q22-Pad2_ Net-_Q21-Pad3_ eSim_PNP +Q28 Net-_Q21-Pad1_ Net-_Q28-Pad2_ Net-_Q26-Pad3_ eSim_NPN +Q26 Net-_C2-Pad2_ Net-_Q22-Pad2_ Net-_Q26-Pad3_ eSim_PNP +Q24 Net-_Q12-Pad3_ Net-_Q22-Pad1_ Net-_Q23-Pad2_ eSim_NPN +Q23 Net-_Q22-Pad1_ Net-_Q23-Pad2_ Net-_Q23-Pad3_ eSim_NPN +Q27 Net-_C2-Pad2_ Net-_Q23-Pad2_ Net-_Q27-Pad3_ eSim_NPN +R13 Net-_Q23-Pad3_ Net-_Q11-Pad3_ 1k +R14 Net-_Q23-Pad2_ Net-_Q11-Pad3_ 50k +R15 Net-_Q27-Pad3_ Net-_Q11-Pad3_ 1k +R17 Net-_Q32-Pad1_ Net-_R17-Pad2_ 19.5k +R18 Net-_R17-Pad2_ Net-_Q30-Pad2_ 19.5k +Q30 Net-_Q22-Pad2_ Net-_Q30-Pad2_ Net-_Q30-Pad3_ eSim_NPN +Q31 Net-_Q30-Pad2_ Net-_Q30-Pad2_ Net-_Q11-Pad3_ eSim_NPN +R16 Net-_Q30-Pad3_ Net-_Q11-Pad3_ 5k +C2 Net-_C2-Pad1_ Net-_C2-Pad2_ 30p +Q33 Net-_C2-Pad2_ Net-_Q33-Pad2_ Net-_Q11-Pad3_ eSim_NPN +Q34 Net-_D3-Pad2_ Net-_C2-Pad2_ Net-_Q34-Pad3_ eSim_NPN +R19 Net-_Q34-Pad3_ Net-_Q11-Pad3_ 50k +Q36 Net-_C2-Pad1_ Net-_Q36-Pad2_ Net-_D3-Pad2_ eSim_NPN +Q37 Net-_D3-Pad2_ Net-_Q34-Pad3_ Net-_Q33-Pad2_ eSim_NPN +R22 Net-_Q33-Pad2_ Net-_Q11-Pad3_ 50 +R20 Net-_C2-Pad1_ Net-_Q36-Pad2_ 4.5k +R21 Net-_D3-Pad2_ Net-_Q36-Pad2_ 7.5k +Q38 Net-_C2-Pad1_ Net-_Q38-Pad2_ Net-_D4-Pad1_ eSim_NPN +Q39 Net-_Q12-Pad3_ Net-_C2-Pad1_ Net-_Q38-Pad2_ eSim_NPN +R23 Net-_Q38-Pad2_ Net-_D4-Pad1_ 25 +D3 Net-_D3-Pad1_ Net-_D3-Pad2_ eSim_Diode +D4 Net-_D4-Pad1_ Net-_D3-Pad1_ eSim_Diode +R24 Net-_D4-Pad1_ Net-_Q40-Pad3_ 50 +Q40 Net-_Q11-Pad3_ Net-_D3-Pad2_ Net-_Q40-Pad3_ eSim_PNP +U1 Net-_Q1-Pad2_ Net-_Q8-Pad2_ Net-_Q11-Pad3_ Net-_Q21-Pad2_ Net-_Q12-Pad3_ Net-_D2-Pad1_ Net-_Q28-Pad2_ Net-_D4-Pad1_ PORT + +.end diff --git a/library/SubcircuitLibrary/lm1458/lm1458.cir.out b/library/SubcircuitLibrary/lm1458/lm1458.cir.out new file mode 100644 index 000000000..0a97abf0a --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.cir.out @@ -0,0 +1,85 @@ +* c:\fossee\esim\library\subcircuitlibrary\lm1458\lm1458.cir + +.include D.lib +.include NPN.lib +.include PNP.lib +q5 net-_q1-pad1_ net-_q1-pad1_ net-_q12-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q1-pad1_ net-_q12-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2907A +q15 net-_c1-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q10-pad1_ net-_q1-pad3_ Q2N2907A +q8 net-_q1-pad1_ net-_q8-pad2_ net-_q6-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_q10-pad1_ net-_q6-pad3_ Q2N2907A +q4 net-_q12-pad3_ net-_q2-pad1_ net-_q3-pad2_ Q2N2222 +q3 net-_q2-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q7 net-_c1-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_q11-pad3_ 1k +r2 net-_q3-pad2_ net-_q11-pad3_ 50k +r3 net-_q7-pad3_ net-_q11-pad3_ 1k +r5 net-_q12-pad1_ net-_r5-pad2_ 19.5k +r6 net-_r5-pad2_ net-_q10-pad2_ 19.5k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_q10-pad2_ net-_q10-pad2_ net-_q11-pad3_ Q2N2222 +r4 net-_q10-pad3_ net-_q11-pad3_ 5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q13 net-_c1-pad2_ net-_q13-pad2_ net-_q11-pad3_ Q2N2222 +q14 net-_d1-pad2_ net-_c1-pad2_ net-_q14-pad3_ Q2N2222 +r7 net-_q14-pad3_ net-_q11-pad3_ 50k +q16 net-_c1-pad1_ net-_q16-pad2_ net-_d1-pad2_ Q2N2222 +q17 net-_d1-pad2_ net-_q14-pad3_ net-_q13-pad2_ Q2N2222 +r10 net-_q13-pad2_ net-_q11-pad3_ 50 +r8 net-_c1-pad1_ net-_q16-pad2_ 4.5k +r9 net-_d1-pad2_ net-_q16-pad2_ 7.5k +q18 net-_c1-pad1_ net-_q18-pad2_ net-_d2-pad1_ Q2N2222 +q19 net-_q12-pad3_ net-_c1-pad1_ net-_q18-pad2_ Q2N2222 +r11 net-_q18-pad2_ net-_d2-pad1_ 25 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d2-pad1_ net-_d1-pad1_ 1N4148 +r12 net-_d2-pad1_ net-_q20-pad3_ 50 +q20 net-_q11-pad3_ net-_d1-pad2_ net-_q20-pad3_ Q2N2907A +q25 net-_q21-pad1_ net-_q21-pad1_ net-_q12-pad3_ Q2N2907A +q29 net-_q22-pad2_ net-_q21-pad1_ net-_q12-pad3_ Q2N2907A +q32 net-_q32-pad1_ net-_q32-pad1_ net-_q12-pad3_ Q2N2907A +q35 net-_c2-pad1_ net-_q32-pad1_ net-_q12-pad3_ Q2N2907A +q21 net-_q21-pad1_ net-_q21-pad2_ net-_q21-pad3_ Q2N2222 +q22 net-_q22-pad1_ net-_q22-pad2_ net-_q21-pad3_ Q2N2907A +q28 net-_q21-pad1_ net-_q28-pad2_ net-_q26-pad3_ Q2N2222 +q26 net-_c2-pad2_ net-_q22-pad2_ net-_q26-pad3_ Q2N2907A +q24 net-_q12-pad3_ net-_q22-pad1_ net-_q23-pad2_ Q2N2222 +q23 net-_q22-pad1_ net-_q23-pad2_ net-_q23-pad3_ Q2N2222 +q27 net-_c2-pad2_ net-_q23-pad2_ net-_q27-pad3_ Q2N2222 +r13 net-_q23-pad3_ net-_q11-pad3_ 1k +r14 net-_q23-pad2_ net-_q11-pad3_ 50k +r15 net-_q27-pad3_ net-_q11-pad3_ 1k +r17 net-_q32-pad1_ net-_r17-pad2_ 19.5k +r18 net-_r17-pad2_ net-_q30-pad2_ 19.5k +q30 net-_q22-pad2_ net-_q30-pad2_ net-_q30-pad3_ Q2N2222 +q31 net-_q30-pad2_ net-_q30-pad2_ net-_q11-pad3_ Q2N2222 +r16 net-_q30-pad3_ net-_q11-pad3_ 5k +c2 net-_c2-pad1_ net-_c2-pad2_ 30p +q33 net-_c2-pad2_ net-_q33-pad2_ net-_q11-pad3_ Q2N2222 +q34 net-_d3-pad2_ net-_c2-pad2_ net-_q34-pad3_ Q2N2222 +r19 net-_q34-pad3_ net-_q11-pad3_ 50k +q36 net-_c2-pad1_ net-_q36-pad2_ net-_d3-pad2_ Q2N2222 +q37 net-_d3-pad2_ net-_q34-pad3_ net-_q33-pad2_ Q2N2222 +r22 net-_q33-pad2_ net-_q11-pad3_ 50 +r20 net-_c2-pad1_ net-_q36-pad2_ 4.5k +r21 net-_d3-pad2_ net-_q36-pad2_ 7.5k +q38 net-_c2-pad1_ net-_q38-pad2_ net-_d4-pad1_ Q2N2222 +q39 net-_q12-pad3_ net-_c2-pad1_ net-_q38-pad2_ Q2N2222 +r23 net-_q38-pad2_ net-_d4-pad1_ 25 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d4-pad1_ net-_d3-pad1_ 1N4148 +r24 net-_d4-pad1_ net-_q40-pad3_ 50 +q40 net-_q11-pad3_ net-_d3-pad2_ net-_q40-pad3_ Q2N2907A +* u1 net-_q1-pad2_ net-_q8-pad2_ net-_q11-pad3_ net-_q21-pad2_ net-_q12-pad3_ net-_d2-pad1_ net-_q28-pad2_ net-_d4-pad1_ port +.tran 0e-00 0e-00 0e-00 + +* Control Statements +.control +run +print allv > plot_data_v.txt +print alli > plot_data_i.txt +.endc +.end diff --git a/library/SubcircuitLibrary/lm1458/lm1458.pro b/library/SubcircuitLibrary/lm1458/lm1458.pro new file mode 100644 index 000000000..1c549d980 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.pro @@ -0,0 +1,81 @@ +update=09/24/22 18:31:22 +version=1 +last_client=eeschema +[general] +version=1 +RootSch= +BoardNm= +[pcbnew] +version=1 +LastNetListRead= +UseCmpFile=1 +PadDrill=0.600000000000 +PadDrillOvalY=0.600000000000 +PadSizeH=1.500000000000 +PadSizeV=1.500000000000 +PcbTextSizeV=1.500000000000 +PcbTextSizeH=1.500000000000 +PcbTextThickness=0.300000000000 +ModuleTextSizeV=1.000000000000 +ModuleTextSizeH=1.000000000000 +ModuleTextSizeThickness=0.150000000000 +SolderMaskClearance=0.000000000000 +SolderMaskMinWidth=0.000000000000 +DrawSegmentWidth=0.200000000000 +BoardOutlineThickness=0.100000000000 +ModuleOutlineThickness=0.150000000000 +[cvpcb] +version=1 +NetIExt=net +[eeschema] +version=1 +LibDir= +[eeschema/libraries] +LibName1=adc-dac +LibName2=memory +LibName3=xilinx +LibName4=microcontrollers +LibName5=dsp +LibName6=microchip +LibName7=analog_switches +LibName8=motorola +LibName9=texas +LibName10=intel +LibName11=audio +LibName12=interface +LibName13=digital-audio +LibName14=philips +LibName15=display +LibName16=cypress +LibName17=siliconi +LibName18=opto +LibName19=atmel +LibName20=contrib +LibName21=power +LibName22=eSim_Plot +LibName23=transistors +LibName24=conn +LibName25=eSim_User +LibName26=regul +LibName27=74xx +LibName28=cmos4000 +LibName29=eSim_Analog +LibName30=eSim_Devices +LibName31=eSim_Digital +LibName32=eSim_Hybrid +LibName33=eSim_Miscellaneous +LibName34=eSim_Power +LibName35=eSim_Sources +LibName36=eSim_Subckt +LibName37=eSim_Nghdl +LibName38=eSim_Ngveri +[schematic_editor] +version=1 +PageLayoutDescrFile= +PlotDirectoryName= +SubpartIdSeparator=0 +SubpartFirstId=65 +NetFmtName= +SpiceForceRefPrefix=0 +SpiceUseNetNumbers=0 +LabSize=60 diff --git a/library/SubcircuitLibrary/lm1458/lm1458.sch b/library/SubcircuitLibrary/lm1458/lm1458.sch new file mode 100644 index 000000000..591e1bf77 --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.sch @@ -0,0 +1,1313 @@ +EESchema Schematic File Version 2 +LIBS:adc-dac +LIBS:memory +LIBS:xilinx +LIBS:microcontrollers +LIBS:dsp +LIBS:microchip +LIBS:analog_switches +LIBS:motorola +LIBS:texas +LIBS:intel +LIBS:audio +LIBS:interface +LIBS:digital-audio +LIBS:philips +LIBS:display +LIBS:cypress +LIBS:siliconi +LIBS:opto +LIBS:atmel +LIBS:contrib +LIBS:power +LIBS:eSim_Plot +LIBS:transistors +LIBS:conn +LIBS:eSim_User +LIBS:regul +LIBS:74xx +LIBS:cmos4000 +LIBS:eSim_Analog +LIBS:eSim_Devices +LIBS:eSim_Digital +LIBS:eSim_Hybrid +LIBS:eSim_Miscellaneous +LIBS:eSim_Power +LIBS:eSim_Sources +LIBS:eSim_Subckt +LIBS:eSim_Nghdl +LIBS:eSim_Ngveri +LIBS:lm1458-cache +EELAYER 25 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 1 1 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L eSim_PNP Q5 +U 1 1 631B7C0B +P 2100 1600 +F 0 "Q5" H 2000 1650 50 0000 R CNN +F 1 "eSim_PNP" H 2050 1750 50 0000 R CNN +F 2 "" H 2300 1700 29 0000 C CNN +F 3 "" H 2100 1600 60 0000 C CNN + 1 2100 1600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q9 +U 1 1 631B7C0C +P 2700 1600 +F 0 "Q9" H 2600 1650 50 0000 R CNN +F 1 "eSim_PNP" H 2650 1750 50 0000 R CNN +F 2 "" H 2900 1700 29 0000 C CNN +F 3 "" H 2700 1600 60 0000 C CNN + 1 2700 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q12 +U 1 1 631B7C0D +P 3650 1600 +F 0 "Q12" H 3550 1650 50 0000 R CNN +F 1 "eSim_PNP" H 3600 1750 50 0000 R CNN +F 2 "" H 3850 1700 29 0000 C CNN +F 3 "" H 3650 1600 60 0000 C CNN + 1 3650 1600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q15 +U 1 1 631B7C0E +P 4650 1600 +F 0 "Q15" H 4550 1650 50 0000 R CNN +F 1 "eSim_PNP" H 4600 1750 50 0000 R CNN +F 2 "" H 4850 1700 29 0000 C CNN +F 3 "" H 4650 1600 60 0000 C CNN + 1 4650 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q1 +U 1 1 631B7C0F +P 1150 2300 +F 0 "Q1" H 1050 2350 50 0000 R CNN +F 1 "eSim_NPN" H 1100 2450 50 0000 R CNN +F 2 "" H 1350 2400 29 0000 C CNN +F 3 "" H 1150 2300 60 0000 C CNN + 1 1150 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2300 1600 2500 1600 +Wire Wire Line + 2350 1600 2350 2100 +Wire Wire Line + 1250 1950 2350 1950 +Wire Wire Line + 1250 1950 1250 2100 +Connection ~ 2350 1600 +Wire Wire Line + 2000 1800 2000 1950 +Connection ~ 2000 1950 +$Comp +L eSim_PNP Q2 +U 1 1 631B7C10 +P 1350 3050 +F 0 "Q2" H 1250 3100 50 0000 R CNN +F 1 "eSim_PNP" H 1300 3200 50 0000 R CNN +F 2 "" H 1550 3150 29 0000 C CNN +F 3 "" H 1350 3050 60 0000 C CNN + 1 1350 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 1250 2500 1250 2850 +$Comp +L eSim_NPN Q8 +U 1 1 631B7C11 +P 2450 2300 +F 0 "Q8" H 2350 2350 50 0000 R CNN +F 1 "eSim_NPN" H 2400 2450 50 0000 R CNN +F 2 "" H 2650 2400 29 0000 C CNN +F 3 "" H 2450 2300 60 0000 C CNN + 1 2450 2300 + -1 0 0 -1 +$EndComp +Connection ~ 2350 1950 +$Comp +L eSim_PNP Q6 +U 1 1 631B7C12 +P 2250 3050 +F 0 "Q6" H 2150 3100 50 0000 R CNN +F 1 "eSim_PNP" H 2200 3200 50 0000 R CNN +F 2 "" H 2450 3150 29 0000 C CNN +F 3 "" H 2250 3050 60 0000 C CNN + 1 2250 3050 + 1 0 0 1 +$EndComp +Wire Wire Line + 2350 2850 2350 2500 +Wire Wire Line + 1550 3050 2050 3050 +Wire Wire Line + 2650 2300 2650 2650 +Wire Wire Line + 2650 2650 1000 2650 +Wire Wire Line + 950 2300 750 2300 +$Comp +L eSim_NPN Q4 +U 1 1 631B7C13 +P 1550 3700 +F 0 "Q4" H 1450 3750 50 0000 R CNN +F 1 "eSim_NPN" H 1500 3850 50 0000 R CNN +F 2 "" H 1750 3800 29 0000 C CNN +F 3 "" H 1550 3700 60 0000 C CNN + 1 1550 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1350 3700 1250 3700 +Wire Wire Line + 1250 3250 1250 4200 +Wire Wire Line + 2000 1400 2000 1200 +Wire Wire Line + 1650 1200 10650 1200 +Wire Wire Line + 1650 1200 1650 3500 +Wire Wire Line + 2800 1200 2800 1400 +Connection ~ 2000 1200 +Wire Wire Line + 2800 1800 2800 4200 +Wire Wire Line + 2800 2850 2000 2850 +Wire Wire Line + 2000 2850 2000 3050 +Connection ~ 2000 3050 +Connection ~ 2800 2850 +$Comp +L eSim_NPN Q3 +U 1 1 631B7C14 +P 1350 4400 +F 0 "Q3" H 1250 4450 50 0000 R CNN +F 1 "eSim_NPN" H 1300 4550 50 0000 R CNN +F 2 "" H 1550 4500 29 0000 C CNN +F 3 "" H 1350 4400 60 0000 C CNN + 1 1350 4400 + -1 0 0 -1 +$EndComp +Connection ~ 1250 3700 +Wire Wire Line + 1550 4400 2050 4400 +Wire Wire Line + 1650 4400 1650 3900 +$Comp +L eSim_NPN Q7 +U 1 1 631B7C15 +P 2250 4400 +F 0 "Q7" H 2150 4450 50 0000 R CNN +F 1 "eSim_NPN" H 2200 4550 50 0000 R CNN +F 2 "" H 2450 4500 29 0000 C CNN +F 3 "" H 2250 4400 60 0000 C CNN + 1 2250 4400 + 1 0 0 -1 +$EndComp +Connection ~ 1650 4400 +Wire Wire Line + 2350 3250 2350 4200 +$Comp +L resistor R1 +U 1 1 631B7C16 +P 1200 4850 +F 0 "R1" H 1250 4980 50 0000 C CNN +F 1 "1k" H 1250 4800 50 0000 C CNN +F 2 "" H 1250 4830 30 0000 C CNN +F 3 "" V 1250 4900 30 0000 C CNN + 1 1200 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R2 +U 1 1 631B7C17 +P 1950 4850 +F 0 "R2" H 2000 4980 50 0000 C CNN +F 1 "50k" H 2000 4800 50 0000 C CNN +F 2 "" H 2000 4830 30 0000 C CNN +F 3 "" V 2000 4900 30 0000 C CNN + 1 1950 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R3 +U 1 1 631B7C18 +P 2300 4850 +F 0 "R3" H 2350 4980 50 0000 C CNN +F 1 "1k" H 2350 4800 50 0000 C CNN +F 2 "" H 2350 4830 30 0000 C CNN +F 3 "" V 2350 4900 30 0000 C CNN + 1 2300 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 2350 4750 2350 4600 +Wire Wire Line + 2000 4750 2000 4400 +Connection ~ 2000 4400 +Wire Wire Line + 1250 4750 1250 4600 +Wire Wire Line + 1250 5050 1250 5200 +Wire Wire Line + 2350 5200 2350 5050 +Wire Wire Line + 1250 5200 10650 5200 +Wire Wire Line + 2000 5200 2000 5050 +Connection ~ 2000 5200 +Wire Wire Line + 3550 1200 3550 1400 +Connection ~ 2800 1200 +Wire Wire Line + 3850 1600 4450 1600 +Wire Wire Line + 3900 1600 3900 1850 +Wire Wire Line + 3900 1850 3550 1850 +Wire Wire Line + 3550 1800 3550 2250 +$Comp +L resistor R5 +U 1 1 631B7C19 +P 3500 2350 +F 0 "R5" H 3550 2480 50 0000 C CNN +F 1 "19.5k" H 3550 2300 50 0000 C CNN +F 2 "" H 3550 2330 30 0000 C CNN +F 3 "" V 3550 2400 30 0000 C CNN + 1 3500 2350 + 0 1 1 0 +$EndComp +Connection ~ 3550 1850 +$Comp +L resistor R6 +U 1 1 631B7C1A +P 3500 3250 +F 0 "R6" H 3550 3380 50 0000 C CNN +F 1 "19.5k" H 3550 3200 50 0000 C CNN +F 2 "" H 3550 3230 30 0000 C CNN +F 3 "" V 3550 3300 30 0000 C CNN + 1 3500 3250 + 0 1 1 0 +$EndComp +Wire Wire Line + 3550 2550 3550 3150 +$Comp +L eSim_NPN Q10 +U 1 1 631B7C1B +P 2900 4400 +F 0 "Q10" H 2800 4450 50 0000 R CNN +F 1 "eSim_NPN" H 2850 4550 50 0000 R CNN +F 2 "" H 3100 4500 29 0000 C CNN +F 3 "" H 2900 4400 60 0000 C CNN + 1 2900 4400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q11 +U 1 1 631B7C1C +P 3450 4400 +F 0 "Q11" H 3350 4450 50 0000 R CNN +F 1 "eSim_NPN" H 3400 4550 50 0000 R CNN +F 2 "" H 3650 4500 29 0000 C CNN +F 3 "" H 3450 4400 60 0000 C CNN + 1 3450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3100 4400 3250 4400 +Wire Wire Line + 3550 3450 3550 4200 +$Comp +L resistor R4 +U 1 1 631B7C1D +P 2750 4850 +F 0 "R4" H 2800 4980 50 0000 C CNN +F 1 "5k" H 2800 4800 50 0000 C CNN +F 2 "" H 2800 4830 30 0000 C CNN +F 3 "" V 2800 4900 30 0000 C CNN + 1 2750 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 2800 4750 2800 4600 +Wire Wire Line + 2800 5200 2800 5050 +Connection ~ 2350 5200 +Wire Wire Line + 3550 5200 3550 4600 +Connection ~ 2800 5200 +Wire Wire Line + 4750 1200 4750 1400 +Connection ~ 3550 1200 +Connection ~ 3900 1600 +Wire Wire Line + 2350 3900 3900 3900 +Connection ~ 2350 3900 +$Comp +L capacitor C1 +U 1 1 631B7C1E +P 3800 2900 +F 0 "C1" H 3825 3000 50 0000 L CNN +F 1 "30p" H 3825 2800 50 0000 L CNN +F 2 "" H 3838 2750 30 0000 C CNN +F 3 "" H 3800 2900 60 0000 C CNN + 1 3800 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 3800 3050 3800 4350 +Wire Wire Line + 3800 2750 3800 1900 +Wire Wire Line + 3800 1900 5350 1900 +Wire Wire Line + 4750 1800 4750 2400 +Wire Wire Line + 3200 4400 3200 4150 +Wire Wire Line + 3200 4150 3550 4150 +Connection ~ 3550 4150 +Connection ~ 3200 4400 +$Comp +L eSim_NPN Q13 +U 1 1 631B7C1F +P 3900 4550 +F 0 "Q13" H 3800 4600 50 0000 R CNN +F 1 "eSim_NPN" H 3850 4700 50 0000 R CNN +F 2 "" H 4100 4650 29 0000 C CNN +F 3 "" H 3900 4550 60 0000 C CNN + 1 3900 4550 + -1 0 0 -1 +$EndComp +Connection ~ 3800 3900 +Wire Wire Line + 3800 5200 3800 4750 +Connection ~ 3550 5200 +$Comp +L eSim_NPN Q14 +U 1 1 631B7C20 +P 4100 3900 +F 0 "Q14" H 4000 3950 50 0000 R CNN +F 1 "eSim_NPN" H 4050 4050 50 0000 R CNN +F 2 "" H 4300 4000 29 0000 C CNN +F 3 "" H 4100 3900 60 0000 C CNN + 1 4100 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4100 4550 4750 4550 +Wire Wire Line + 4200 4100 4200 4700 +$Comp +L resistor R7 +U 1 1 631B7C21 +P 4150 4800 +F 0 "R7" H 4200 4930 50 0000 C CNN +F 1 "50k" H 4200 4750 50 0000 C CNN +F 2 "" H 4200 4780 30 0000 C CNN +F 3 "" V 4200 4850 30 0000 C CNN + 1 4150 4800 + 0 1 1 0 +$EndComp +Wire Wire Line + 4200 5200 4200 5000 +Connection ~ 3800 5200 +Wire Wire Line + 4200 3700 4200 3550 +Wire Wire Line + 4200 3550 4900 3550 +$Comp +L eSim_NPN Q16 +U 1 1 631B7C22 +P 4650 2600 +F 0 "Q16" H 4550 2650 50 0000 R CNN +F 1 "eSim_NPN" H 4600 2750 50 0000 R CNN +F 2 "" H 4850 2700 29 0000 C CNN +F 3 "" H 4650 2600 60 0000 C CNN + 1 4650 2600 + 1 0 0 -1 +$EndComp +Connection ~ 4750 1900 +Wire Wire Line + 4750 2800 4750 4050 +Connection ~ 4750 3550 +$Comp +L eSim_NPN Q17 +U 1 1 631B7C23 +P 4650 4250 +F 0 "Q17" H 4550 4300 50 0000 R CNN +F 1 "eSim_NPN" H 4600 4400 50 0000 R CNN +F 2 "" H 4850 4350 29 0000 C CNN +F 3 "" H 4650 4250 60 0000 C CNN + 1 4650 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 4450 4250 4200 4250 +Connection ~ 4200 4250 +Wire Wire Line + 4750 4450 4750 4700 +$Comp +L resistor R10 +U 1 1 631B7C24 +P 4700 4800 +F 0 "R10" H 4750 4930 50 0000 C CNN +F 1 "50" H 4750 4750 50 0000 C CNN +F 2 "" H 4750 4780 30 0000 C CNN +F 3 "" V 4750 4850 30 0000 C CNN + 1 4700 4800 + 0 1 1 0 +$EndComp +Connection ~ 4750 4550 +Wire Wire Line + 4750 5200 4750 5000 +Connection ~ 4200 5200 +$Comp +L resistor R8 +U 1 1 631B7C25 +P 4500 2150 +F 0 "R8" H 4550 2280 50 0000 C CNN +F 1 "4.5k" H 4550 2100 50 0000 C CNN +F 2 "" H 4550 2130 30 0000 C CNN +F 3 "" V 4550 2200 30 0000 C CNN + 1 4500 2150 + -1 0 0 1 +$EndComp +$Comp +L resistor R9 +U 1 1 631B7C26 +P 4500 2900 +F 0 "R9" H 4550 3030 50 0000 C CNN +F 1 "7.5k" H 4550 2850 50 0000 C CNN +F 2 "" H 4550 2880 30 0000 C CNN +F 3 "" V 4550 2950 30 0000 C CNN + 1 4500 2900 + -1 0 0 1 +$EndComp +Wire Wire Line + 4600 2200 4750 2200 +Connection ~ 4750 2200 +Wire Wire Line + 4600 2950 4750 2950 +Connection ~ 4750 2950 +Wire Wire Line + 4450 2600 4100 2600 +Wire Wire Line + 4100 2200 4100 2950 +Wire Wire Line + 4100 2200 4300 2200 +Wire Wire Line + 4100 2950 4300 2950 +Connection ~ 4100 2600 +$Comp +L eSim_NPN Q18 +U 1 1 631B7C27 +P 5250 2500 +F 0 "Q18" H 5150 2550 50 0000 R CNN +F 1 "eSim_NPN" H 5200 2650 50 0000 R CNN +F 2 "" H 5450 2600 29 0000 C CNN +F 3 "" H 5250 2500 60 0000 C CNN + 1 5250 2500 + -1 0 0 -1 +$EndComp +Connection ~ 4750 1200 +Wire Wire Line + 5150 1900 5150 2300 +$Comp +L eSim_NPN Q19 +U 1 1 631B7C28 +P 5550 1900 +F 0 "Q19" H 5450 1950 50 0000 R CNN +F 1 "eSim_NPN" H 5500 2050 50 0000 R CNN +F 2 "" H 5750 2000 29 0000 C CNN +F 3 "" H 5550 1900 60 0000 C CNN + 1 5550 1900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 5650 1700 5650 1200 +Connection ~ 5650 1200 +Connection ~ 5150 1900 +Wire Wire Line + 5450 2500 5650 2500 +Wire Wire Line + 5650 2100 5650 2750 +$Comp +L resistor R11 +U 1 1 631B7C29 +P 5600 2850 +F 0 "R11" H 5650 2980 50 0000 C CNN +F 1 "25" H 5650 2800 50 0000 C CNN +F 2 "" H 5650 2830 30 0000 C CNN +F 3 "" V 5650 2900 30 0000 C CNN + 1 5600 2850 + 0 1 1 0 +$EndComp +Connection ~ 5650 2500 +Wire Wire Line + 5150 2700 5150 3300 +Wire Wire Line + 5150 3300 5650 3300 +Wire Wire Line + 5650 3050 5650 3800 +$Comp +L eSim_Diode D1 +U 1 1 631B7C2A +P 5050 3550 +F 0 "D1" H 5050 3650 50 0000 C CNN +F 1 "eSim_Diode" H 5050 3450 50 0000 C CNN +F 2 "" H 5050 3550 60 0000 C CNN +F 3 "" H 5050 3550 60 0000 C CNN + 1 5050 3550 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D2 +U 1 1 631B7C2B +P 5400 3550 +F 0 "D2" H 5400 3650 50 0000 C CNN +F 1 "eSim_Diode" H 5400 3450 50 0000 C CNN +F 2 "" H 5400 3550 60 0000 C CNN +F 3 "" H 5400 3550 60 0000 C CNN + 1 5400 3550 + -1 0 0 1 +$EndComp +Wire Wire Line + 5250 3550 5200 3550 +Wire Wire Line + 5550 3550 5950 3550 +Connection ~ 5650 3300 +$Comp +L resistor R12 +U 1 1 631B7C2C +P 5600 3900 +F 0 "R12" H 5650 4030 50 0000 C CNN +F 1 "50" H 5650 3850 50 0000 C CNN +F 2 "" H 5650 3880 30 0000 C CNN +F 3 "" V 5650 3950 30 0000 C CNN + 1 5600 3900 + 0 1 1 0 +$EndComp +Connection ~ 5650 3550 +$Comp +L eSim_PNP Q20 +U 1 1 631B7C2D +P 5550 4550 +F 0 "Q20" H 5450 4600 50 0000 R CNN +F 1 "eSim_PNP" H 5500 4700 50 0000 R CNN +F 2 "" H 5750 4650 29 0000 C CNN +F 3 "" H 5550 4550 60 0000 C CNN + 1 5550 4550 + 1 0 0 1 +$EndComp +Wire Wire Line + 5650 4350 5650 4100 +Wire Wire Line + 4750 3850 4900 3850 +Wire Wire Line + 4900 3850 4900 4550 +Wire Wire Line + 4900 4550 5350 4550 +Connection ~ 4750 3850 +Wire Wire Line + 5650 5200 5650 4750 +Connection ~ 4750 5200 +Connection ~ 5650 5200 +$Comp +L eSim_PNP Q25 +U 1 1 631B7C2E +P 7100 1600 +F 0 "Q25" H 7000 1650 50 0000 R CNN +F 1 "eSim_PNP" H 7050 1750 50 0000 R CNN +F 2 "" H 7300 1700 29 0000 C CNN +F 3 "" H 7100 1600 60 0000 C CNN + 1 7100 1600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q29 +U 1 1 631B7C2F +P 7700 1600 +F 0 "Q29" H 7600 1650 50 0000 R CNN +F 1 "eSim_PNP" H 7650 1750 50 0000 R CNN +F 2 "" H 7900 1700 29 0000 C CNN +F 3 "" H 7700 1600 60 0000 C CNN + 1 7700 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q32 +U 1 1 631B7C30 +P 8650 1600 +F 0 "Q32" H 8550 1650 50 0000 R CNN +F 1 "eSim_PNP" H 8600 1750 50 0000 R CNN +F 2 "" H 8850 1700 29 0000 C CNN +F 3 "" H 8650 1600 60 0000 C CNN + 1 8650 1600 + -1 0 0 1 +$EndComp +$Comp +L eSim_PNP Q35 +U 1 1 631B7C31 +P 9650 1600 +F 0 "Q35" H 9550 1650 50 0000 R CNN +F 1 "eSim_PNP" H 9600 1750 50 0000 R CNN +F 2 "" H 9850 1700 29 0000 C CNN +F 3 "" H 9650 1600 60 0000 C CNN + 1 9650 1600 + 1 0 0 1 +$EndComp +$Comp +L eSim_NPN Q21 +U 1 1 631B7C32 +P 6150 2300 +F 0 "Q21" H 6050 2350 50 0000 R CNN +F 1 "eSim_NPN" H 6100 2450 50 0000 R CNN +F 2 "" H 6350 2400 29 0000 C CNN +F 3 "" H 6150 2300 60 0000 C CNN + 1 6150 2300 + 1 0 0 -1 +$EndComp +Wire Wire Line + 7300 1600 7500 1600 +Wire Wire Line + 7350 1600 7350 2100 +Wire Wire Line + 6250 1950 7350 1950 +Wire Wire Line + 6250 1950 6250 2100 +Connection ~ 7350 1600 +Wire Wire Line + 7000 1800 7000 1950 +Connection ~ 7000 1950 +$Comp +L eSim_PNP Q22 +U 1 1 631B7C33 +P 6350 3050 +F 0 "Q22" H 6250 3100 50 0000 R CNN +F 1 "eSim_PNP" H 6300 3200 50 0000 R CNN +F 2 "" H 6550 3150 29 0000 C CNN +F 3 "" H 6350 3050 60 0000 C CNN + 1 6350 3050 + -1 0 0 1 +$EndComp +Wire Wire Line + 6250 2500 6250 2850 +$Comp +L eSim_NPN Q28 +U 1 1 631B7C34 +P 7450 2300 +F 0 "Q28" H 7350 2350 50 0000 R CNN +F 1 "eSim_NPN" H 7400 2450 50 0000 R CNN +F 2 "" H 7650 2400 29 0000 C CNN +F 3 "" H 7450 2300 60 0000 C CNN + 1 7450 2300 + -1 0 0 -1 +$EndComp +Connection ~ 7350 1950 +$Comp +L eSim_PNP Q26 +U 1 1 631B7C35 +P 7250 3050 +F 0 "Q26" H 7150 3100 50 0000 R CNN +F 1 "eSim_PNP" H 7200 3200 50 0000 R CNN +F 2 "" H 7450 3150 29 0000 C CNN +F 3 "" H 7250 3050 60 0000 C CNN + 1 7250 3050 + 1 0 0 1 +$EndComp +Wire Wire Line + 7350 2850 7350 2500 +Wire Wire Line + 6550 3050 7050 3050 +Wire Wire Line + 7650 2300 7650 2650 +Wire Wire Line + 7650 2650 6650 2650 +Wire Wire Line + 5950 2300 5900 2300 +$Comp +L eSim_NPN Q24 +U 1 1 631B7C36 +P 6550 3700 +F 0 "Q24" H 6450 3750 50 0000 R CNN +F 1 "eSim_NPN" H 6500 3850 50 0000 R CNN +F 2 "" H 6750 3800 29 0000 C CNN +F 3 "" H 6550 3700 60 0000 C CNN + 1 6550 3700 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6350 3700 6250 3700 +Wire Wire Line + 6250 3250 6250 4200 +Wire Wire Line + 7000 1200 7000 1400 +Wire Wire Line + 6650 1200 6650 3500 +Wire Wire Line + 7800 1200 7800 1400 +Connection ~ 7000 1200 +Wire Wire Line + 7800 1800 7800 4200 +Wire Wire Line + 7800 2850 7000 2850 +Wire Wire Line + 7000 2850 7000 3050 +Connection ~ 7000 3050 +Connection ~ 7800 2850 +$Comp +L eSim_NPN Q23 +U 1 1 631B7C37 +P 6350 4400 +F 0 "Q23" H 6250 4450 50 0000 R CNN +F 1 "eSim_NPN" H 6300 4550 50 0000 R CNN +F 2 "" H 6550 4500 29 0000 C CNN +F 3 "" H 6350 4400 60 0000 C CNN + 1 6350 4400 + -1 0 0 -1 +$EndComp +Connection ~ 6250 3700 +Wire Wire Line + 6550 4400 7050 4400 +Wire Wire Line + 6650 4400 6650 3900 +$Comp +L eSim_NPN Q27 +U 1 1 631B7C38 +P 7250 4400 +F 0 "Q27" H 7150 4450 50 0000 R CNN +F 1 "eSim_NPN" H 7200 4550 50 0000 R CNN +F 2 "" H 7450 4500 29 0000 C CNN +F 3 "" H 7250 4400 60 0000 C CNN + 1 7250 4400 + 1 0 0 -1 +$EndComp +Connection ~ 6650 4400 +Wire Wire Line + 7350 3250 7350 4200 +$Comp +L resistor R13 +U 1 1 631B7C39 +P 6200 4850 +F 0 "R13" H 6250 4980 50 0000 C CNN +F 1 "1k" H 6250 4800 50 0000 C CNN +F 2 "" H 6250 4830 30 0000 C CNN +F 3 "" V 6250 4900 30 0000 C CNN + 1 6200 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R14 +U 1 1 631B7C3A +P 6950 4850 +F 0 "R14" H 7000 4980 50 0000 C CNN +F 1 "50k" H 7000 4800 50 0000 C CNN +F 2 "" H 7000 4830 30 0000 C CNN +F 3 "" V 7000 4900 30 0000 C CNN + 1 6950 4850 + 0 1 1 0 +$EndComp +$Comp +L resistor R15 +U 1 1 631B7C3B +P 7300 4850 +F 0 "R15" H 7350 4980 50 0000 C CNN +F 1 "1k" H 7350 4800 50 0000 C CNN +F 2 "" H 7350 4830 30 0000 C CNN +F 3 "" V 7350 4900 30 0000 C CNN + 1 7300 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 7350 4750 7350 4600 +Wire Wire Line + 7000 4750 7000 4400 +Connection ~ 7000 4400 +Wire Wire Line + 6250 4750 6250 4600 +Wire Wire Line + 6250 5200 6250 5050 +Wire Wire Line + 7350 5200 7350 5050 +Wire Wire Line + 7000 5200 7000 5050 +Connection ~ 7000 5200 +Wire Wire Line + 8550 1200 8550 1400 +Connection ~ 7800 1200 +Wire Wire Line + 8850 1600 9450 1600 +Wire Wire Line + 8900 1600 8900 1850 +Wire Wire Line + 8900 1850 8550 1850 +Wire Wire Line + 8550 1800 8550 2250 +$Comp +L resistor R17 +U 1 1 631B7C3C +P 8500 2350 +F 0 "R17" H 8550 2480 50 0000 C CNN +F 1 "19.5k" H 8550 2300 50 0000 C CNN +F 2 "" H 8550 2330 30 0000 C CNN +F 3 "" V 8550 2400 30 0000 C CNN + 1 8500 2350 + 0 1 1 0 +$EndComp +Connection ~ 8550 1850 +$Comp +L resistor R18 +U 1 1 631B7C3D +P 8500 3250 +F 0 "R18" H 8550 3380 50 0000 C CNN +F 1 "19.5k" H 8550 3200 50 0000 C CNN +F 2 "" H 8550 3230 30 0000 C CNN +F 3 "" V 8550 3300 30 0000 C CNN + 1 8500 3250 + 0 1 1 0 +$EndComp +Wire Wire Line + 8550 2550 8550 3150 +$Comp +L eSim_NPN Q30 +U 1 1 631B7C3E +P 7900 4400 +F 0 "Q30" H 7800 4450 50 0000 R CNN +F 1 "eSim_NPN" H 7850 4550 50 0000 R CNN +F 2 "" H 8100 4500 29 0000 C CNN +F 3 "" H 7900 4400 60 0000 C CNN + 1 7900 4400 + -1 0 0 -1 +$EndComp +$Comp +L eSim_NPN Q31 +U 1 1 631B7C3F +P 8450 4400 +F 0 "Q31" H 8350 4450 50 0000 R CNN +F 1 "eSim_NPN" H 8400 4550 50 0000 R CNN +F 2 "" H 8650 4500 29 0000 C CNN +F 3 "" H 8450 4400 60 0000 C CNN + 1 8450 4400 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8100 4400 8250 4400 +Wire Wire Line + 8550 3450 8550 4200 +$Comp +L resistor R16 +U 1 1 631B7C40 +P 7750 4850 +F 0 "R16" H 7800 4980 50 0000 C CNN +F 1 "5k" H 7800 4800 50 0000 C CNN +F 2 "" H 7800 4830 30 0000 C CNN +F 3 "" V 7800 4900 30 0000 C CNN + 1 7750 4850 + 0 1 1 0 +$EndComp +Wire Wire Line + 7800 4750 7800 4600 +Wire Wire Line + 7800 5200 7800 5050 +Connection ~ 7350 5200 +Wire Wire Line + 8550 5200 8550 4600 +Connection ~ 7800 5200 +Wire Wire Line + 9750 1200 9750 1400 +Connection ~ 8550 1200 +Connection ~ 8900 1600 +Wire Wire Line + 7350 3900 8900 3900 +Connection ~ 7350 3900 +$Comp +L capacitor C2 +U 1 1 631B7C41 +P 8800 2900 +F 0 "C2" H 8825 3000 50 0000 L CNN +F 1 "30p" H 8825 2800 50 0000 L CNN +F 2 "" H 8838 2750 30 0000 C CNN +F 3 "" H 8800 2900 60 0000 C CNN + 1 8800 2900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 8800 3050 8800 4350 +Wire Wire Line + 8800 2750 8800 1900 +Wire Wire Line + 8800 1900 10350 1900 +Wire Wire Line + 9750 1800 9750 2400 +Wire Wire Line + 8200 4400 8200 4150 +Wire Wire Line + 8200 4150 8550 4150 +Connection ~ 8550 4150 +Connection ~ 8200 4400 +$Comp +L eSim_NPN Q33 +U 1 1 631B7C42 +P 8900 4550 +F 0 "Q33" H 8800 4600 50 0000 R CNN +F 1 "eSim_NPN" H 8850 4700 50 0000 R CNN +F 2 "" H 9100 4650 29 0000 C CNN +F 3 "" H 8900 4550 60 0000 C CNN + 1 8900 4550 + -1 0 0 -1 +$EndComp +Connection ~ 8800 3900 +Wire Wire Line + 8800 5200 8800 4750 +Connection ~ 8550 5200 +$Comp +L eSim_NPN Q34 +U 1 1 631B7C43 +P 9100 3900 +F 0 "Q34" H 9000 3950 50 0000 R CNN +F 1 "eSim_NPN" H 9050 4050 50 0000 R CNN +F 2 "" H 9300 4000 29 0000 C CNN +F 3 "" H 9100 3900 60 0000 C CNN + 1 9100 3900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9100 4550 9750 4550 +Wire Wire Line + 9200 4100 9200 4700 +$Comp +L resistor R19 +U 1 1 631B7C44 +P 9150 4800 +F 0 "R19" H 9200 4930 50 0000 C CNN +F 1 "50k" H 9200 4750 50 0000 C CNN +F 2 "" H 9200 4780 30 0000 C CNN +F 3 "" V 9200 4850 30 0000 C CNN + 1 9150 4800 + 0 1 1 0 +$EndComp +Wire Wire Line + 9200 5200 9200 5000 +Connection ~ 8800 5200 +Wire Wire Line + 9200 3700 9200 3550 +Wire Wire Line + 9200 3550 9900 3550 +$Comp +L eSim_NPN Q36 +U 1 1 631B7C45 +P 9650 2600 +F 0 "Q36" H 9550 2650 50 0000 R CNN +F 1 "eSim_NPN" H 9600 2750 50 0000 R CNN +F 2 "" H 9850 2700 29 0000 C CNN +F 3 "" H 9650 2600 60 0000 C CNN + 1 9650 2600 + 1 0 0 -1 +$EndComp +Connection ~ 9750 1900 +Wire Wire Line + 9750 2800 9750 4050 +Connection ~ 9750 3550 +$Comp +L eSim_NPN Q37 +U 1 1 631B7C46 +P 9650 4250 +F 0 "Q37" H 9550 4300 50 0000 R CNN +F 1 "eSim_NPN" H 9600 4400 50 0000 R CNN +F 2 "" H 9850 4350 29 0000 C CNN +F 3 "" H 9650 4250 60 0000 C CNN + 1 9650 4250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 9450 4250 9200 4250 +Connection ~ 9200 4250 +Wire Wire Line + 9750 4450 9750 4700 +$Comp +L resistor R22 +U 1 1 631B7C47 +P 9700 4800 +F 0 "R22" H 9750 4930 50 0000 C CNN +F 1 "50" H 9750 4750 50 0000 C CNN +F 2 "" H 9750 4780 30 0000 C CNN +F 3 "" V 9750 4850 30 0000 C CNN + 1 9700 4800 + 0 1 1 0 +$EndComp +Connection ~ 9750 4550 +Wire Wire Line + 9750 5200 9750 5000 +Connection ~ 9200 5200 +$Comp +L resistor R20 +U 1 1 631B7C48 +P 9500 2150 +F 0 "R20" H 9550 2280 50 0000 C CNN +F 1 "4.5k" H 9550 2100 50 0000 C CNN +F 2 "" H 9550 2130 30 0000 C CNN +F 3 "" V 9550 2200 30 0000 C CNN + 1 9500 2150 + -1 0 0 1 +$EndComp +$Comp +L resistor R21 +U 1 1 631B7C49 +P 9500 2900 +F 0 "R21" H 9550 3030 50 0000 C CNN +F 1 "7.5k" H 9550 2850 50 0000 C CNN +F 2 "" H 9550 2880 30 0000 C CNN +F 3 "" V 9550 2950 30 0000 C CNN + 1 9500 2900 + -1 0 0 1 +$EndComp +Wire Wire Line + 9600 2200 9750 2200 +Connection ~ 9750 2200 +Wire Wire Line + 9600 2950 9750 2950 +Connection ~ 9750 2950 +Wire Wire Line + 9450 2600 9100 2600 +Wire Wire Line + 9100 2200 9100 2950 +Wire Wire Line + 9100 2200 9300 2200 +Wire Wire Line + 9100 2950 9300 2950 +Connection ~ 9100 2600 +$Comp +L eSim_NPN Q38 +U 1 1 631B7C4A +P 10250 2500 +F 0 "Q38" H 10150 2550 50 0000 R CNN +F 1 "eSim_NPN" H 10200 2650 50 0000 R CNN +F 2 "" H 10450 2600 29 0000 C CNN +F 3 "" H 10250 2500 60 0000 C CNN + 1 10250 2500 + -1 0 0 -1 +$EndComp +Connection ~ 9750 1200 +Wire Wire Line + 10150 1900 10150 2300 +$Comp +L eSim_NPN Q39 +U 1 1 631B7C4B +P 10550 1900 +F 0 "Q39" H 10450 1950 50 0000 R CNN +F 1 "eSim_NPN" H 10500 2050 50 0000 R CNN +F 2 "" H 10750 2000 29 0000 C CNN +F 3 "" H 10550 1900 60 0000 C CNN + 1 10550 1900 + 1 0 0 -1 +$EndComp +Wire Wire Line + 10650 1200 10650 1700 +Connection ~ 10150 1900 +Wire Wire Line + 10450 2500 10650 2500 +Wire Wire Line + 10650 2100 10650 2750 +$Comp +L resistor R23 +U 1 1 631B7C4C +P 10600 2850 +F 0 "R23" H 10650 2980 50 0000 C CNN +F 1 "25" H 10650 2800 50 0000 C CNN +F 2 "" H 10650 2830 30 0000 C CNN +F 3 "" V 10650 2900 30 0000 C CNN + 1 10600 2850 + 0 1 1 0 +$EndComp +Connection ~ 10650 2500 +Wire Wire Line + 10150 2700 10150 3300 +Wire Wire Line + 10150 3300 10650 3300 +Wire Wire Line + 10650 3050 10650 3800 +$Comp +L eSim_Diode D3 +U 1 1 631B7C4D +P 10050 3550 +F 0 "D3" H 10050 3650 50 0000 C CNN +F 1 "eSim_Diode" H 10050 3450 50 0000 C CNN +F 2 "" H 10050 3550 60 0000 C CNN +F 3 "" H 10050 3550 60 0000 C CNN + 1 10050 3550 + -1 0 0 1 +$EndComp +$Comp +L eSim_Diode D4 +U 1 1 631B7C4E +P 10400 3550 +F 0 "D4" H 10400 3650 50 0000 C CNN +F 1 "eSim_Diode" H 10400 3450 50 0000 C CNN +F 2 "" H 10400 3550 60 0000 C CNN +F 3 "" H 10400 3550 60 0000 C CNN + 1 10400 3550 + -1 0 0 1 +$EndComp +Wire Wire Line + 10250 3550 10200 3550 +Wire Wire Line + 10550 3550 10950 3550 +Connection ~ 10650 3300 +$Comp +L resistor R24 +U 1 1 631B7C4F +P 10600 3900 +F 0 "R24" H 10650 4030 50 0000 C CNN +F 1 "50" H 10650 3850 50 0000 C CNN +F 2 "" H 10650 3880 30 0000 C CNN +F 3 "" V 10650 3950 30 0000 C CNN + 1 10600 3900 + 0 1 1 0 +$EndComp +Connection ~ 10650 3550 +$Comp +L eSim_PNP Q40 +U 1 1 631B7C50 +P 10550 4550 +F 0 "Q40" H 10450 4600 50 0000 R CNN +F 1 "eSim_PNP" H 10500 4700 50 0000 R CNN +F 2 "" H 10750 4650 29 0000 C CNN +F 3 "" H 10550 4550 60 0000 C CNN + 1 10550 4550 + 1 0 0 1 +$EndComp +Wire Wire Line + 10650 4350 10650 4100 +Wire Wire Line + 9750 3850 9900 3850 +Wire Wire Line + 9900 3850 9900 4550 +Wire Wire Line + 9900 4550 10350 4550 +Connection ~ 9750 3850 +Wire Wire Line + 10650 5200 10650 4750 +Connection ~ 9750 5200 +Connection ~ 6650 1200 +Connection ~ 6250 5200 +$Comp +L PORT U1 +U 1 1 631B7C51 +P 750 2550 +F 0 "U1" H 800 2650 30 0000 C CNN +F 1 "PORT" H 750 2550 30 0000 C CNN +F 2 "" H 750 2550 60 0000 C CNN +F 3 "" H 750 2550 60 0000 C CNN + 1 750 2550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 2 1 631B7C52 +P 1000 2900 +F 0 "U1" H 1050 3000 30 0000 C CNN +F 1 "PORT" H 1000 2900 30 0000 C CNN +F 2 "" H 1000 2900 60 0000 C CNN +F 3 "" H 1000 2900 60 0000 C CNN + 2 1000 2900 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 6 1 631B7C53 +P 5950 3800 +F 0 "U1" H 6000 3900 30 0000 C CNN +F 1 "PORT" H 5950 3800 30 0000 C CNN +F 2 "" H 5950 3800 60 0000 C CNN +F 3 "" H 5950 3800 60 0000 C CNN + 6 5950 3800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 4 1 631B7C54 +P 5900 2550 +F 0 "U1" H 5950 2650 30 0000 C CNN +F 1 "PORT" H 5900 2550 30 0000 C CNN +F 2 "" H 5900 2550 60 0000 C CNN +F 3 "" H 5900 2550 60 0000 C CNN + 4 5900 2550 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 7 1 631B7C55 +P 6400 2650 +F 0 "U1" H 6450 2750 30 0000 C CNN +F 1 "PORT" H 6400 2650 30 0000 C CNN +F 2 "" H 6400 2650 60 0000 C CNN +F 3 "" H 6400 2650 60 0000 C CNN + 7 6400 2650 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 8 1 631B7C56 +P 10950 3800 +F 0 "U1" H 11000 3900 30 0000 C CNN +F 1 "PORT" H 10950 3800 30 0000 C CNN +F 2 "" H 10950 3800 60 0000 C CNN +F 3 "" H 10950 3800 60 0000 C CNN + 8 10950 3800 + 0 -1 -1 0 +$EndComp +$Comp +L PORT U1 +U 3 1 631B7C57 +P 5700 5500 +F 0 "U1" H 5750 5600 30 0000 C CNN +F 1 "PORT" H 5700 5500 30 0000 C CNN +F 2 "" H 5700 5500 60 0000 C CNN +F 3 "" H 5700 5500 60 0000 C CNN + 3 5700 5500 + 1 0 0 -1 +$EndComp +$Comp +L PORT U1 +U 5 1 631B7C58 +P 5950 950 +F 0 "U1" H 6000 1050 30 0000 C CNN +F 1 "PORT" H 5950 950 30 0000 C CNN +F 2 "" H 5950 950 60 0000 C CNN +F 3 "" H 5950 950 60 0000 C CNN + 5 5950 950 + 1 0 0 -1 +$EndComp +Wire Wire Line + 6200 950 6250 950 +Connection ~ 6250 1200 +Wire Wire Line + 5950 5500 6000 5500 +Wire Wire Line + 6000 5500 6000 5200 +Connection ~ 6000 5200 +Wire Wire Line + 6250 950 6250 1200 +$EndSCHEMATC diff --git a/library/SubcircuitLibrary/lm1458/lm1458.sub b/library/SubcircuitLibrary/lm1458/lm1458.sub new file mode 100644 index 000000000..8c0eb086b --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458.sub @@ -0,0 +1,79 @@ +* Subcircuit lm1458 +.subckt lm1458 net-_q1-pad2_ net-_q8-pad2_ net-_q11-pad3_ net-_q21-pad2_ net-_q12-pad3_ net-_d2-pad1_ net-_q28-pad2_ net-_d4-pad1_ +* c:\fossee\esim\library\subcircuitlibrary\lm1458\lm1458.cir +.include D.lib +.include NPN.lib +.include PNP.lib +q5 net-_q1-pad1_ net-_q1-pad1_ net-_q12-pad3_ Q2N2907A +q9 net-_q10-pad1_ net-_q1-pad1_ net-_q12-pad3_ Q2N2907A +q12 net-_q12-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2907A +q15 net-_c1-pad1_ net-_q12-pad1_ net-_q12-pad3_ Q2N2907A +q1 net-_q1-pad1_ net-_q1-pad2_ net-_q1-pad3_ Q2N2222 +q2 net-_q2-pad1_ net-_q10-pad1_ net-_q1-pad3_ Q2N2907A +q8 net-_q1-pad1_ net-_q8-pad2_ net-_q6-pad3_ Q2N2222 +q6 net-_c1-pad2_ net-_q10-pad1_ net-_q6-pad3_ Q2N2907A +q4 net-_q12-pad3_ net-_q2-pad1_ net-_q3-pad2_ Q2N2222 +q3 net-_q2-pad1_ net-_q3-pad2_ net-_q3-pad3_ Q2N2222 +q7 net-_c1-pad2_ net-_q3-pad2_ net-_q7-pad3_ Q2N2222 +r1 net-_q3-pad3_ net-_q11-pad3_ 1k +r2 net-_q3-pad2_ net-_q11-pad3_ 50k +r3 net-_q7-pad3_ net-_q11-pad3_ 1k +r5 net-_q12-pad1_ net-_r5-pad2_ 19.5k +r6 net-_r5-pad2_ net-_q10-pad2_ 19.5k +q10 net-_q10-pad1_ net-_q10-pad2_ net-_q10-pad3_ Q2N2222 +q11 net-_q10-pad2_ net-_q10-pad2_ net-_q11-pad3_ Q2N2222 +r4 net-_q10-pad3_ net-_q11-pad3_ 5k +c1 net-_c1-pad1_ net-_c1-pad2_ 30p +q13 net-_c1-pad2_ net-_q13-pad2_ net-_q11-pad3_ Q2N2222 +q14 net-_d1-pad2_ net-_c1-pad2_ net-_q14-pad3_ Q2N2222 +r7 net-_q14-pad3_ net-_q11-pad3_ 50k +q16 net-_c1-pad1_ net-_q16-pad2_ net-_d1-pad2_ Q2N2222 +q17 net-_d1-pad2_ net-_q14-pad3_ net-_q13-pad2_ Q2N2222 +r10 net-_q13-pad2_ net-_q11-pad3_ 50 +r8 net-_c1-pad1_ net-_q16-pad2_ 4.5k +r9 net-_d1-pad2_ net-_q16-pad2_ 7.5k +q18 net-_c1-pad1_ net-_q18-pad2_ net-_d2-pad1_ Q2N2222 +q19 net-_q12-pad3_ net-_c1-pad1_ net-_q18-pad2_ Q2N2222 +r11 net-_q18-pad2_ net-_d2-pad1_ 25 +d1 net-_d1-pad1_ net-_d1-pad2_ 1N4148 +d2 net-_d2-pad1_ net-_d1-pad1_ 1N4148 +r12 net-_d2-pad1_ net-_q20-pad3_ 50 +q20 net-_q11-pad3_ net-_d1-pad2_ net-_q20-pad3_ Q2N2907A +q25 net-_q21-pad1_ net-_q21-pad1_ net-_q12-pad3_ Q2N2907A +q29 net-_q22-pad2_ net-_q21-pad1_ net-_q12-pad3_ Q2N2907A +q32 net-_q32-pad1_ net-_q32-pad1_ net-_q12-pad3_ Q2N2907A +q35 net-_c2-pad1_ net-_q32-pad1_ net-_q12-pad3_ Q2N2907A +q21 net-_q21-pad1_ net-_q21-pad2_ net-_q21-pad3_ Q2N2222 +q22 net-_q22-pad1_ net-_q22-pad2_ net-_q21-pad3_ Q2N2907A +q28 net-_q21-pad1_ net-_q28-pad2_ net-_q26-pad3_ Q2N2222 +q26 net-_c2-pad2_ net-_q22-pad2_ net-_q26-pad3_ Q2N2907A +q24 net-_q12-pad3_ net-_q22-pad1_ net-_q23-pad2_ Q2N2222 +q23 net-_q22-pad1_ net-_q23-pad2_ net-_q23-pad3_ Q2N2222 +q27 net-_c2-pad2_ net-_q23-pad2_ net-_q27-pad3_ Q2N2222 +r13 net-_q23-pad3_ net-_q11-pad3_ 1k +r14 net-_q23-pad2_ net-_q11-pad3_ 50k +r15 net-_q27-pad3_ net-_q11-pad3_ 1k +r17 net-_q32-pad1_ net-_r17-pad2_ 19.5k +r18 net-_r17-pad2_ net-_q30-pad2_ 19.5k +q30 net-_q22-pad2_ net-_q30-pad2_ net-_q30-pad3_ Q2N2222 +q31 net-_q30-pad2_ net-_q30-pad2_ net-_q11-pad3_ Q2N2222 +r16 net-_q30-pad3_ net-_q11-pad3_ 5k +c2 net-_c2-pad1_ net-_c2-pad2_ 30p +q33 net-_c2-pad2_ net-_q33-pad2_ net-_q11-pad3_ Q2N2222 +q34 net-_d3-pad2_ net-_c2-pad2_ net-_q34-pad3_ Q2N2222 +r19 net-_q34-pad3_ net-_q11-pad3_ 50k +q36 net-_c2-pad1_ net-_q36-pad2_ net-_d3-pad2_ Q2N2222 +q37 net-_d3-pad2_ net-_q34-pad3_ net-_q33-pad2_ Q2N2222 +r22 net-_q33-pad2_ net-_q11-pad3_ 50 +r20 net-_c2-pad1_ net-_q36-pad2_ 4.5k +r21 net-_d3-pad2_ net-_q36-pad2_ 7.5k +q38 net-_c2-pad1_ net-_q38-pad2_ net-_d4-pad1_ Q2N2222 +q39 net-_q12-pad3_ net-_c2-pad1_ net-_q38-pad2_ Q2N2222 +r23 net-_q38-pad2_ net-_d4-pad1_ 25 +d3 net-_d3-pad1_ net-_d3-pad2_ 1N4148 +d4 net-_d4-pad1_ net-_d3-pad1_ 1N4148 +r24 net-_d4-pad1_ net-_q40-pad3_ 50 +q40 net-_q11-pad3_ net-_d3-pad2_ net-_q40-pad3_ Q2N2907A +* Control Statements + +.ends lm1458 \ No newline at end of file diff --git a/library/SubcircuitLibrary/lm1458/lm1458_Previous_Values.xml b/library/SubcircuitLibrary/lm1458/lm1458_Previous_Values.xml new file mode 100644 index 000000000..0ce355b4c --- /dev/null +++ b/library/SubcircuitLibrary/lm1458/lm1458_Previous_Values.xml @@ -0,0 +1 @@ +truefalsefalseHzHz0Volts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesVolts or AmperesSecSecSecC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\NPN.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Diode\D.libC:\FOSSEE\eSim\library\deviceModelLibrary\Transistor\PNP.lib \ No newline at end of file