CLK_PULSE.EXP

(* @NESTEDCOMMENTS := 'Yes' *)
(* @PATH := '\/Logic\/generators' *)
(* @OBJECTFLAGS := '0, 8' *)
(* @SYMFILEFLAGS := '2048' *)
FUNCTION_BLOCK CLK_PULSE
VAR_INPUT
	PT : TIME;
	N : INT;
	RST : BOOL ;
END_VAR
VAR_OUTPUT
	Q : BOOL;
	CNT : INT;
	RUN : BOOL;
END_VAR
VAR
	tx, tn: DWORD;
	init: BOOL;
END_VAR

(*
version 1.2		16 feb 2011
programmer 	hugo
tested by		oscat

clk_pulse uses the internal sps time to generate a clock with programmable period time.
the period time is defined for 10ms .. 65s.
pulse generation is continuous if N = 0 and for n pulses otherwise.
the first cycle after start is a clk pulse and then depending on the programmed period time a delay.
every pulse is only valid for one cycle so that a edge trigger is not necessary
clk_prg depending on the accuracy of the system clock.

*)
(* @END_DECLARATION := '0' *)
tx := T_PLC_MS();		(* read system *)
Q := FALSE;				(* reset Q we generate pulses only for one cycle *)
RUN := CNT < N;

IF NOT init OR RST THEN
	init := TRUE;
	CNT := 0;
	tn := tx - TIME_TO_DWORD(PT);
	RUN := FALSE;
ELSIF (cnt < N OR N = 0) AND tx - tn >= TIME_TO_DWORD(PT) THEN		(* generate a pulse *)
	CNT := CNT + 1;
	Q := TRUE;
	tn := tn + TIME_TO_DWORD(PT);
END_IF;



(* revision history
hm		4. aug 2006		rev 1.0
	original version

hm		17. sep 2007	rev 1.1
	replaced time() with T_PLC_S() for compatblity reasons

hm		16. feb. 2011	rev 1.2
	fixed an error when timer overflows 
*)
END_FUNCTION_BLOCK