Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

morello atomic: Trim gcvalue from the spin loop of arithmetic atomics #2249

Open
wants to merge 1 commit into
base: dev
Choose a base branch
from

Conversation

bsdjhb
Copy link
Collaborator

@bsdjhb bsdjhb commented Nov 15, 2024

Use a ptraddr_t as the input that can be assigned to the register
constraint as is done for RISC-V. This allows the compiler to either
hoist the gcvalue out of the loop, or to just use the x portion of the
relevant register.

Use a ptraddr_t as the input that can be assigned to the register
constraint as is done for RISC-V.  This allows the compiler to either
hoist the gcvalue out of the loop, or to just use the x portion of the
relevant register.
@bsdjhb bsdjhb requested a review from jrtc27 November 15, 2024 16:25
@@ -667,21 +667,19 @@ static __inline void \
atomic_##op##_##bar##ptr(volatile uintptr_t *p, uintptr_t val) \
{ \
uintptr_t previous; \
ptraddr_t tmp1, tmp2; \
ptraddr_t tmp; \
int res; \
\
__asm __volatile( \
"1:" \
"ld" #a "xr %0, [%4]\n" \
"gcvalue %2, %0\n" \
Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This could be eliminated if there was an equivalent to %wN to denote the X version of the C register as then we could use that as the second operand in the scvalue instruction below.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants