How to to generate traces using timing.core or simple.core?

[manwu1994]

Has anyone attempted to generate traces using timing.core or simple.core, or to build a PIM architecture based on these cores? If so, I would greatly appreciate any insights or suggestions.

I am looking to build a PIM architecture using timing.core or simple.core instead of ooo.core and subsequently generate memory access traces.

Any guidance, references to similar projects, or detailed steps on how to approach this modification would be extremely helpful. Thank you!