From aac05ad318a7c7ab99392a9d5d87a1e33b91cd54 Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Thu, 23 Jun 2022 21:29:54 +0800 Subject: [PATCH] initialized to zero all registered outputs --- rtl/rv32i_csr.v | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/rtl/rv32i_csr.v b/rtl/rv32i_csr.v index e41db0b..b6959e0 100644 --- a/rtl/rv32i_csr.v +++ b/rtl/rv32i_csr.v @@ -43,6 +43,14 @@ module rv32i_csr #(parameter CLK_FREQ_MHZ = 100, TRAP_ADDRESS = 0) ( input wire i_change_pc, //high if PC needs to jump input wire i_ce // input clk enable for pipeline stalling of this stage ); + initial begin + o_csr_out = 0; + o_return_address = 0; + o_trap_address = 0; + o_go_to_trap_q = 0; + o_return_from_trap_q = 0; + end + //CSR operation type localparam CSRRW = 3'b001, CSRRS = 3'b010,