From 763bb52038d03a5ab6a90638ae6b785333b6260a Mon Sep 17 00:00:00 2001 From: Angelo Jacobo Date: Thu, 23 Jun 2022 22:18:32 +0800 Subject: [PATCH] edited Pipeline Features and image --- README.md | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index de8bebc..ed4c7bb 100644 --- a/README.md +++ b/README.md @@ -20,12 +20,12 @@ Inside the `rtl/` folder are the following: - `extra/` folder = contains my own assembly testfiles for all basic instructions, system instructions, and pipeline hazards ## Pipeline Features - - 5 pipeline stages - - Separate data and instruction memory interface [Harvard architecture] + - 5 pipelined stages + - Separate data and instruction memory interface **[Harvard architecture]** - Load instructions take a minimum of 2 clk cycles - - Taken branch and jump instructions take a minimum of 6 clk cycles [No Branch Prediction Used] - - Two **consecutive** instructions with data dependency take a minimum of 2 clk cycles. Nonconsecutive instructions with data dependency take a minimum of 1 clk cycle [Operation Forwarding used] - - All remaining instructions take a minimum of 1 clk cycle + - Taken branch and jump instructions take a minimum of 6 clk cycles **[No Branch Prediction Used]** + - Two **consecutive** instructions with data dependency take a minimum of 2 clk cycles. Nonconsecutive instructions with data dependency take a minimum of 1 clk cycle **[Operation Forwarding used]** + - **All remaining instructions take a minimum of 1 clk cycle** ## Supported Features of Zicsr Extension Module - **CSR instructions**: `CSRRW`, `CSRRS`, `CSRRC`, `CSRRWI`, `CSRRSI`, `CSRRCI` @@ -50,8 +50,7 @@ The RISCV toolchain `riscv64-unknown-elf-` and Modelsim executables `vsim` and ` Below is the expected output after running `$ ./test.sh`: -![script_updated](https://user-images.githubusercontent.com/87559347/175277402-d0fbb6ba-53c4-4457-8730-0ce0b3c58a43.png) - +![script_updated](https://user-images.githubusercontent.com/87559347/175321267-a22a95d9-5ed2-448f-aa32-1e9f5e56f579.png) ## Goal Checklist :white_check_mark: Add more testcases for the testbench