diff --git a/arm/am64xr5/README b/arm/am64xr5/README new file mode 100644 index 00000000..fccafecd --- /dev/null +++ b/arm/am64xr5/README @@ -0,0 +1,274 @@ +TI AM64x/AM263x Arm Cortex-R5 Runtime +===================================== + +Runtimes Supported +------------------ + +* Light-Tasking + +Targets Supported +----------------- + +* TI AM64x/AM263x Arm Cortex-R5F Subsystem (R5FSS) + - The runtime can run on any R5FSS CPU without modification. + - Symmetric multiprocessing (SMP) is not supported. + - Separate applications can be run on different CPUs. + +Using the runtimes +------------------ + +As a prerequisite, GNAT Pro for ARM ELF needs to be installed. To then use the +runtime copy it to the `/arm-eabi/lib/gnat/` folder. +You can then select the runtime in GNAT Studio from the Toolchain pane of the +Project Properties dialog box or set the following in your GPR file: + + for Runtime ("ada") use "light-tasking-am64xr5"; + +Alternatively, you can locate the runtime in another directory and then in the +project file provide the full or relative path from the project file: + + for Runtime ("ada") use "/path/to/runtime/light-tasking-am64xr5"; + +Rebuilding the Runtime +---------------------- + +If you need to make changes to the runtime's BSP you can rebuild it as follows: + +For the Light-Tasking runtime: gprbuild -P ravenscar_build.gpr + +Note: if you were provided the runtime in a certification context, please reach +out to AdaCore before modifying the runtime. + +Resources used by the runtime +----------------------------- + +- The Global Timebase Counter as the source for Ada.Real_Time.Clock; +- Timers 0 and 1 as the alarm source for R5FSS0 CPU 0 and 1 respectively; +- Timers 2 and 3 as the alarm source for R5FSS1 CPU 0 and 1 respectively; +- The local Vectored Interrupt Manager (VIM) controller for interrupt support; +- UART0 for Ada.Text_IO. + +Interrupt sources TIMER0_INTR_PEND_0, TIMER1_INTR_PEND_0, TIMER2_INTR_PEND_0, +TIMER3_INTR_PEND_0 are reserved for runtime use and should not be used by user +applications. + +See the respective sections below for further details on each resource used by +the GNAT runtime. + +System Clocks +------------- + +The AM64x/AM263x R5FSS runtime uses two clock sources: + +* Global Timebase Counter (GTC): high resolution counter used for + Ada.Real_Time.Clock. +* Timers: used for delays and timing events. + +The GTC is a read-only monotonic clock shared among all CPUs. The runtime will +enable the GTC if it's not enabled. User software should not disable the GTC nor +modify the GTC after the runtime starts, instead configuration of the GTC +should be performed by the SBL. The GTC clock frequency is defined in the +runtime package System.BB.Board_Parameters (`s-bbbopa.ads`) in the gnat +directory by the constant GTC_Frequency. By default, the GTC_Frequency is +defined as 225 MHz and can be updated by users by modifying this value and +rebuilding the runtime. + +Timers 0 and 1 are used as the alarm source when the runtime is run on R5FSS0 +CPU 0 and CPU 1 respectively, while Timers 2 and 3 are used as the alarm source +for R5FSS1 CPU 0 and CPU 1. The runtime will determine the appropriate Timer +to use at runtime, no configuration is necessary. The runtime configures each +Timer to use HFOSC0_CLKOUT as its clock input source. The frequency of +HFOSC0_CLKOUT is defined in System.BB.Board_Parameters as 25 MHz and can be +changed by users to suit their board if required. + +Startup Code +------------ + +The TI AM64x/AM263x R5FSS runtime provides low-level startup code in `crt0.S` +that contains the entry point of the application to be called from your +bootloader and performs the low-level runtime initialization required before +high-level Ada code is called. The startup code performs the following +operations: + + * initialization of core registers; + * Enabling of the FPU; + * Clearing the BSS section; + * Loading of the DATA section to RAM if required; + * Configuration of the MPU. + +Outside of the startup code, the runtime will also configure the CPU's +respective Timer and local VIM. All other SoC initialization and configuration +needs to be carried out by the Secondary Bootloader (SBL) prior to passing +control over to the application. The SBL is also required to load the +application into memory if required. Any peripherals the application may use +should be configured by the SBL or the application directly prior to their use. + +The configuration of the MPU is located in System.Board_Parameters +(`s-boapar`). This package can be modified directly by non-certification users +to suit your needs. For certification users who cannot modify the runtime you +should configure the MPU directly yourself by implementing your own version of +the parameterless function `__gnat_mpu_init` in your application. At link time +your application will use your version of `__gnat_mpu_init` instead of the +runtime provided version. + +In limited circumstances, `crt0.S` may be replaced with your own code that +performs the above requirement and directly calls `main`, but please contact +AdaCore if you need to modify the FPU settings as doing so may affect the +conformance of the runtime to the Ada Standard. + +Memory +------ + +The application memory is broken down into three primary memory regions: + + * Boot and Vector Code ("Boot Region") + * Code, read-only data and the initial read-write data ("Code Region") + * Data and bss (zeroed data) sections ("Data Region") + +A set of default linker scripts are provided with the runtime that locate +the Boot Region at the start of TCM A and the Code and Data regions into MSRAM. +These linker scripts can be found in the `ld` directory and consist of the +following scripts: + + * `memmap.ld`: defines the layout of the AM64x/AM263x memory. + * `ram.ld`: maps AM64x/AM263x memory to the memory regions defined above. This + is the main linker script that includes the other two scripts. + * `common.ld`: defines the application entry point and sections. It uses the + memory regions defined in `ram.ld` to allow this script to be used in + different scenarios without modification. + +While you can modify these scripts directly, it's recommended to copy the +scripts you need to modify to your project folder and modify them there. This +allows you to preserve your scripts between runtime updates and is required if +you will be using the runtime to run applications on different cores (as each +application will need to be mapped to different memory locations). + +To use your own linker scripts, specify the main linker script via the `-T` +linker switch and use the `-XLOADER=USER` switch when building your application +with GPRbuild. + +When relocating the primary memory regions, please keep in mind the following +guidance for each region. + +Boot Region +~~~~~~~~~~~~ + +The Boot Region contains the exception vector table, start code and hardware +exception handlers. The exception vector table appears at the start of this +region and consequently the region needs to be mapped to 0x00000000 if the +R5FSS core is booted from TCM. The AM64x/AM263x also supports remapping the +boot vector elsewhere in the SoC memory map by programming the +CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_LO and CTRLMMR_SEC_CLSTR0_CORE0_BOOTVECT_HI +registers. In this scenario, the Boot Region should be placed at the start of +this boot vector address. + +This region needs to be loaded into memory by the SBL. + +Code Region +~~~~~~~~~~~ + +The Code Region contains the application code, read-only data and the initial +state of the data section. This region can be located in RAM or read-only +memory like FLASH. If located in RAM it is the bootloader's responsibility to +load the Code Region to memory. + +Data Region +~~~~~~~~~~~ + +The Data Region contains the data and bss sections. The region needs to be +located in RAM, which can either be the SoC's internal TCM or SRAM, or external +DDR memory. During runtime startup the runtime will zero the bss section and +copy the initial state of the data section from the Code Region if the two +regions are not located together. There is no need for the SBL to load the +Data Region into RAM. + +Caches +~~~~~~ + +The runtime enables the data and instruction cache during initialization. + +Interrupts +---------- + +External Interrupts +~~~~~~~~~~~~~~~~~~~ + +The AM64x/AM263x R5FSS runtime supports connecting IRQ interrupts generated by +the CPU's Vectored Interrupt Manager (VIM) to protected procedure handlers as +documented in the Ada Reference Manual C.3.1. The list of interrupt names can +be found in the package Ada.Interrupts.Names (`gnarl/a-intnam.ads`). + +Due to the design of the VIM, all interrupts are mapped to a single Ada +Interrupt Priority and nested priorities are not supported. Interrupts handled +by the runtime use a dedicated stack and the FPU is enabled, allowing the +use of floating-point instructions within an interrupt handler. The runtime +will initialize the CPU's VIM during runtime initialization and the VIM is +configured to use the vector interface (VIC). + +Additional interrupt functionality is provided through the GNAT.Interrupts +(`gnarl/g-interr.ads`) package: + + * Enabling and disabling interrupts at the VIM; + * Raising a software interrupt (for testing); + * Setting the type of interrupt event (level (default) or pulse); + * Setting the priority of the interrupt at the VIM. + +Note that since the runtime does not support nested priorities, the VIM +interrupt priorities are only used to determine which interrupt has precedence +to be serviced when there are multiple pending interrupts. + +Additionally, GNAT.Interrupts supports direct attachment of IRQ and FIQ +interrupt handlers to the VIM that bypasses the GNAT runtime. This allows users +to provide low latency handlers. Direct attachment of handlers comes with the +following limitations: + + * Nesting of interrupts is not supported; + * Interrupts must not be reenabled while in a handler; + * Handler *must* not make any runtime calls, including calling protected + subprograms; + * Handler should not use the FPU; + * Users are responsible for saving and restoring register state, and + returning from the interrupt. This can be done by using the "interrupt" + machine attribute on the handler procedure; + * Users must follow TI's documentation on "Servicing IRQ Through Vector + Interface" for IRQ handlers and "Servicing FIQ" for FIQ handlers. + Use the provided procedures Clear_VIM_Status and Clear_Priority_Mask to + clear the interrupt status and VIM priority. + +Cortex R5 Core Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~ + +Undefined instruction exceptions, prefetch abort and data abort exceptions +will call the GNAT Last Chance Handler with a message indicating which +exception was raised. By default, the Last Chance Handler will print out this +exception message and loop. It is expected that the default Last Chance Handler +is replaced with your application specific Last Chance Handler. + +Power Management +---------------- + +The runtime will place the CPU into standby mode if there are no tasks eligible +to run. + +Text_IO +------- + +The runtime provides a minimal version of the Ada.Text_IO package supporting +character- and string-based input and output routines for basic I/O needs. It +is recommended to implement your own I/O packages based around your I/O +channel of choice. + +The bodies of the Ada.Text_IO routines call through to a device-specific I/O +package named System.Text_IO. See the package body in the file `s-textio.adb` +in the gnat directory for more details. + +System.Text_IO on the AM64x/AM263x R5FSS runtime is configured by default to +use UART0. UART0 is configured for 115200 baud rate, one stop bit, no parity +using the 48 MHz clock source. + +Note: System.Text_IO does not provide any synchronised access to UART0 across +R5FSS and A53SS CPUs. If you deploy multiple applications using the runtime, +ensure only one application uses Ada.Text_IO. If your other applications +require Text_IO services, have these applications interface directly with +different I/O peripherals, or use the AM64x/AM243x IPC facilities to relay +messages through the application designated to communicate with UART0. diff --git a/arm/am64xr5/common.ld b/arm/am64xr5/common.ld new file mode 100644 index 00000000..b67df557 --- /dev/null +++ b/arm/am64xr5/common.ld @@ -0,0 +1,237 @@ +/**************************************************************************** + * * + * GNAT COMPILER COMPONENTS * + * * + * A R M * + * * + * Linker Script File * + * * + * Copyright (C) 1999-2002 Universidad Politecnica de Madrid * + * Copyright (C) 2003-2006 The European Space Agency * + * Copyright (C) 2003-2017 AdaCore * + * * + * GNAT is free software; you can redistribute it and/or modify it under * + * terms of the GNU General Public License as published by the Free Soft- * + * ware Foundation; either version 2, or (at your option) any later ver- * + * sion. GNAT is distributed in the hope that it will be useful, but WITH- * + * OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * + * for more details. You should have received a copy of the GNU General * + * Public License distributed with GNAT; see file COPYING. If not, write * + * to the Free Software Foundation, 51 Franklin Street, Fifth Floor, * + * Boston, MA 02110-1301, USA. * + * * + * As a special exception, if you link this file with other files to * + * produce an executable, this file does not by itself cause the resulting * + * executable to be covered by the GNU General Public License. This except- * + * ion does not however invalidate any other reasons why the executable * + * file might be covered by the GNU Public License. * + * * + * GNARL was developed by the GNARL team at Florida State University. * + * Extensive contributions were provided by Ada Core Technologies, Inc. * + * The executive was developed by the Real-Time Systems Group at the * + * Technical University of Madrid. * + * * + ****************************************************************************/ + +/* This is a ARM specific version of this file */ + +/* This script replaces ld's default linker script, providing the + appropriate memory map and output format. */ + +/* Stack sizes */ +_DEFAULT_STACK_SIZE = (20 * 1024); + +_UNDEF_STACK_SIZE = 256; +_ABORT_STACK_SIZE = 256; +_IRQ_STACK_SIZE = 1024; +_FIQ_STACK_SIZE = 256; + +ENTRY(_start); + +/* + * The memory map looks like this: + * +--------------------------------+ <- low memory + * | .traps | + * +--------------------------------+ + * | .text | + * | | + * +--------------------------------+ + * | .data | initialized data goes here + * | | + * +--------------------------------+ + * | .bss | + * | __bss_start | start of bss, cleared by crt0 + * | uninitialized data | + * | __bss_end | + * | | + * | __interrupt_stack_start | + * | interrupt stack space | + * | __interrupt_stack_end | + * | | + * | __stack_start | + * | stack space | + * | __stack_end | top of stack + * | _end | start of heap, used by sbrk() + * +--------------------------------+ + * | heap space | + * | | + * +--------------------------------+ + * | remote monitor | + * +--------------------------------+ <- high memory + */ + +SECTIONS +{ + .vectors : + { + KEEP (*(.traps)) + *(.boot) + /* The trap handlers are placed here to keep them close to the vector + table. This allows us to use relative jumps from the vector table to + the handler instead of a trampoline in cases where the code region is + located far away from the boot region. + */ + *(.text.__gnat_undef_trap .text.__gnat_dabt_trap) + *(.text.__gnat_irq_trap .text.__gnat_fiq_trap) + } > REGION_BOOT + + .text : + { + *(.text .text.* .gnu.linkonce.t*) + } > REGION_CODE + + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) } > REGION_CODE + /* .ARM.exidx is 4-bytes aligned, so __exidx_start needs to be + aligned too. Note that assigning the location counter also makes + ld attach the following symbols to the next section (instead of the + previous section which is the default), so will properly + consider the location counter of .ARM.exidx for __exidx_start and + __exidx_end and not the previous section's one. */ + . = ALIGN(0x4); + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : { *(.ARM.exidx* .gnu.linkonce.armexidx.*) } > REGION_CODE + PROVIDE_HIDDEN (__exidx_end = .); + + .rodata : + { + *(.rodata .rodata.* .gnu.linkonce.r*) + . = ALIGN(0x8); + } > REGION_CODE + + /* relocated at runtime in case REGION_DATA /= REGION_CODE */ + .data : AT (ALIGN (ADDR (.rodata) + SIZEOF(.rodata), ALIGNOF (.data))) + { + __data_load = LOADADDR(.data); + __data_start = .; + *(.data .data.* .gnu.linkonce.d*) + . = ALIGN(0x4); + __data_end = .; + } > REGION_DATA + __data_words = (__data_end - __data_start) >> 2; + + .bss (NOLOAD): + { + . = ALIGN(0x8); + __bss_start = .; + + *(.bss .bss.*) + *(COMMON) + + /* Align the stack to 64 bits */ + + . = ALIGN(0x8); + __bss_end = .; + + __interrupt_stack_start = .; + + __abort_stack_start = .; + . = ALIGN(__abort_stack_start + _ABORT_STACK_SIZE, 0x8); + __abort_stack_end = .; + + __undef_stack_start = .; + . = ALIGN(__undef_stack_start + _UNDEF_STACK_SIZE, 0x8); + __undef_stack_end = .; + + __fiq_stack_start = .; + . = ALIGN(__fiq_stack_start + _FIQ_STACK_SIZE, 0x8); + __fiq_stack_end = .; + + /* Use the largest of .interrupt_stacks or the default trap stack sizes. + This allows use with the Light, Light-Tasking or Embedded run times. */ + + __irq_stack_start = .; + *(.interrupt_stacks) + . = MAX(., __irq_stack_start + _IRQ_STACK_SIZE); + . = ALIGN(0x8); + __irq_stack_end = .; + + __interrupt_stack_end = .; + + __stack_start = .; + + /* Reserve the space for the stack to be used by the environment task */ + + . += DEFINED (__stack_size) ? __stack_size : _DEFAULT_STACK_SIZE; + + /* Pointer to the top of the stack to be used by the main procedure (the + environment task. */ + + . = ALIGN(0x8); + __stack_end = .; + + _end = .; + __heap_start = .; + __heap_end = ORIGIN(REGION_DATA) + LENGTH(REGION_DATA); + } > REGION_DATA + + __bss_words = (__bss_end - __bss_start) >> 2; + + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + + /* DWARF 1. */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions. */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2. */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + + /* DWARF 2. */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line .debug_line.* .debug_line_end) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* SGI/MIPS DWARF 2 extensions. */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /* DWARF 3. */ + .debug_pubtypes 0 : { *(.debug_pubtypes) } + .debug_ranges 0 : { *(.debug_ranges) } + + /* DWARF 5. */ + .debug_addr 0 : { *(.debug_addr) } + .debug_line_str 0 : { *(.debug_line_str) } + .debug_loclists 0 : { *(.debug_loclists) } + .debug_macro 0 : { *(.debug_macro) } + .debug_names 0 : { *(.debug_names) } + .debug_rnglists 0 : { *(.debug_rnglists) } + .debug_str_offsets 0 : { *(.debug_str_offsets) } + .debug_sup 0 : { *(.debug_sup) } + + .gnu.attributes 0 : { KEEP (*(.gnu.attributes)) } + /DISCARD/ : { *(.note.GNU-stack) *(.gnu_debuglink) *(.gnu.lto_*) } +} diff --git a/arm/am64xr5/crt0.S b/arm/am64xr5/crt0.S new file mode 100644 index 00000000..a4396373 --- /dev/null +++ b/arm/am64xr5/crt0.S @@ -0,0 +1,294 @@ +/**************************************************************************** + * * + * GNU ADA RUN-TIME LIBRARY (GNARL) COMPONENTS * + * * + * C R T 0 * + * * + * Assembly File * + * * + * Copyright (C) 2011-2019 AdaCore * + * * + * GNAT is free software; you can redistribute it and/or modify it under * + * terms of the GNU General Public License as published by the Free Soft- * + * ware Foundation; either version 2, or (at your option) any later ver- * + * sion. GNAT is distributed in the hope that it will be useful, but WITH- * + * OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY * + * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License * + * for more details. You should have received a copy of the GNU General * + * Public License distributed with GNAT; see file COPYING. If not, write * + * to the Free Software Foundation, 59 Temple Place - Suite 330, Boston, * + * MA 02111-1307, USA. * + * * + * As a special exception, if you link this file with other files to * + * produce an executable, this file does not by itself cause the resulting * + * executable to be covered by the GNU General Public License. This except- * + * ion does not however invalidate any other reasons why the executable * + * file might be covered by the GNU Public License. * + * * + ****************************************************************************/ + +/* This file is specific to the TI AM64x and AM263x ARM Cortex-R5 cores. */ + +/* This file contains the trap table and start up code for the multitasking + executive implemented for bareboard targets. */ + +/* Startup code */ + + .section .traps + + .weak __gnat_undef_trap /* Undefined instruction trap */ + .weak __gnat_svc_trap /* Supervisor call trap */ + .weak __gnat_pabt_trap /* prefetch abort trap */ + .weak __gnat_dabt_trap /* data abort trap */ + .weak __gnat_irq_trap /* IRQ trap */ + .weak __gnat_fiq_trap /* FIQ trap */ + + /* The following provide default definitions for trap vectors that + loop back to the trap address, so the system will stop in a safe + state. The Ravenscar runtimes now can install their handlers by simply + exporting the relevant symbols. */ + + b _start +__gnat_undef_trap: + b __gnat_undef_trap +__gnat_svc_trap: + b __gnat_svc_trap +__gnat_pabt_trap: + b __gnat_pabt_trap +__gnat_dabt_trap: + b __gnat_dabt_trap + nop /* 14 : unused on the R5*/ +__gnat_irq_trap: + b __gnat_irq_trap +__gnat_fiq_trap: + b __gnat_fiq_trap + +.section .boot,"axS" + + /********************************************************************* + * _start: * + * * + * main entry point. * + *********************************************************************/ + .globl _start + .type _start, %function +_start: + /*********************************************/ + /* 1. Init registers, stacks and FPU */ + /*********************************************/ + + /* Start initializing CPU registers, including banked registers, for + all modes. */ + + /* init all base registers */ + mov r0, #0 + mov r1, #0 + mov r2, #0 + mov r3, #0 + mov r4, #0 + mov r5, #0 + mov r6, #0 + mov r7, #0 + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + + /* Switch to FIQ mode (M = 10001) */ + cps #17 + /* r8-r12,lr are banked */ + mov r8, #0 + mov r9, #0 + mov r10, #0 + mov r11, #0 + mov r12, #0 + mov lr, #0 + /* stack, spsr init */ + ldr sp, fiqSp + mrs r1, CPSR + msr SPSR_fsxc, r1 + + /* IRQ mode (M = 10010) */ + cps #18 + /* LR is banked */ + mov lr, #0 + /* stack, spsr init */ + ldr sp, irqSp + mrs r1, CPSR + msr SPSR_fsxc, r1 + + /* SVC mode (M = 10011) */ + cps #19 + /* LR is banked */ + mov lr, #0 + /* stack */ + ldr sp, irqSp /* The IRQ handler switches to SVC to handle IRQs */ + mrs r1, CPSR + msr SPSR_fsxc, r1 + + /* Abort mode (M = 10111) */ + cps #23 + /* LR is banked */ + mov lr, #0 + /* stack, spsr init */ + ldr sp, abortSp + mrs r1, CPSR + msr SPSR_fsxc, r1 + + /* Undefined instruction mode (M = 11011) */ + cps #27 + /* LR is banked */ + mov lr, #0 + /* stack, spsr init */ + ldr sp, undefSp + mrs r1, CPSR + msr SPSR_fsxc, r1 + + /* System mode (M = 11111) */ + cps #31 + /* LR is banked */ + mov lr, #0 + /* stack, spsr init */ + ldr sp, userSp /* SYS mode shared stack with User mode */ + mrs r1, CPSR + msr SPSR_fsxc, r1 + + /* Stay in system mode. */ + + /* Enable FPU on the CPACR/FPEXC registers */ + mrc p15, #0, r2, c1, c0, #2 /* CPACR */ + orr r2, r2, #0xF00000 /* Enable CP10, CP11 user & system */ + mcr p15, #0, r2, c1, c0, #2 /* set */ + isb + vmrs r2, fpexc + orr r2, r2, #0x40000000 /* Set the FPEXC.EN bit */ + vmsr fpexc, r2 + + mov r1, #0 + vmov d0, r1, r1 + vmov d1, r1, r1 + vmov d2, r1, r1 + vmov d3, r1, r1 + vmov d4, r1, r1 + vmov d5, r1, r1 + vmov d6, r1, r1 + vmov d7, r1, r1 + vmov d8, r1, r1 + vmov d9, r1, r1 + vmov d10, r1, r1 + vmov d11, r1, r1 + vmov d12, r1, r1 + vmov d13, r1, r1 + vmov d14, r1, r1 + vmov d15, r1, r1 + + /* Disable MPU and caches */ + mrc p15, 0, r2, c1, c0, 0 /* CP15 CTRL register */ + bic r2, r2, #5 /* Disable MPU and D cache */ + bic r2, r2, #0x1000 /* Disable I cache */ + dsb /* Ensure loads/stores are completed */ + mcr p15, 0, r2, c1, c0, 0 + isb /* insns must execute with the new + MPU settings */ + + /* Disable branch prediction, TCM ECC checks */ + mrc p15, 0, r2, c1, c0, 1 /* ACTLR */ + orr r2, r2, #(0x1 << 17) /* Enable RSDIS bit 17 to disable the return stack */ + orr r2, r2, #(0x1 << 16) /* Clear BP bit 15 and set BP bit 16:*/ + bic r2, r2, #(0x1 << 15) /* Branch always not taken and history table updates disabled*/ + orr r2, r2, #(0x1 << 27) /* Enable B1TCM ECC check */ + orr r2, r2, #(0x1 << 26) /* Enable B0TCM ECC check */ + orr r2, r2, #(0x1 << 25) /* Enable ATCM ECC check */ + bic r2, r2, #(0x1 << 5) /* Generate abort on parity errors, with [5:3]=b 000*/ + bic r2, r2, #(0x1 << 4) + bic r2, r2, #(0x1 << 3) + mcr p15, 0, r2, c1, c0, 1 + dsb + + /* Invalidate caches */ + mov r0,#0 /* r0 = 0 */ + dsb + mcr p15, 0, r0, c7, c5, 0 /* invalidate icache */ + mcr p15, 0, r0, c15, c5, 0 /* Invalidate entire data cache*/ + isb + + /*********************************************/ + /* 2. MPU initialization */ + /*********************************************/ + + /* See s-mpu* and s-boapar.ads */ + bl __gnat_mpu_init + + /* Enable branch prediction */ + mrc p15, 0, r0, c1, c0, 1 /* Read ACTLR*/ + bic r0, r0, #(0x1 << 17) /* Clear RSDIS bit 17 to enable return stack*/ + bic r0, r0, #(0x1 << 16) /* Clear BP bit 15 and BP bit 16:*/ + bic r0, r0, #(0x1 << 15) /* Normal operation, BP is taken from the global history table.*/ + orr r0, r0, #(0x1 << 14) /* Disable DBWR for errata 780125 */ + mcr p15, 0, r0, c1, c0, 1 /* Write ACTLR*/ + + /* Enable d-cache and i-cache */ + mrc p15,0,r1,c1,c0,0 + ldr r0, =0x1005 + orr r1,r1,r0 + dsb + mcr p15,0,r1,c1,c0,0 /* Enable cache */ + isb /* isb flush prefetch buffer */ + + /* enable asynchronous abort exception */ + mrs r0, cpsr + bic r0, r0, #0x100 + msr cpsr_xsf, r0 + + /*********************************************/ + /* 3. Memory sections init */ + /*********************************************/ + + /* Clear .bss */ + movw r0, #:lower16:__bss_start + movt r0, #:upper16:__bss_start + movw r1, #:lower16:__bss_words + movt r1, #:upper16:__bss_words + movw r2, #0 + cmp r1,#0 + beq 1f +0: str r2,[r0],#4 + subs r1,r1,#1 + bne 0b +1: + + /* Copy .data */ + movw r0,#:lower16:__data_start + movt r0,#:upper16:__data_start + movw r2,#:lower16:__data_load + movt r2,#:upper16:__data_load + cmp r0, r2 + beq 1f /* start == load: Skip data copy */ + + movw r1,#:lower16:__data_words + movt r1,#:upper16:__data_words + cmp r1,#0 + beq 1f +0: ldr r4,[r2],#4 + str r4,[r0],#4 + subs r1,r1,#1 + bne 0b +1: + + /*********************************************/ + /* 4. Run application */ + /*********************************************/ + + /* Call the main routine */ + bl main + + /* reboot the board if main would return */ + bl _exit + +abortSp: .word __abort_stack_end +undefSp: .word __undef_stack_end +fiqSp: .word __fiq_stack_end +irqSp: .word __irq_stack_end +userSp: .word __stack_end + .size _start, . - _start diff --git a/arm/am64xr5/memmap.ld b/arm/am64xr5/memmap.ld new file mode 100644 index 00000000..a02dbbc1 --- /dev/null +++ b/arm/am64xr5/memmap.ld @@ -0,0 +1,34 @@ +MEMORY +{ + /* TCM is configured for dual core mode (each core has 64KB of TCM) */ + + R5F_TCMA : ORIGIN = 0x00000000, LENGTH = 32K + R5F_TCMB : ORIGIN = 0x41010000, LENGTH = 32K + + /* MSRAM is divided on 8 banks of 256KB each. The banks are separated below + to allow easy assignment of banks to applications running on different + cores. Several banks can be assigned to single application by merging + the required banks below into a single region if required. */ + + MSRAM_256K0 : ORIGIN = 0x70000000, LENGTH = 256K + MSRAM_256K1 : ORIGIN = 0x70040000, LENGTH = 256K + MSRAM_256K2 : ORIGIN = 0x70080000, LENGTH = 256K + MSRAM_256K3 : ORIGIN = 0x700C0000, LENGTH = 256K + MSRAM_256K4 : ORIGIN = 0x70100000, LENGTH = 256K + MSRAM_256K5 : ORIGIN = 0x70140000, LENGTH = 256K + MSRAM_256K6 : ORIGIN = 0x70180000, LENGTH = 256K + MSRAM_256K7 : ORIGIN = 0x701C0000, LENGTH = 256K + + /* FLASH Memory. Ensure it does not overlap with other CPUs if you're + planning to place executable code and other CPU specific data in this + region. */ + + FLASH : ORIGIN = 0x60100000, LENGTH = 512K + + /* DDR Memory. Ensure it does not overlap with other CPUs if you're + planning to place executable code and other CPU specific data in this + region. */ + + DDR_RAM : ORIGIN = 0x80000000, LENGTH = 2048M + +} diff --git a/arm/am64xr5/ram.ld b/arm/am64xr5/ram.ld new file mode 100644 index 00000000..8bac3be7 --- /dev/null +++ b/arm/am64xr5/ram.ld @@ -0,0 +1,7 @@ +INCLUDE memmap.ld + +REGION_ALIAS("REGION_BOOT", R5F_TCMA) +REGION_ALIAS("REGION_CODE", MSRAM_256K2) +REGION_ALIAS("REGION_DATA", MSRAM_256K2) + +INCLUDE common.ld diff --git a/arm/cortexar.py b/arm/cortexar.py index 6b209374..657c7b37 100644 --- a/arm/cortexar.py +++ b/arm/cortexar.py @@ -50,6 +50,65 @@ def amend_rts(self, rts_profile, conf): conf.build_flags['common_gnarl_flags'] += ['-mgeneral-regs-only'] +class AM64xR5(CortexARTarget): + @property + def name(self): + return 'am64xr5' + + @property + def has_small_memory(self): + return True + + @property + def loaders(self): + return ('RAM',) + + @property + def cpu(self): + return 'cortex-r5' + + @property + def compiler_switches(self): + # The required compiler switches + return ('-mlittle-endian', '-mfloat-abi=hard', + '-mcpu=%s' % self.cpu, '-mfpu=vfpv3-d16', '-marm') + + @property + def readme_file(self): + return 'arm/am64xr5/README' + + @property + def system_ads(self): + return {'light-tasking': 'system-xi-arm-light-tasking-no-irq-nesting.ads'} + + def add_linker_scripts(self): + self.add_linker_script('arm/am64xr5/common.ld') + self.add_linker_script('arm/am64xr5/memmap.ld') + self.add_linker_script('arm/am64xr5/ram.ld', loader='RAM') + + def __init__(self): + super(AM64xR5, self).__init__() + + self.add_linker_scripts() + + self.add_gnat_sources( + 'arm/am64xr5/crt0.S', + 'arm/src/s-mpudef.ads', + 'arm/src/s-mpuini.ads', 'arm/src/s-mpuini.adb', + 'src/s-boapar__am64xr5.ads', + 'src/s-macres__none.adb', + 'src/s-textio__16C750.adb') + + self.add_gnarl_sources( + 'src/a-intnam__am64xr5.ads', + 'src/g-interr__ti_vim.ads', 'src/g-interr__ti_vim.adb', + 'src/s-bbpara__am64xr5.ads', 'src/s-bbbosu__am64xr5.adb', + 'src/s-bbsumu__generic.adb', + 'src/s-bbcppr__arm.adb', + 'src/s-ti.ads', + 'src/s-tvinma.ads', 'src/s-tvinma.adb') + + class Rpi2Base(CortexARTarget): @property def loaders(self): @@ -265,8 +324,8 @@ def __init__(self): self.add_gnat_sources( 'arm/zynqmpr5/crt0.S', - 'arm/zynqmpr5/s-mpudef.ads', - 'arm/zynqmpr5/s-mpuini.ads', 'arm/zynqmpr5/s-mpuini.adb', + 'arm/src/s-mpudef.ads', + 'arm/src/s-mpuini.ads', 'arm/src/s-mpuini.adb', 'src/s-boapar__zynqmpr5.ads') self.add_gnat_sources( 'src/s-textio__zynqmp.adb', diff --git a/arm/zynqmpr5/s-mpudef.ads b/arm/src/s-mpudef.ads similarity index 91% rename from arm/zynqmpr5/s-mpudef.ads rename to arm/src/s-mpudef.ads index e75354fe..d1c00774 100644 --- a/arm/zynqmpr5/s-mpudef.ads +++ b/arm/src/s-mpudef.ads @@ -124,12 +124,12 @@ package System.MPU_Definitions is Privileged_RO_User_RO) with Size => 3; for Access_Control_AP use - (Privileged_NA_User_NA => 2#000#, - Privileged_RW_User_NA => 2#001#, - Privileged_RW_User_RO => 2#010#, + (Privileged_NA_User_NA => 2#000#, + Privileged_RW_User_NA => 2#001#, + Privileged_RW_User_RO => 2#010#, Privileged_RW_User_RW => 2#011#, - Privileged_RO_User_NA => 2#101#, - Privileged_RO_User_RO => 2#110#); + Privileged_RO_User_NA => 2#101#, + Privileged_RO_User_RO => 2#110#); -- TEX S C B bits: @@ -164,21 +164,28 @@ package System.MPU_Definitions is type Unsigned_19 is mod 2 ** 19 with Size => 19; type Size_And_Enable_Reg is record - Reserved_1 : I.Unsigned_16 := 0; Sub_Region_Disable : I.Unsigned_8 := 0; - Reserved_2 : Unsigned_2 := 0; Size : Region_Size; Enable : Boolean; - end record with Pack, Size => 32; + end record with Size => 32; + + for Size_And_Enable_Reg use record + Sub_Region_Disable at 0 range 8 .. 15; + Size at 0 range 1 .. 5; + Enable at 0 range 0 .. 0; + end record; type Access_Control_Reg is record - Reserved_1 : Unsigned_19 := 0; XN : Access_Control_XN; - Reserved_2 : Unsigned_1 := 0; AP : Access_Control_AP; - Reserved_3 : Unsigned_2 := 0; TEX_S_C_B : Access_Control_TEX_S_C_B; - end record with Pack, Size => 32; + end record with Size => 32; + + for Access_Control_Reg use record + XN at 0 range 12 .. 12; + AP at 0 range 8 .. 10; + TEX_S_C_B at 0 range 0 .. 5; + end record; type MPU_Region_Configuration is record Base_Address : I.Unsigned_32; diff --git a/arm/zynqmpr5/s-mpuini.adb b/arm/src/s-mpuini.adb similarity index 93% rename from arm/zynqmpr5/s-mpuini.adb rename to arm/src/s-mpuini.adb index 0aaec3b3..c7c28cbf 100644 --- a/arm/zynqmpr5/s-mpuini.adb +++ b/arm/src/s-mpuini.adb @@ -25,7 +25,6 @@ -- -- ------------------------------------------------------------------------------ -with Ada.Unchecked_Conversion; with Interfaces; use Interfaces; with Interfaces.ARM_V7AR; use Interfaces.ARM_V7AR; with System.MPU_Definitions; use System.MPU_Definitions; @@ -63,17 +62,16 @@ package body System.MPU_Init is -- Disable the unused regions - for Index in MPU_Config'Last + 1 .. Num_Rgn loop + for Index in MPU_Config'Last + 1 .. Num_Rgn - 1 loop CP15.Set_MPU_Region_Number (Index); CP15.Set_MPU_Region_Base_Address (16#0000_0000#); CP15.Set_MPU_Region_Size_And_Enable (0); CP15.Set_MPU_Region_Access_Control (0); end loop; - -- Enable MPU with background region activated (respectively bits 0 and - -- 17 of SCTLR) + -- Enable MPU (bit 0 of SCTLR) SCTLR := CP15.Get_SCTLR; - SCTLR := SCTLR or 1 or (2 ** 17); + SCTLR := SCTLR or 1; Barriers.DSB; CP15.Set_SCTLR (SCTLR); Barriers.ISB; diff --git a/arm/zynqmpr5/s-mpuini.ads b/arm/src/s-mpuini.ads similarity index 100% rename from arm/zynqmpr5/s-mpuini.ads rename to arm/src/s-mpuini.ads diff --git a/build_rts.py b/build_rts.py index 5879df00..f32b7ddb 100755 --- a/build_rts.py +++ b/build_rts.py @@ -23,7 +23,7 @@ CortexM7F, CortexM7DF, CortexM23, CortexM33F, CortexM33DF # Cortex-A/R runtimes -from arm.cortexar import TMS570, Rpi2, Rpi2Mc, Zynq7000, ZynqmpR5 +from arm.cortexar import AM64xR5, TMS570, Rpi2, Rpi2Mc, Zynq7000, ZynqmpR5 # Aarch64 from aarch64 import Morello, Rpi3, Rpi3Mc, ZynqMP @@ -89,6 +89,8 @@ def build_configs(target): elif target == 'zynqmp': t = ZynqMP() # ARM elf + elif target == 'am64xr5': + t = AM64xR5() elif target == 'zynq7000': t = Zynq7000() elif target == 'zynqmpr5': diff --git a/src/a-intnam__am64xr5.ads b/src/a-intnam__am64xr5.ads new file mode 100644 index 00000000..b9059c34 --- /dev/null +++ b/src/a-intnam__am64xr5.ads @@ -0,0 +1,530 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS -- +-- -- +-- A D A . I N T E R R U P T S . N A M E S -- +-- -- +-- S p e c -- +-- -- +-- Copyright (C) 2012-2017, Free Software Foundation, Inc. -- +-- -- +-- GNAT is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +------------------------------------------------------------------------------ + +-- This is the TI AM64x/AM263x Arm Cortex-R5 version of this package + +pragma Restrictions (No_Elaboration_Code); + +package Ada.Interrupts.Names is + + -- All identifiers in this unit are implementation defined + + pragma Implementation_Defined; + + RTI8_INTR_WWD_0 : constant Interrupt_ID := 0; + -- R5FSS0 Core 0 + + RTI9_INTR_WWD_0 : constant Interrupt_ID := 0; + -- R5FSS0 Core 1 + + RTI10_INTR_WWD_0 : constant Interrupt_ID := 0; + -- R5FSS1 Core 0 + + RTI11_INTR_WWD_0 : constant Interrupt_ID := 0; + -- R5FSS1 Core 1 + + DMSC0_AES_0_HIB_PUBLIC_0 : constant Interrupt_ID := 1; + DMSC0_AES_0_HIB_SECURE_0 : constant Interrupt_ID := 2; + DMSC0_DBG_AUTH_0_DEBUG_AUTH_INTR_0 : constant Interrupt_ID := 3; + -- All cores + + R5FSS0_CORE_0_EXP_INTR_0 : constant Interrupt_ID := 4; + R5FSS0_COMMON0_COMMRX_LEVEL_0_0 : constant Interrupt_ID := 5; + R5FSS0_COMMON0_COMMTX_LEVEL_0_0 : constant Interrupt_ID := 6; + -- R5FSS0 Core 0 + + R5FSS0_CORE_1_EXP_INTR_0 : constant Interrupt_ID := 4; + R5FSS0_COMMON0_COMMRX_LEVEL_1_0 : constant Interrupt_ID := 5; + R5FSS0_COMMON0_COMMTX_LEVEL_1_0 : constant Interrupt_ID := 6; + -- R5FSS0 Core 1 + + R5FSS1_CORE_0_EXP_INTR_0 : constant Interrupt_ID := 4; + R5FSS1_COMMON0_COMMRX_LEVEL_0_0 : constant Interrupt_ID := 5; + R5FSS1_COMMON0_COMMTX_LEVEL_0_0 : constant Interrupt_ID := 6; + -- R5FSS1 Core 0 + + R5FSS1_CORE_1_EXP_INTR_0 : constant Interrupt_ID := 4; + R5FSS1_COMMON0_COMMRX_LEVEL_1_0 : constant Interrupt_ID := 5; + R5FSS1_COMMON0_COMMTX_LEVEL_1_0 : constant Interrupt_ID := 6; + -- R5FSS1 Core 1 + + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_72 : constant Interrupt_ID := 8; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_73 : constant Interrupt_ID := 9; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_74 : constant Interrupt_ID := 10; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_75 : constant Interrupt_ID := 11; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_76 : constant Interrupt_ID := 12; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_77 : constant Interrupt_ID := 13; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_78 : constant Interrupt_ID := 14; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_79 : constant Interrupt_ID := 15; + -- R5FSS0 Core 0 + + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_80 : constant Interrupt_ID := 8; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_81 : constant Interrupt_ID := 9; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_82 : constant Interrupt_ID := 10; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_83 : constant Interrupt_ID := 11; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_84 : constant Interrupt_ID := 12; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_85 : constant Interrupt_ID := 13; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_86 : constant Interrupt_ID := 14; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_87 : constant Interrupt_ID := 15; + -- R5FSS0 Core 1 + + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_120 : constant Interrupt_ID := 8; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_121 : constant Interrupt_ID := 9; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_122 : constant Interrupt_ID := 10; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_123 : constant Interrupt_ID := 11; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_124 : constant Interrupt_ID := 12; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_125 : constant Interrupt_ID := 13; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_126 : constant Interrupt_ID := 14; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_127 : constant Interrupt_ID := 15; + -- R5FSS1 Core 0 + + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_128 : constant Interrupt_ID := 8; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_129 : constant Interrupt_ID := 9; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_130 : constant Interrupt_ID := 10; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_131 : constant Interrupt_ID := 11; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_132 : constant Interrupt_ID := 12; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_133 : constant Interrupt_ID := 13; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_134 : constant Interrupt_ID := 14; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_135 : constant Interrupt_ID := 15; + -- R5FSS1 Core 1 + + FSIRX0_FSI_RX_OINT1_0 : constant Interrupt_ID := 16; + FSIRX0_FSI_RX_OINT2_0 : constant Interrupt_ID := 17; + FSIRX1_FSI_RX_OINT1_0 : constant Interrupt_ID := 18; + FSIRX1_FSI_RX_OINT2_0 : constant Interrupt_ID := 19; + FSIRX2_FSI_RX_OINT1_0 : constant Interrupt_ID := 20; + FSIRX2_FSI_RX_OINT2_0 : constant Interrupt_ID := 21; + FSIRX3_FSI_RX_OINT1_0 : constant Interrupt_ID := 22; + FSIRX3_FSI_RX_OINT2_0 : constant Interrupt_ID := 23; + FSIRX4_FSI_RX_OINT1_0 : constant Interrupt_ID := 24; + FSIRX4_FSI_RX_OINT2_0 : constant Interrupt_ID := 25; + FSIRX5_FSI_RX_OINT1_0 : constant Interrupt_ID := 26; + FSIRX5_FSI_RX_OINT2_0 : constant Interrupt_ID := 27; + FSITX0_FSI_TX_OINT1_0 : constant Interrupt_ID := 28; + FSITX0_FSI_TX_OINT2_0 : constant Interrupt_ID := 29; + FSITX1_FSI_TX_OINT1_0 : constant Interrupt_ID := 30; + FSITX1_FSI_TX_OINT2_0 : constant Interrupt_ID := 31; + -- All cores + + MAIN_GPIOMUX_INTROUTER0_OUTP_0 : constant Interrupt_ID := 32; + MAIN_GPIOMUX_INTROUTER0_OUTP_1 : constant Interrupt_ID := 33; + MAIN_GPIOMUX_INTROUTER0_OUTP_2 : constant Interrupt_ID := 34; + MAIN_GPIOMUX_INTROUTER0_OUTP_3 : constant Interrupt_ID := 35; + MAIN_GPIOMUX_INTROUTER0_OUTP_4 : constant Interrupt_ID := 36; + MAIN_GPIOMUX_INTROUTER0_OUTP_5 : constant Interrupt_ID := 37; + MAIN_GPIOMUX_INTROUTER0_OUTP_6 : constant Interrupt_ID := 38; + MAIN_GPIOMUX_INTROUTER0_OUTP_7 : constant Interrupt_ID := 39; + MAIN_GPIOMUX_INTROUTER0_OUTP_8 : constant Interrupt_ID := 40; + MAIN_GPIOMUX_INTROUTER0_OUTP_9 : constant Interrupt_ID := 41; + MAIN_GPIOMUX_INTROUTER0_OUTP_10 : constant Interrupt_ID := 42; + MAIN_GPIOMUX_INTROUTER0_OUTP_11 : constant Interrupt_ID := 43; + MAIN_GPIOMUX_INTROUTER0_OUTP_12 : constant Interrupt_ID := 44; + MAIN_GPIOMUX_INTROUTER0_OUTP_13 : constant Interrupt_ID := 45; + MAIN_GPIOMUX_INTROUTER0_OUTP_14 : constant Interrupt_ID := 46; + MAIN_GPIOMUX_INTROUTER0_OUTP_15 : constant Interrupt_ID := 47; + -- All cores + + CMPEVENT_INTROUTER0_OUTP_16 : constant Interrupt_ID := 48; + CMPEVENT_INTROUTER0_OUTP_17 : constant Interrupt_ID := 49; + CMPEVENT_INTROUTER0_OUTP_18 : constant Interrupt_ID := 50; + CMPEVENT_INTROUTER0_OUTP_19 : constant Interrupt_ID := 51; + CMPEVENT_INTROUTER0_OUTP_20 : constant Interrupt_ID := 52; + CMPEVENT_INTROUTER0_OUTP_21 : constant Interrupt_ID := 53; + CMPEVENT_INTROUTER0_OUTP_22 : constant Interrupt_ID := 54; + CMPEVENT_INTROUTER0_OUTP_23 : constant Interrupt_ID := 55; + -- R5FSS0 Core 0 and Core 1 + + CMPEVENT_INTROUTER0_OUTP_24 : constant Interrupt_ID := 48; + CMPEVENT_INTROUTER0_OUTP_25 : constant Interrupt_ID := 49; + CMPEVENT_INTROUTER0_OUTP_26 : constant Interrupt_ID := 50; + CMPEVENT_INTROUTER0_OUTP_27 : constant Interrupt_ID := 51; + CMPEVENT_INTROUTER0_OUTP_28 : constant Interrupt_ID := 52; + CMPEVENT_INTROUTER0_OUTP_29 : constant Interrupt_ID := 53; + CMPEVENT_INTROUTER0_OUTP_30 : constant Interrupt_ID := 54; + CMPEVENT_INTROUTER0_OUTP_31 : constant Interrupt_ID := 55; + -- R5FSS1 Core 0 and Core 1 + + DMSC0_CORTEX_M3_0_SEC_OUT_0 : constant Interrupt_ID := 56; + DMSC0_CORTEX_M3_0_SEC_OUT_1 : constant Interrupt_ID := 57; + -- All cores + + R5FSS0_CORE0_PMU_0 : constant Interrupt_ID := 58; + R5FSS0_CORE0_VALFIQ_0 : constant Interrupt_ID := 59; + R5FSS0_CORE0_VALIRQ_0 : constant Interrupt_ID := 60; + -- R5FSS0 Core 0 + + R5FSS0_CORE1_PMU_0 : constant Interrupt_ID := 58; + R5FSS0_CORE1_VALFIQ_0 : constant Interrupt_ID := 59; + R5FSS0_CORE1_VALIRQ_0 : constant Interrupt_ID := 60; + -- R5FSS0 Core 1 + + R5FSS1_CORE0_PMU_0 : constant Interrupt_ID := 58; + R5FSS1_CORE0_VALFIQ_0 : constant Interrupt_ID := 59; + R5FSS1_CORE0_VALIRQ_0 : constant Interrupt_ID := 60; + -- R5FSS0 Core 0 + + R5FSS1_CORE1_PMU_0 : constant Interrupt_ID := 58; + R5FSS1_CORE1_VALFIQ_0 : constant Interrupt_ID := 59; + R5FSS1_CORE1_VALIRQ_0 : constant Interrupt_ID := 60; + -- R5FSS1 Core 1 + + MCU_I2C0_POINTRPEND_0 : constant Interrupt_ID := 61; + MCU_I2C1_POINTRPEND_0 : constant Interrupt_ID := 62; + MCSPI3_INTR_SPI_0 : constant Interrupt_ID := 63; + -- All Cores + + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_40 : constant Interrupt_ID := 64; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_41 : constant Interrupt_ID := 65; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_42 : constant Interrupt_ID := 66; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_43 : constant Interrupt_ID := 67; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_44 : constant Interrupt_ID := 68; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_45 : constant Interrupt_ID := 69; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_46 : constant Interrupt_ID := 70; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_47 : constant Interrupt_ID := 71; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_48 : constant Interrupt_ID := 72; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_49 : constant Interrupt_ID := 73; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_50 : constant Interrupt_ID := 74; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_51 : constant Interrupt_ID := 75; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_52 : constant Interrupt_ID := 76; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_53 : constant Interrupt_ID := 77; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_54 : constant Interrupt_ID := 78; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_55 : constant Interrupt_ID := 79; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_56 : constant Interrupt_ID := 80; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_57 : constant Interrupt_ID := 81; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_58 : constant Interrupt_ID := 82; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_59 : constant Interrupt_ID := 83; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_60 : constant Interrupt_ID := 84; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_61 : constant Interrupt_ID := 85; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_62 : constant Interrupt_ID := 86; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_63 : constant Interrupt_ID := 87; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_64 : constant Interrupt_ID := 88; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_65 : constant Interrupt_ID := 89; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_66 : constant Interrupt_ID := 90; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_67 : constant Interrupt_ID := 91; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_68 : constant Interrupt_ID := 92; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_69 : constant Interrupt_ID := 93; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_70 : constant Interrupt_ID := 94; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_71 : constant Interrupt_ID := 95; + -- R5FSS0 Core 0 and Core 1 + + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_88 : constant Interrupt_ID := 64; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_89 : constant Interrupt_ID := 65; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_90 : constant Interrupt_ID := 66; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_91 : constant Interrupt_ID := 67; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_92 : constant Interrupt_ID := 68; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_93 : constant Interrupt_ID := 69; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_94 : constant Interrupt_ID := 70; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_95 : constant Interrupt_ID := 71; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_96 : constant Interrupt_ID := 72; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_97 : constant Interrupt_ID := 73; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_98 : constant Interrupt_ID := 74; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_99 : constant Interrupt_ID := 75; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_100 : constant Interrupt_ID := 76; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_101 : constant Interrupt_ID := 77; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_102 : constant Interrupt_ID := 78; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_103 : constant Interrupt_ID := 79; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_104 : constant Interrupt_ID := 80; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_105 : constant Interrupt_ID := 81; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_106 : constant Interrupt_ID := 82; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_107 : constant Interrupt_ID := 83; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_108 : constant Interrupt_ID := 84; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_109 : constant Interrupt_ID := 85; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_110 : constant Interrupt_ID := 86; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_111 : constant Interrupt_ID := 87; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_112 : constant Interrupt_ID := 88; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_113 : constant Interrupt_ID := 89; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_114 : constant Interrupt_ID := 90; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_115 : constant Interrupt_ID := 91; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_116 : constant Interrupt_ID := 92; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_117 : constant Interrupt_ID := 93; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_118 : constant Interrupt_ID := 94; + DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_119 : constant Interrupt_ID := 95; + -- R5FSS1 Core 0 and Core 1 + + MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_0 : + constant Interrupt_ID := 96; + MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_0 : + constant Interrupt_ID := 97; + MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_0 : + constant Interrupt_ID := 98; + MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_0 : + constant Interrupt_ID := 99; + MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_0 : + constant Interrupt_ID := 100; + -- R5FSS0 Core 0 + + MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_1 : + constant Interrupt_ID := 96; + MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_1 : + constant Interrupt_ID := 97; + MAILBOX0_MAILBOX_CLUSTER_2_MAILBOX_CLUSTER_PEND_1 : + constant Interrupt_ID := 98; + MAILBOX0_MAILBOX_CLUSTER_3_MAILBOX_CLUSTER_PEND_1 : + constant Interrupt_ID := 99; + MAILBOX0_MAILBOX_CLUSTER_6_MAILBOX_CLUSTER_PEND_1 : + constant Interrupt_ID := 100; + -- R5FSS0 Core 1 + + MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_2 : + constant Interrupt_ID := 96; + MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_2 : + constant Interrupt_ID := 97; + MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_0 : + constant Interrupt_ID := 98; + MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_0 : + constant Interrupt_ID := 99; + MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_0 : + constant Interrupt_ID := 100; + -- R5FSS1 Core 0 + + MAILBOX0_MAILBOX_CLUSTER_0_MAILBOX_CLUSTER_PEND_3 : + constant Interrupt_ID := 96; + MAILBOX0_MAILBOX_CLUSTER_1_MAILBOX_CLUSTER_PEND_3 : + constant Interrupt_ID := 97; + MAILBOX0_MAILBOX_CLUSTER_4_MAILBOX_CLUSTER_PEND_1 : + constant Interrupt_ID := 98; + MAILBOX0_MAILBOX_CLUSTER_5_MAILBOX_CLUSTER_PEND_1 : + constant Interrupt_ID := 99; + MAILBOX0_MAILBOX_CLUSTER_7_MAILBOX_CLUSTER_PEND_1 : + constant Interrupt_ID := 100; + -- R5FSS1 Core 0 + + GLUELOGIC_MAINRESET_REQUEST_GLUE_MAIN_RESETZ_SYNC_STRETCH_0 : + constant Interrupt_ID := 101; + GLUELOGIC_MAINRESET_REQUEST_GLUE_MAIN_PORZ_SYNC_STRETCH_0 : + constant Interrupt_ID := 102; + -- All cores + + PCIE0_PCIE_DPA_PULSE_0 : constant Interrupt_ID := 103; + -- All cores + + MCU_MCU_GPIOMUX_INTROUTER0_OUTP_0 : constant Interrupt_ID := 104; + MCU_MCU_GPIOMUX_INTROUTER0_OUTP_1 : constant Interrupt_ID := 105; + MCU_MCU_GPIOMUX_INTROUTER0_OUTP_2 : constant Interrupt_ID := 106; + MCU_MCU_GPIOMUX_INTROUTER0_OUTP_3 : constant Interrupt_ID := 107; + -- All cores + + EPWM0_EPWM_ETINT_0 : constant Interrupt_ID := 108; + EPWM0_EPWM_TRIPZINT_0 : constant Interrupt_ID := 109; + EPWM1_EPWM_ETINT_0 : constant Interrupt_ID := 110; + EPWM1_EPWM_TRIPZINT_0 : constant Interrupt_ID := 111; + EPWM2_EPWM_ETINT_0 : constant Interrupt_ID := 112; + EPWM2_EPWM_TRIPZINT_0 : constant Interrupt_ID := 113; + EPWM3_EPWM_ETINT_0 : constant Interrupt_ID := 114; + EPWM3_EPWM_TRIPZINT_0 : constant Interrupt_ID := 115; + EPWM4_EPWM_ETINT_0 : constant Interrupt_ID := 116; + EPWM4_EPWM_TRIPZINT_0 : constant Interrupt_ID := 117; + EPWM5_EPWM_ETINT_0 : constant Interrupt_ID := 118; + -- All cores + + CTRL_MMR0_ACCESS_ERR_0 : constant Interrupt_ID := 119; + -- All cores + + PRU_ICSSG0_PR1_HOST_INTR_PEND_0 : constant Interrupt_ID := 120; + PRU_ICSSG0_PR1_HOST_INTR_PEND_1 : constant Interrupt_ID := 121; + PRU_ICSSG0_PR1_HOST_INTR_PEND_2 : constant Interrupt_ID := 122; + PRU_ICSSG0_PR1_HOST_INTR_PEND_3 : constant Interrupt_ID := 123; + PRU_ICSSG0_PR1_HOST_INTR_PEND_4 : constant Interrupt_ID := 124; + PRU_ICSSG0_PR1_HOST_INTR_PEND_5 : constant Interrupt_ID := 125; + PRU_ICSSG0_PR1_HOST_INTR_PEND_6 : constant Interrupt_ID := 126; + PRU_ICSSG0_PR1_HOST_INTR_PEND_7 : constant Interrupt_ID := 127; + -- All cores + + ADC0_GEN_LEVEL_0 : constant Interrupt_ID := 128; + CPTS0_EVNT_PEND_0 : constant Interrupt_ID := 129; + MCU_CTRL_MMR0_ACCESS_ERR_0 : constant Interrupt_ID := 130; + PADCFG_CTRL0_ACCESS_ERR_0 : constant Interrupt_ID := 131; + MCU_PADCFG_CTRL0_ACCESS_ERR_0 : constant Interrupt_ID := 132; + GLUELOGIC_CBASS_INTR_OR_GLUE_MAIN_CBASS_AGG_ERR_INTR_0 : + constant Interrupt_ID := 133; + CPSW0_EVNT_PEND_0 : constant Interrupt_ID := 134; + CPSW0_MDIO_PEND_0 : constant Interrupt_ID := 135; + CPSW0_STAT_PEND_0 : constant Interrupt_ID := 136; + MCU_DCC0_INTR_DONE_LEVEL_0 : constant Interrupt_ID := 137; + EPWM5_EPWM_TRIPZINT_0 : constant Interrupt_ID := 139; + ECAP0_ECAP_INT_0 : constant Interrupt_ID := 140; + ECAP1_ECAP_INT_0 : constant Interrupt_ID := 141; + ECAP2_ECAP_INT_0 : constant Interrupt_ID := 142; + EQEP0_EQEP_INT_0 : constant Interrupt_ID := 143; + EQEP1_EQEP_INT_0 : constant Interrupt_ID := 144; + EQEP2_EQEP_INT_0 : constant Interrupt_ID := 145; + EPWM6_EPWM_ETINT_0 : constant Interrupt_ID := 146; + EPWM6_EPWM_TRIPZINT_0 : constant Interrupt_ID := 147; + EPWM7_EPWM_ETINT_0 : constant Interrupt_ID := 148; + EPWM7_EPWM_TRIPZINT_0 : constant Interrupt_ID := 149; + EPWM8_EPWM_ETINT_0 : constant Interrupt_ID := 150; + DDR16SS0_DDRSS_CONTROLLER_0 : constant Interrupt_ID := 151; + -- All cores + + TIMER0_INTR_PEND_0 : constant Interrupt_ID := 152; + TIMER1_INTR_PEND_0 : constant Interrupt_ID := 153; + TIMER2_INTR_PEND_0 : constant Interrupt_ID := 154; + TIMER3_INTR_PEND_0 : constant Interrupt_ID := 155; + -- Reserved for runtime use + + TIMER4_INTR_PEND_0 : constant Interrupt_ID := 156; + TIMER5_INTR_PEND_0 : constant Interrupt_ID := 157; + TIMER6_INTR_PEND_0 : constant Interrupt_ID := 158; + TIMER7_INTR_PEND_0 : constant Interrupt_ID := 159; + TIMER8_INTR_PEND_0 : constant Interrupt_ID := 160; + TIMER9_INTR_PEND_0 : constant Interrupt_ID := 161; + TIMER10_INTR_PEND_0 : constant Interrupt_ID := 162; + TIMER11_INTR_PEND_0 : constant Interrupt_ID := 163; + -- All cores + + ELM0_ELM_POROCPSINTERRUPT_LVL_0 : constant Interrupt_ID := 164; + MMCSD0_EMMCSS_INTR_0 : constant Interrupt_ID := 165; + MMCSD1_EMMCSDSS_INTR_0 : constant Interrupt_ID := 166; + ESM0_ESM_INT_CFG_LVL_0 : constant Interrupt_ID := 167; + ESM0_ESM_INT_HI_LVL_0 : constant Interrupt_ID := 168; + ESM0_ESM_INT_LOW_LVL_0 : constant Interrupt_ID := 169; + PRU_ICSSG0_ISO_RESET_PROTCOL_ACK_0 : constant Interrupt_ID := 170; + FSS0_OSPI_0_OSPI_LVL_INTR_0 : constant Interrupt_ID := 171; + PRU_ICSSG1_ISO_RESET_PROTCOL_ACK_0 : constant Interrupt_ID := 172; + GICSS0_GIC_PWR0_WAKE_REQUEST_0 : constant Interrupt_ID := 173; + GICSS0_GIC_PWR0_WAKE_REQUEST_1 : constant Interrupt_ID := 174; + -- All cores + + R5FSS0_CORE0_CTI_0 : constant Interrupt_ID := 175; + R5FSS0_CORE1_CTI_0 : constant Interrupt_ID := 176; + -- R5FSS0 Core 0 and Core 1 + + R5FSS1_CORE0_CTI_0 : constant Interrupt_ID := 175; + R5FSS1_CORE1_CTI_0 : constant Interrupt_ID := 176; + -- R5FSS1 Core 0 and Core 1 + + DDPA0_DDPA_INTR_0 : constant Interrupt_ID := 177; + EPWM8_EPWM_TRIPZINT_0 : constant Interrupt_ID := 178; + SERDES_10G0_PHY_PWR_TIMEOUT_LVL_0 : constant Interrupt_ID := 180; + GLUELOGIC_DCC_DONE_GLUE_MAIN_DCC_DONE_0 : constant Interrupt_ID := 182; + -- All cores + + VTM0_THERM_LVL_GT_TH1_INTR_0 : constant Interrupt_ID := 183; + VTM0_THERM_LVL_GT_TH2_INTR_0 : constant Interrupt_ID := 184; + VTM0_THERM_LVL_LT_TH0_INTR_0 : constant Interrupt_ID := 185; + -- All cores + + MCAN0_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 : constant Interrupt_ID := 186; + MCAN0_MCANSS_MCAN_LVL_INT_0 : constant Interrupt_ID := 187; + MCAN0_MCANSS_MCAN_LVL_INT_1 : constant Interrupt_ID := 188; + MCAN1_MCANSS_EXT_TS_ROLLOVER_LVL_INT_0 : constant Interrupt_ID := 189; + MCAN1_MCANSS_MCAN_LVL_INT_0 : constant Interrupt_ID := 190; + MCAN1_MCANSS_MCAN_LVL_INT_1 : constant Interrupt_ID := 191; + -- All cores + + MCU_MCRC64_0_INT_MCRC_0 : constant Interrupt_ID := 192; + -- All cores + + I2C0_POINTRPEND_0 : constant Interrupt_ID := 193; + I2C1_POINTRPEND_0 : constant Interrupt_ID := 194; + I2C2_POINTRPEND_0 : constant Interrupt_ID := 195; + I2C3_POINTRPEND_0 : constant Interrupt_ID := 196; + -- All cores + + PCIE0_PCIE_PWR_STATE_PULSE_0 : constant Interrupt_ID := 197; + GLUELOGIC_GLUE_EXT_INTN_OUT_0 : constant Interrupt_ID := 198; + -- All cores + SA2_UL0_SA_UL_PKA_0 : constant Interrupt_ID := 199; + SA2_UL0_SA_UL_TRNG_0 : constant Interrupt_ID := 200; + -- All cores + + DEBUGSS0_AQCMPINTR_LEVEL_0 : constant Interrupt_ID := 201; + DEBUGSS0_CTM_LEVEL_0 : constant Interrupt_ID := 202; + -- All cores + + PSC0_PSC_ALLINT_0 : constant Interrupt_ID := 203; + -- All cores + + MCSPI0_INTR_SPI_0 : constant Interrupt_ID := 204; + MCSPI1_INTR_SPI_0 : constant Interrupt_ID := 205; + MCSPI2_INTR_SPI_0 : constant Interrupt_ID := 206; + MCSPI4_INTR_SPI_0 : constant Interrupt_ID := 207; + MCU_MCSPI0_INTR_SPI_0 : constant Interrupt_ID := 208; + MCU_MCSPI1_INTR_SPI_0 : constant Interrupt_ID := 209; + -- All cores + + UART0_USART_IRQ_0 : constant Interrupt_ID := 210; + UART1_USART_IRQ_0 : constant Interrupt_ID := 211; + UART2_USART_IRQ_0 : constant Interrupt_ID := 212; + UART3_USART_IRQ_0 : constant Interrupt_ID := 213; + UART4_USART_IRQ_0 : constant Interrupt_ID := 214; + UART5_USART_IRQ_0 : constant Interrupt_ID := 215; + UART6_USART_IRQ_0 : constant Interrupt_ID := 216; + MCU_UART0_USART_IRQ_0 : constant Interrupt_ID := 217; + MCU_UART1_USART_IRQ_0 : constant Interrupt_ID := 218; + -- All cores + + USB0_HOST_SYSTEM_ERROR_0 : constant Interrupt_ID := 219; + USB0_IRQ_0 : constant Interrupt_ID := 220; + USB0_IRQ_1 : constant Interrupt_ID := 221; + USB0_IRQ_2 : constant Interrupt_ID := 222; + USB0_IRQ_3 : constant Interrupt_ID := 223; + USB0_IRQ_4 : constant Interrupt_ID := 224; + USB0_IRQ_5 : constant Interrupt_ID := 225; + USB0_IRQ_6 : constant Interrupt_ID := 226; + USB0_IRQ_7 : constant Interrupt_ID := 227; + USB0_OTGIRQ_0 : constant Interrupt_ID := 228; + -- All cores + + PCIE0_PCIE_CPTS_PEND_0 : constant Interrupt_ID := 229; + PCIE0_PCIE_DOWNSTREAM_PULSE_0 : constant Interrupt_ID := 230; + PCIE0_PCIE_FLR_PULSE_0 : constant Interrupt_ID := 231; + PCIE0_PCIE_ERROR_PULSE_0 : constant Interrupt_ID := 232; + PCIE0_PCIE_HOT_RESET_PULSE_0 : constant Interrupt_ID := 233; + PCIE0_PCIE_LEGACY_PULSE_0 : constant Interrupt_ID := 234; + PCIE0_PCIE_LINK_STATE_PULSE_0 : constant Interrupt_ID := 235; + PCIE0_PCIE_LOCAL_LEVEL_0 : constant Interrupt_ID := 236; + PCIE0_PCIE_PHY_LEVEL_0 : constant Interrupt_ID := 237; + PCIE0_PCIE_PTM_VALID_PULSE_0 : constant Interrupt_ID := 238; + -- All cores + + GPMC0_GPMC_SINTERRUPT_0 : constant Interrupt_ID := 239; + -- All cores + + PRU_ICSSG1_PR1_RX_SOF_INTR_REQ_0 : constant Interrupt_ID := 240; + PRU_ICSSG1_PR1_RX_SOF_INTR_REQ_1 : constant Interrupt_ID := 241; + PRU_ICSSG1_PR1_TX_SOF_INTR_REQ_0 : constant Interrupt_ID := 242; + PRU_ICSSG1_PR1_TX_SOF_INTR_REQ_1 : constant Interrupt_ID := 243; + PRU_ICSSG0_PR1_RX_SOF_INTR_REQ_0 : constant Interrupt_ID := 244; + PRU_ICSSG0_PR1_RX_SOF_INTR_REQ_1 : constant Interrupt_ID := 245; + PRU_ICSSG0_PR1_TX_SOF_INTR_REQ_0 : constant Interrupt_ID := 246; + PRU_ICSSG0_PR1_TX_SOF_INTR_REQ_1 : constant Interrupt_ID := 247; + PRU_ICSSG1_PR1_HOST_INTR_PEND_0 : constant Interrupt_ID := 248; + PRU_ICSSG1_PR1_HOST_INTR_PEND_1 : constant Interrupt_ID := 249; + PRU_ICSSG1_PR1_HOST_INTR_PEND_2 : constant Interrupt_ID := 250; + PRU_ICSSG1_PR1_HOST_INTR_PEND_3 : constant Interrupt_ID := 251; + PRU_ICSSG1_PR1_HOST_INTR_PEND_4 : constant Interrupt_ID := 252; + PRU_ICSSG1_PR1_HOST_INTR_PEND_5 : constant Interrupt_ID := 253; + PRU_ICSSG1_PR1_HOST_INTR_PEND_6 : constant Interrupt_ID := 254; + PRU_ICSSG1_PR1_HOST_INTR_PEND_7 : constant Interrupt_ID := 255; + -- All cores + +end Ada.Interrupts.Names; diff --git a/src/g-interr__ti_vim.adb b/src/g-interr__ti_vim.adb new file mode 100644 index 00000000..def76dc8 --- /dev/null +++ b/src/g-interr__ti_vim.adb @@ -0,0 +1,244 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME COMPONENTS -- +-- -- +-- S Y S T E M . T I . V E C T O R E D _ I N T E R R U P T _ M A N A G E R -- +-- -- +-- B o d y -- +-- -- +-- Copyright (C) 2023, AdaCore -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNARL is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- The port of GNARL to bare board targets was initially developed by the -- +-- Real-Time Systems Group at the Technical University of Madrid. -- +-- -- +------------------------------------------------------------------------------ + +with Ada.Unchecked_Conversion; +with System; +with System.BB.Interrupts; + +package body GNAT.Interrupts is + package VIM renames System.TI.Vectored_Interrupt_Manager; + use System, System.BB.Interrupts, VIM; + + function To_Address is new + Ada.Unchecked_Conversion (Direct_Interrupt_Handler, System.Address); + + -------------------- + -- Attach_Handler -- + -------------------- + + procedure Attach_Handler + (New_Handler : Direct_Interrupt_Handler; + Interrupt : Ada.Interrupts.Interrupt_ID; + Kind : VIM_Interrupt_Kind; + Event_Type : VIM_Interrupt_Type := VIM_Interrupt_Type'First; + Prio : VIM_Interrupt_Priority := VIM_Interrupt_Priority'Last; + Enable : Boolean := True) + is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + + Interrupt_Group_Register renames + VIM_Interrupt_Group_Register (Group_ID); + + begin + VIM_Interrupt_Vector_Register (ID) := To_Address (New_Handler); + + VIM_Priority_Register (ID).Priority := Prio; + Interrupt_Group_Register.Interrupt_Map_Register (Sub_ID) := Kind; + Interrupt_Group_Register.Interrupt_Type_Register (Sub_ID) := Event_Type; + Interrupt_Group_Register.Interrupt_Enable_Register (Sub_ID) := + (if Enable then VIM.Enable else VIM.Disable); + end Attach_Handler; + + -------------------- + -- Detach_Handler -- + -------------------- + + procedure Detach_Handler (Interrupt : Ada.Interrupts.Interrupt_ID) is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + begin + VIM_Interrupt_Group_Register (Group_ID). + Interrupt_Enable_Register (Sub_ID) := VIM.Disable; + VIM_Interrupt_Vector_Register (ID) := Null_Address; + end Detach_Handler; + + ----------------------- + -- Disable_Interrupt -- + ----------------------- + + procedure Disable_Interrupt (Interrupt : Ada.Interrupts.Interrupt_ID) is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + begin + VIM_Interrupt_Group_Register (Group_ID). + Interrupt_Enable_Register (Sub_ID) := VIM.Disable; + end Disable_Interrupt; + + ------------------------- + -- Clear_Priority_Mask -- + ------------------------- + + procedure Clear_Priority_Mask is + begin + VIM_IRQ_Vector_Register := Null_Address; + end Clear_Priority_Mask; + + ---------------------- + -- Clear_VIM_Status -- + ---------------------- + + procedure Clear_VIM_Status (Interrupt : Ada.Interrupts.Interrupt_ID) is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + begin + VIM_Interrupt_Group_Register (Group_ID). + Interrupt_Status_Register (Sub_ID) := Active_Clear; + end Clear_VIM_Status; + + ---------------------- + -- Enable_Interrupt -- + ---------------------- + + procedure Enable_Interrupt (Interrupt : Ada.Interrupts.Interrupt_ID) is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + begin + VIM_Interrupt_Group_Register (Group_ID). + Interrupt_Enable_Register (Sub_ID) := VIM.Enable; + end Enable_Interrupt; + + ------------------------ + -- Interrupt_Priority -- + ------------------------ + + function Interrupt_Priority + (Interrupt : Ada.Interrupts.Interrupt_ID) + return VIM_Interrupt_Priority + is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + -- The ID of Interrupt + begin + return VIM_Priority_Register (ID).Priority; + end Interrupt_Priority; + + -------------------- + -- Interrupt_Type -- + -------------------- + + function Interrupt_Type + (Interrupt : Ada.Interrupts.Interrupt_ID) + return VIM_Interrupt_Type + is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + begin + return VIM_Interrupt_Group_Register (Group_ID). + Interrupt_Type_Register (Sub_ID); + end Interrupt_Type; + + ---------------- + -- Is_Enabled -- + ---------------- + + function Is_Enabled (Interrupt : Ada.Interrupts.Interrupt_ID) + return Boolean + is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + begin + return VIM_Interrupt_Group_Register (Group_ID). + Interrupt_Enable_Register (Sub_ID) = Enable; + end Is_Enabled; + + ------------------------------ + -- Raise_Software_Interrupt -- + ------------------------------ + + procedure Raise_Software_Interrupt (Interrupt : Ada.Interrupts.Interrupt_ID) + is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + begin + VIM_Interrupt_Group_Register (Group_ID). + Raw_Status_Register (Sub_ID) := Active_Set; + + end Raise_Software_Interrupt; + + ---------------------------- + -- Set_Interrupt_Priority -- + ---------------------------- + + procedure Set_Interrupt_Priority + (Interrupt : Ada.Interrupts.Interrupt_ID; + Prio : VIM_Interrupt_Priority) + is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + -- The ID of Interrupt + begin + VIM_Priority_Register (ID).Priority := Prio; + end Set_Interrupt_Priority; + + ------------------------ + -- Set_Interrupt_Type -- + ------------------------ + + procedure Set_Interrupt_Type + (Interrupt : Ada.Interrupts.Interrupt_ID; + Event_Type : VIM_Interrupt_Type) + is + ID : constant Interrupt_ID := Interrupt_ID (Interrupt); + Group_ID : constant Interrupt_Group := VIM_Group_ID (ID); + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (ID); + -- The ID of the interrupt, the register group it belongs to and its ID + -- within that group. + begin + VIM_Interrupt_Group_Register (Group_ID). + Interrupt_Type_Register (Sub_ID) := Event_Type; + end Set_Interrupt_Type; +end GNAT.Interrupts; diff --git a/src/g-interr__ti_vim.ads b/src/g-interr__ti_vim.ads new file mode 100644 index 00000000..6cc16a75 --- /dev/null +++ b/src/g-interr__ti_vim.ads @@ -0,0 +1,156 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME COMPONENTS -- +-- -- +-- G N A T . I N T E R R U P T S -- +-- -- +-- S p e c -- +-- -- +-- Copyright (C) 2023, AdaCore -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNARL is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- The port of GNARL to bare board targets was initially developed by the -- +-- Real-Time Systems Group at the Technical University of Madrid. -- +-- -- +------------------------------------------------------------------------------ + +-- Provides a high level interface to Interrupt controllers. Generally +-- interrupts are managed by the GNAT runtime and interrupt handlers are +-- attached through protected procedure handlers. This package provides access +-- to additional interrupt controller features that may not be exposed via +-- Ada, for example setting whether an interrupt is pulse or level. + +-- This version targets TI's Vectored Interrupt Manager for the TI Keystone +-- Cortex-R5F. Specifically, for each VIM interrupt it allows: +-- +-- * Enabling and disabling interrupts at the VIM; +-- * Raising a software interrupt (for testing); +-- * Setting the type of interrupt event (level (default) or pulse); +-- * Setting the priority of the interrupt at the VIM. +-- +-- Note: The TI Keystone Cortex-R5F runtimes do not support nested priorities +-- and the VIM interrupt priorities are only used to determine which interrupt +-- has precedence to be serviced when there are multiple pending interrupts. +-- +-- Additionally, GNAT.Interrupts support direct attachment of IRQ and FIQ +-- interrupt handlers to the VIM that bypasses the GNAT runtime. This allows +-- users to provide low latency handlers. Direct attachment of handlers come +-- with the following limitations: +-- +-- * Nesting of interrupts is not supported; +-- * Interrupts must not be reenabled while in a handler; +-- * Handler *must* not make any runtime calls, including calling protected +-- subprograms; +-- * Handler should not use the FPU; +-- * Users are responsible for save and restoring register state, and +-- returning from the interrupt. This can be done by using the "interrupt" +-- machine attribute on the handler procedure; +-- * Users must follow TI's documentation on "Servicing IRQ Through Vector +-- Interface" for IRQ handlers and "Servicing FIQ" for FIQ handlers. +-- Use the provided procedures Clear_VIM_Status and Clear_Priority_Mask to +-- clear the interrupt status and VIM priority. + +with Ada.Interrupts; +with System.TI.Vectored_Interrupt_Manager; + +package GNAT.Interrupts is + + -------------------------------------- + -- Vectored Interrupt Manager Types -- + -------------------------------------- + + subtype VIM_Interrupt_Priority is + System.TI.Vectored_Interrupt_Manager.VIM_Interrupt_Priority; + -- Interrupt priorities in the VIM + + subtype VIM_Interrupt_Type is + System.TI.Vectored_Interrupt_Manager.Interrupt_Type; + -- Type of interrupt event: Level, Pulse + + subtype VIM_Interrupt_Kind is + System.TI.Vectored_Interrupt_Manager.Interrupt_Kind; + -- Kind of interrupt: IRQ, FIQ + + type Direct_Interrupt_Handler is access procedure; + -- Parameterless access to procedure type for the handler to attach + -- directly. + + -------------------- + -- VIM Operations -- + -------------------- + + procedure Enable_Interrupt (Interrupt : Ada.Interrupts.Interrupt_ID); + procedure Disable_Interrupt (Interrupt : Ada.Interrupts.Interrupt_ID); + -- Enable and disable the interrupt in the VIM + + function Is_Enabled (Interrupt : Ada.Interrupts.Interrupt_ID) + return Boolean; + -- Returns True if the interrupt is enabled in the VIM + + procedure Raise_Software_Interrupt + (Interrupt : Ada.Interrupts.Interrupt_ID); + -- Raise the named interrupt at the VIM. This sets the relevant bit in + -- Raw Status/Set register (R5FSS_VIM_RAW_j) + + procedure Set_Interrupt_Type + (Interrupt : Ada.Interrupts.Interrupt_ID; + Event_Type : VIM_Interrupt_Type); + function Interrupt_Type + (Interrupt : Ada.Interrupts.Interrupt_ID) + return VIM_Interrupt_Type; + -- Set and get the event type of interrupt, i.e.: Level or Pulse + + procedure Set_Interrupt_Priority + (Interrupt : Ada.Interrupts.Interrupt_ID; + Prio : VIM_Interrupt_Priority); + function Interrupt_Priority + (Interrupt : Ada.Interrupts.Interrupt_ID) + return VIM_Interrupt_Priority; + -- Set and get the priority of the interrupt + + ------------------------------- + -- Direct Handler Attachment -- + ------------------------------- + + procedure Attach_Handler + (New_Handler : Direct_Interrupt_Handler; + Interrupt : Ada.Interrupts.Interrupt_ID; + Kind : VIM_Interrupt_Kind; + Event_Type : VIM_Interrupt_Type := VIM_Interrupt_Type'First; + Prio : VIM_Interrupt_Priority := VIM_Interrupt_Priority'Last; + Enable : Boolean := True); + -- Attach the IRQ or FIQ interrupt handler for Interrupt directly to the + -- VIM, bypassing the GNAT runtime. Kind is either IRQ and FIQ, and must be + -- specified. Optionally, the Event_Type (Level or Pulse) and priority of + -- the interrupt in the VIM can be specified. By default, the interrupt + -- will be enabled but can remain disabled by passing False to Enable. + + procedure Detach_Handler (Interrupt : Ada.Interrupts.Interrupt_ID); + -- Detach the handler for Interrupt. This will disable the interrupt and + -- set the vector address for this interrupt to Null_Address. + + procedure Clear_VIM_Status (Interrupt : Ada.Interrupts.Interrupt_ID); + -- Clear the VIM interrupt status for Interrupt + + procedure Clear_Priority_Mask; + -- Clear the VIM priority mask + +end GNAT.Interrupts; diff --git a/src/i-arm_v7ar.ads b/src/i-arm_v7ar.ads index a2ff0caa..75c4a880 100644 --- a/src/i-arm_v7ar.ads +++ b/src/i-arm_v7ar.ads @@ -33,7 +33,6 @@ -- maintainance, access to control registers...) with System; --- @design used for the type ``Address`` package Interfaces.ARM_V7AR is pragma No_Elaboration_Code_All; diff --git a/src/s-bbbosu__am64xr5.adb b/src/s-bbbosu__am64xr5.adb new file mode 100644 index 00000000..dfc5551c --- /dev/null +++ b/src/s-bbbosu__am64xr5.adb @@ -0,0 +1,599 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS -- +-- -- +-- S Y S T E M . B B . B O A R D _ S U P P O R T -- +-- -- +-- B o d y -- +-- -- +-- Copyright (C) 1999-2002 Universidad Politecnica de Madrid -- +-- Copyright (C) 2003-2006 The European Space Agency -- +-- Copyright (C) 2003-2021, AdaCore -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNARL is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- The port of GNARL to bare board targets was initially developed by the -- +-- Real-Time Systems Group at the Technical University of Madrid. -- +-- -- +------------------------------------------------------------------------------ + +-- This is the TI AM64x/AM263x Arm Cortex-R5 version of this package. +-- +-- The package uses the following hardware resources: +-- +-- * The Global Timebase Counter (GTC) as the source for Clock; +-- * Timers 0 and 1 as the alarm source for R5FSS0 CPU 0 and 1 respectively; +-- * Timers 2 and 3 as the alarm source for R5FSS1 CPU 0 and 1 respectively; +-- * The local VIM controller for interrupt support. +-- +-- The timers are configured to use HFOSC0_CLKOUT as their clock source while +-- the GTC uses the default MAIN_PLL2_HSDIV5_CLKOUT source. + +with Interfaces; +with System.Machine_Code; +with System.BB.Parameters; +with System.TI.Vectored_Interrupt_Manager; + +package body System.BB.Board_Support is + use BB.Interrupts, BB.Time, Parameters; + use Interfaces; + use System.Machine_Code, System.Multiprocessors; + use Time; + + -------------------------- + -- Hardware Definitions -- + -------------------------- + + Number_CPU_Clusters : constant := 2; + -- Number of CPU clusters for our chip + + Number_Of_Timers : constant := 12; + -- Number of timers on the SoC + + type Timer_ID is mod Number_Of_Timers; + -- ID for each timer on the SoC + + ------------------------ + -- Hardware Registers -- + ------------------------ + + type MPIDR is record + Aff2 : Unsigned_8; + Aff1 : Unsigned_8; + Aff : Unsigned_8; + end record with Size => 32; + -- Multiprocessor Affinity Register + + for MPIDR use record + Aff2 at 0 range 16 .. 23; + Aff1 at 0 range 8 .. 15; + Aff at 0 range 0 .. 7; + end record; + + function MPIDR_Register return MPIDR; + -- Return the contents of the Multiprocessor Affinity Register + + -------------------- + -- Control Module -- + -------------------- + + -- See TI AM64x/AM243x Technical Reference Manual, 5.1 Control Module for + -- details + + Control_Module_Base_Address : constant := 16#4300_0000#; + -- Base address of the Control Module + + -- Control Module types + + type Timer_Clock_Source is (HFOSC0_CLKOUT); + for Timer_Clock_Source use (HFOSC0_CLKOUT => 0); + + type CTRLMMR_TIMERx_CLKSEL is record + Clock : Timer_Clock_Source; + end record; + + for CTRLMMR_TIMERx_CLKSEL use record + Clock at 0 range 0 .. 3; + end record; + + -- Control Module Registers + + Timer_Clock_Selection : array (Timer_ID'Range) of CTRLMMR_TIMERx_CLKSEL + with Volatile_Components, + Address => + System'To_Address (Control_Module_Base_Address + 16#81B0#); + -- CTRLMMR_TIMERx_CLKSEL registers + + ----------------------------- + -- Global Timebase Counter -- + ----------------------------- + + -- See TI AM64x/AM243x Technical Reference Manual, 12.5.1 Global Timebase + -- Counter for details. + + GTC_Base_Address : constant := 16#00A9_0000#; + -- Base address of the GTC module + + -- GTC types + + type Requested_Frequency is mod 2 ** 24; + + type Enable_Bit is (Disable, Enable); + for Enable_Bit use (Disable => 0, Enable => 1); + + type GTC_Counter_Control is record + Frequency_Change_Request : Requested_Frequency; + Halt_On_Debug : Boolean; + Enable_System_Counter : Boolean; + end record with Size => 32; + + for GTC_Counter_Control use record + Frequency_Change_Request at 0 range 8 .. 31; + Halt_On_Debug at 0 range 1 .. 1; + Enable_System_Counter at 0 range 0 .. 0; + end record; + + -- GTC registers + + GTC_Counter_Control_Register : GTC_Counter_Control + with Address => System'To_Address (GTC_Base_Address + 16#0#), + Volatile_Full_Access; + -- GTC0_CNTCR Register + + GTC_Counter_Low_Register : Unsigned_32 + with Address => System'To_Address (GTC_Base_Address + 16#8#); + -- GTC0_LO Register + + GTC_Counter_High_Register : Unsigned_32 + with Address => System'To_Address (GTC_Base_Address + 16#C#); + -- GTC0_HI Register + + ------------ + -- Timers -- + ------------ + + -- See TI AM64x/AM243x Technical Reference Manual, 12.5.3 Timers for + -- details. + + Timers_Base_Address : constant := 16#240_0000#; + -- Base address of the Timer modules + + TIMER0_INTR_PEND_0 : constant Interrupt_ID := 152; + -- Interrupt ID of Timer 0. The other timers are number sequentially. We + -- cannot use Ada.Interrupts.Names here since Ada.Interrupts is not + -- Preelaborate. + + -- Timer types + + type Timer_Idle_Mode is + (Force_Idle, No_Idle, Smart_Idle, Smart_Idle_Wake_Up); + for Timer_Idle_Mode use + (Force_Idle => 0, No_Idle => 1, Smart_Idle => 2, Smart_Idle_Wake_Up => 3); + + type Timer_Emulation_Mode is (Frozen, Free); + for Timer_Emulation_Mode use (Frozen => 0, Free => 1); + + type TIMER_TIOCP_CFG is record + Idle_Mode : Timer_Idle_Mode; + Emulation_Mode : Timer_Emulation_Mode; + Software_Reset : Boolean; + end record with Size => 32, Volatile_Full_Access; + + for TIMER_TIOCP_CFG use record + Idle_Mode at 0 range 2 .. 3; + Emulation_Mode at 0 range 1 .. 1; + Software_Reset at 0 range 0 .. 0; + end record; + + type Interrupt_Line is range 0 .. 0; + + type TIMER_IRQ_EOI is record + Line_Number : Interrupt_Line; + end record with Size => 32, Volatile_Full_Access; + + for TIMER_IRQ_EOI use record + Line_Number at 0 range 0 .. 0; + end record; + + type Timer_GPIO_Config is (Output, Input); + for Timer_GPIO_Config use (Output => 0, Input => 1); + + type Timer_Capture_Mode is (Single, Double); + for Timer_Capture_Mode use (Single => 0, Double => 1); + + type Timer_Pulse_Toggle_Mode is (Pulse_Modulation, Toggle_Modulation); + for Timer_Pulse_Toggle_Mode use + (Pulse_Modulation => 0, Toggle_Modulation => 1); + + type Timer_Trigger_Mode is (No_Trigger, On_Overflow, On_Overflow_And_Match); + for Timer_Trigger_Mode use + (No_Trigger => 0, On_Overflow => 1, On_Overflow_And_Match => 2); + + type Timer_Transition_Capture_Mode is + (No_Capture, Rising_Edge, Falling_Edge, Both_Edges); + for Timer_Transition_Capture_Mode use + (No_Capture => 0, Rising_Edge => 1, Falling_Edge => 2, Both_Edges => 3); + + type Timer_PWM_Output_Pusle is (Positive, Negative); + for Timer_PWM_Output_Pusle use (Positive => 0, Negative => 1); + + type Timer_Prescale is mod 2 ** 3; + + type Timer_Control is (Stop, Start); + for Timer_Control use (Stop => 0, Start => 1); + + type TIMER_TCLR is record + GPO_Config : Timer_GPIO_Config; + Capture_Mode : Timer_Capture_Mode; + Output_Pulse_Toggle_Mode : Timer_Pulse_Toggle_Mode; + Output_Trigger_Mode : Timer_Trigger_Mode; + Transition_Capture_Mode : Timer_Transition_Capture_Mode; + PWM_Output_Pusle : Timer_PWM_Output_Pusle; + Compare_Enable : Boolean; + Prescaler_Enable : Boolean; + Prescale_Timer_Value : Timer_Prescale; + Autoreload : Boolean; + Start_Stop : Timer_Control; + end record with Size => 32, Volatile_Full_Access; + + for TIMER_TCLR use record + GPO_Config at 0 range 14 .. 14; + Capture_Mode at 0 range 13 .. 13; + Output_Pulse_Toggle_Mode at 0 range 12 .. 12; + Output_Trigger_Mode at 0 range 10 .. 11; + Transition_Capture_Mode at 0 range 8 .. 9; + PWM_Output_Pusle at 0 range 7 .. 7; + Compare_Enable at 0 range 6 .. 6; + Prescaler_Enable at 0 range 5 .. 5; + Prescale_Timer_Value at 0 range 2 .. 4; + Autoreload at 0 range 1 .. 1; + Start_Stop at 0 range 0 .. 0; + end record; + + type Pending_Clear_Bit is (No_Event, Pending_Clear); + for Pending_Clear_Bit use (No_Event => 0, Pending_Clear => 1); + + type TIMER_IRQSTATUS is record + Compare : Pending_Clear_Bit; + Overflow : Pending_Clear_Bit; + Match : Pending_Clear_Bit; + end record with Size => 32, Volatile_Full_Access; + + for TIMER_IRQSTATUS use record + Compare at 0 range 2 .. 2; + Overflow at 0 range 1 .. 1; + Match at 0 range 0 .. 0; + end record; + + type TIMER_IRQSTATUS_SET is record + Compare : Enable_Bit; + Overflow : Enable_Bit; + Match : Enable_Bit; + end record with Size => 32, Volatile_Full_Access; + + for TIMER_IRQSTATUS_SET use record + Compare at 0 range 2 .. 2; + Overflow at 0 range 1 .. 1; + Match at 0 range 0 .. 0; + end record; + + type Timer_Read_Mode is (Posted, Non_Posted); + for Timer_Read_Mode use (Posted => 0, Non_Posted => 1); + + type TIMER_TSICR is record + Read_After_Ide : Boolean; + Read_Mode : Timer_Read_Mode; + Posted : Enable_Bit; + Reset_Posted_Bit : Boolean; + end record with Size => 32, Volatile_Full_Access; + + for TIMER_TSICR use record + Read_After_Ide at 0 range 4 .. 4; + Read_Mode at 0 range 3 .. 3; + Posted at 0 range 2 .. 2; + Reset_Posted_Bit at 0 range 1 .. 1; + end record; + + pragma Warnings (Off, "*bits of*"); + -- Suppress warning of unused bits in Timer. The unused bits is + -- expected for the Timers module as each module is placed at 16#1_0000# + -- offsets. + + type Timer is record + CBASS0_Configuration_Register : TIMER_TIOCP_CFG; + End_Of_Interrupt_Register : TIMER_IRQ_EOI; + Interrupt_Status_Register : TIMER_IRQSTATUS; + Interrupt_Enable_Register : TIMER_IRQSTATUS_SET; + Control_Register : TIMER_TCLR; + Counter_Register : Unsigned_32; + Compare_Register : Unsigned_32; + Synchronous_Interface_Control_Register : TIMER_TSICR; + end record with Size => 16#1_0000# * Storage_Unit; + + for Timer use record + CBASS0_Configuration_Register at 16#10# range 0 .. 31; + End_Of_Interrupt_Register at 16#20# range 0 .. 31; + Interrupt_Status_Register at 16#28# range 0 .. 31; + Interrupt_Enable_Register at 16#2C# range 0 .. 31; + Control_Register at 16#38# range 0 .. 31; + Counter_Register at 16#3C# range 0 .. 31; + Compare_Register at 16#4C# range 0 .. 31; + Synchronous_Interface_Control_Register at 16#54# range 0 .. 31; + end record; + + -- Timer Registers + + Timer_Register : array (Timer_ID) of Timer + with Address => Timers_Base_Address, Volatile_Components; + -- TIMERx_CFG Registers + + -- Timer helper functions + + function CPU_Timer return Timer_ID; + -- Get the timer used for runtime alarm + + --------------- + -- CPU_Timer -- + --------------- + + function CPU_Timer return Timer_ID is + ID_Reg : constant MPIDR := MPIDR_Register; + begin + -- CPUs are allocated timers based on their group and processors ID + -- starting from Cluster 0 CPU0 through to Cluster 1 CPU 1. + + return Timer_ID (ID_Reg.Aff1 * Number_CPU_Clusters + ID_Reg.Aff); + end CPU_Timer; + + ---------------------- + -- Initialize_Board -- + ---------------------- + + procedure Initialize_Board is + T : constant Timer_ID := CPU_Timer; + Alarm_Timer renames Timer_Register (T); + begin + + TI.Vectored_Interrupt_Manager.Initialize; + + -- Start the Global Timebase Counter + + GTC_Counter_Control_Register.Enable_System_Counter := True; + + -- Initialize alarm timer using HFOSC0_CLKOUT as the clock source. The + -- timer configured as a one-shot match timer. + + Timer_Clock_Selection (T) := (Clock => HFOSC0_CLKOUT); + + Alarm_Timer.CBASS0_Configuration_Register.Software_Reset := True; + + loop + exit when + not Alarm_Timer.CBASS0_Configuration_Register.Software_Reset; + end loop; + + Alarm_Timer.CBASS0_Configuration_Register := + (Idle_Mode => Smart_Idle, + Emulation_Mode => Frozen, + Software_Reset => False); + + Alarm_Timer.Synchronous_Interface_Control_Register := + (Read_After_Ide => False, + Read_Mode => Posted, + Posted => Enable, + Reset_Posted_Bit => False); + + Alarm_Timer.Control_Register := + (GPO_Config => Output, + Capture_Mode => Single, + Output_Pulse_Toggle_Mode => Pulse_Modulation, + Output_Trigger_Mode => No_Trigger, + Transition_Capture_Mode => No_Capture, + PWM_Output_Pusle => Positive, + Compare_Enable => False, + Prescaler_Enable => False, + Prescale_Timer_Value => 0, + Autoreload => False, + Start_Stop => Stop); + + Alarm_Timer.Interrupt_Enable_Register := + (Compare => Disable, Overflow => Disable, Match => Enable); + end Initialize_Board; + + package body Interrupts is + + ------------------------------- + -- Install_Interrupt_Handler -- + ------------------------------- + + procedure Install_Interrupt_Handler + (Interrupt : BB.Interrupts.Interrupt_ID; + Prio : Interrupt_Priority) + renames TI.Vectored_Interrupt_Manager.Install_Interrupt_Handler; + + --------------------------- + -- Priority_Of_Interrupt -- + --------------------------- + + function Priority_Of_Interrupt + (Interrupt : System.BB.Interrupts.Interrupt_ID) + return System.Any_Priority + renames TI.Vectored_Interrupt_Manager.Priority_Of_Interrupt; + + -------------------------- + -- Set_Current_Priority -- + -------------------------- + + procedure Set_Current_Priority (Priority : Integer) + renames TI.Vectored_Interrupt_Manager.Set_Current_Priority; + + ---------------- + -- Power_Down -- + ---------------- + + procedure Power_Down renames TI.Vectored_Interrupt_Manager.Power_Down; + end Interrupts; + + -------------------- + -- MPIDR_Register -- + -------------------- + + function MPIDR_Register return MPIDR is + MPIDR_State : MPIDR; + begin + Asm ("mrc p15,0,%0,c0,c0,5", + Outputs => MPIDR'Asm_Output ("=r", MPIDR_State), + Volatile => True); + return MPIDR_State; + end MPIDR_Register; + + package body Multiprocessors is separate; + + package body Time is + + --------------- + -- Set_Alarm -- + --------------- + + -- Set_Alarm sets the timer to fire (Ticks - Now) time in the future, + -- bounded by 1 (the shortest delay we can have) and Max_Timer_Value. As + -- part of the procedure, the delay needs to be converted from the GTC + -- timebase to the Timer timebase. To ensure that we can perform the + -- timebase conversion in 64 bits without overflow, the bounds are + -- applied before conversion in the GTC timebase. + + procedure Set_Alarm (Ticks : BB.Time.Time) is + T : constant Timer_ID := CPU_Timer; + Alarm_Timer renames Timer_Register (T); + -- Timer used for the alarm + + Now : constant BB.Time.Time := Read_Clock; + -- The current time + + Max_Timer_Value : constant := Unsigned_32'Last; + -- The highest value the timer can be set to + + Max_Timer_Value_In_GTC_Ticks : constant := + (Max_Timer_Value * GTC_Frequency) / Timer_Frequency; + -- The highest value the timer can set to in terms of GTC Ticks + + GTC_Ticks_To_Alarm : constant Unsigned_64 := + Unsigned_64 + (if Ticks <= Now then 1 + else + BB.Time.Time'Min (Ticks - Now, Max_Timer_Value_In_GTC_Ticks)); + -- Number of GTC ticks until the timer needs to fire, bounded by the + -- range 1 .. Max_Timer_Value_In_GTC_Ticks. The lower bound is needed + -- as we cannot set the timer to the past and the upper bound is the + -- the maximum value we can set in our timer; if we have an alarm + -- value greater than this then the runtime will set a new alarm once + -- this alarm fires. The upper bound is imposed here as it allows + -- conversion from GTC ticks to Timer ticks in 64-bit space without + -- overflow. + + Timer_Value : Unsigned_64; + -- The requested value for the timer + + begin + -- Ensure the timer is stopped before reseting the timer and setting + -- the compare value. + + Alarm_Timer.Control_Register.Start_Stop := Stop; + + -- Convert GTC_Ticks_To_Alarm from GTC timebase to the Timer + -- timebase to get the timer match value. We add an offset of + -- (GTC_Frequency/Timer_Frequency - 1) to GTC_Ticks_To_Alarm to have + -- the division round up, ensuring the timer does not fire earlier + -- than the desired time. + + Timer_Value := + ((GTC_Ticks_To_Alarm + GTC_Frequency / Timer_Frequency - 1) * + Timer_Frequency) / GTC_Frequency; + + Alarm_Timer.Counter_Register := 0; + Alarm_Timer.Compare_Register := Unsigned_32 (Timer_Value); + Alarm_Timer.Control_Register.Compare_Enable := True; + Alarm_Timer.Control_Register.Start_Stop := Start; + end Set_Alarm; + + ---------------- + -- Read_Clock -- + ---------------- + + function Read_Clock return BB.Time.Time is + Low : Unsigned_32; + High : Unsigned_32; + Reread_High : Unsigned_32; + -- Copies of the GTC Clock registers + begin + -- As we need to read the 64-bit clock in two seperate 32-bit reads, + -- we need to ensure the upper 32 bits do not change while the lower + -- 32 bits are read (which occurs when the lower part wraps around) + -- Consequently, we reread the upper half after the lower half is + -- read to ensure no change occurred. If it happens, we reread the + -- the clock registers again. + + High := GTC_Counter_High_Register; + loop + Low := GTC_Counter_Low_Register; + Reread_High := GTC_Counter_High_Register; + exit when High = Reread_High; + High := Reread_High; + end loop; + + return (BB.Time.Time (High) * 2 ** 32) + BB.Time.Time (Low); + end Read_Clock; + + --------------------------- + -- Install_Alarm_Handler -- + --------------------------- + + procedure Install_Alarm_Handler (Handler : Interrupt_Handler) is + begin + -- The timer we attach our handler to is TIMER0_INTR_PEND_0 + the + -- CPU timer number (which starts from 0). + + BB.Interrupts.Attach_Handler + (Handler, + (TIMER0_INTR_PEND_0 + Interrupt_ID (CPU_Timer)), + Interrupt_Priority'Last); + end Install_Alarm_Handler; + + --------------------------- + -- Clear_Alarm_Interrupt -- + --------------------------- + + procedure Clear_Alarm_Interrupt is + T : constant Timer_ID := CPU_Timer; + -- Timer used for the alarm + + Alarm_Timer renames Timer_Register (T); + begin + -- Note interrupt is a level line interrupt so we do not (and should) + -- not write to the End_Of_Interrupt register. + + Alarm_Timer.Control_Register.Start_Stop := Stop; + Alarm_Timer.Control_Register.Compare_Enable := False; + Alarm_Timer.Interrupt_Status_Register := + (Compare => No_Event, Overflow => No_Event, Match => Pending_Clear); + end Clear_Alarm_Interrupt; + end Time; + +end System.BB.Board_Support; diff --git a/src/s-bbcppr__arm.adb b/src/s-bbcppr__arm.adb index c89441a5..886ffbd3 100644 --- a/src/s-bbcppr__arm.adb +++ b/src/s-bbcppr__arm.adb @@ -191,6 +191,7 @@ package body System.BB.CPU_Primitives is Set_FPU_Enabled (False); -- Prepare the IRQ handler FPU context + IRQ_Ctxt.V_Init := False; Running_Thread_Table (CPU_Id).Context.Running := IRQ_Ctxt'Unchecked_Access; @@ -202,6 +203,7 @@ package body System.BB.CPU_Primitives is SPSR := Get_SPSR; -- Call the handler + if Is_FIQ then Fiq_User_Handler; else @@ -209,6 +211,7 @@ package body System.BB.CPU_Primitives is end if; -- Check FPU usage in handler + if Current_FPU_Context (CPU_Id) = IRQ_Ctxt'Unchecked_Access then -- FPU was used. -- Invalidate the current FPU context as we're leaving the IRQ diff --git a/src/s-bbpara__am64xr5.ads b/src/s-bbpara__am64xr5.ads new file mode 100644 index 00000000..5dd20934 --- /dev/null +++ b/src/s-bbpara__am64xr5.ads @@ -0,0 +1,125 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS -- +-- -- +-- S Y S T E M . B B . P A R A M E T E R S -- +-- -- +-- S p e c -- +-- -- +-- Copyright (C) 1999-2002 Universidad Politecnica de Madrid -- +-- Copyright (C) 2003-2005 The European Space Agency -- +-- Copyright (C) 2003-2021, AdaCore -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNARL is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- The port of GNARL to bare board targets was initially developed by the -- +-- Real-Time Systems Group at the Technical University of Madrid. -- +-- -- +------------------------------------------------------------------------------ + +-- This package defines basic parameters used by the low level tasking system + +-- This is the TI AM64x/AM243x Cortex-R5 version of this package + +package System.BB.Parameters is + pragma Pure; + pragma No_Elaboration_Code_All; + + --------------------- + -- Hardware clocks -- + --------------------- + + HFOSC0_CLKOUT : constant := 25_000_000; + -- Frequency of the HFOSC0_CLKOUT is 25MHz + + Timer_Frequency : constant := HFOSC0_CLKOUT; + -- Frequency of the Timer used for scheduler alarms + + GTC_Frequency : constant := 225_000_000; + -- Frequency of the Global Timebase Counter + + Ticks_Per_Second : constant := GTC_Frequency; + + ---------------- + -- Interrupts -- + ---------------- + + -- These definitions are in this package in order to isolate target + -- dependencies. + + subtype Interrupt_Range is Natural range 0 .. 255; + -- Number of interrupts supported by the AM64x Cortex R5 VIM + + Trap_Vectors : constant := 7; + -- ARMv7 has these traps: + -- 0 (at 16#0000#) Reset + -- 1 (at 16#0004#) Undefined Instruction (synchronous) + -- 2 (at 16#0008#) Supervisor Call (synchronous) + -- 3 (at 16#000C#) Abort - Prefetch (synchronous) + -- 4 (at 16#0010#) Abort - Data (asynchronous) + -- 5 (at 16#0014#) IRQ Trap (asynchronous) + -- 6 (at 16#0018#) FIQ Trap (asynchronous) + + Interrupt_Unmask_Priority : constant System.Interrupt_Priority := + System.Interrupt_Priority'Last; + -- The priority under which we unmask interrupts. + -- Useful when we use FIQ to simulate priorities on ARM. + + VIM_Base_Address : constant := 16#2FFF_0000#; + -- Base address of the Vectored Interrupt Manager + + ------------ + -- Stacks -- + ------------ + + Interrupt_Stack_Size : constant := 4096; + -- Size of each of the interrupt stacks. Each processor has its own + -- interrupt stack. In case interrupts are nested, the same stack is used. + + Interrupt_Sec_Stack_Size : constant := 128; + -- Size of the secondary stack for interrupt handlers + + ---------- + -- CPUS -- + ---------- + + Max_Number_Of_CPUs : constant := 1; + -- Maximum number of CPUs avaialble on the target. + + Multiprocessor : constant Boolean := Max_Number_Of_CPUs /= 1; + -- Are we on a multiprocessor board? + + ---------- + -- UART -- + ---------- + + UART_Base_Address : constant := 16#0280_0000#; + -- UART base address + + Number_Of_UART_Modules : constant := 6; + -- Number of UART Modules on the SoC + + type UART_ID is mod Number_Of_UART_Modules; + -- UART Modules on the SoC + + IO_Module : constant UART_ID := 0; + -- UART Module used by System.Text_IO + +end System.BB.Parameters; diff --git a/src/s-boapar__am64xr5.ads b/src/s-boapar__am64xr5.ads new file mode 100644 index 00000000..22acd56f --- /dev/null +++ b/src/s-boapar__am64xr5.ads @@ -0,0 +1,142 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS -- +-- -- +-- S Y S T E M . B O A R D _ P A R A M E T E R S -- +-- -- +-- S p e c -- +-- -- +-- Copyright (C) 1999-2002 Universidad Politecnica de Madrid -- +-- Copyright (C) 2003-2005 The European Space Agency -- +-- Copyright (C) 2003-2023, AdaCore -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNARL is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- The port of GNARL to bare board targets was initially developed by the -- +-- Real-Time Systems Group at the Technical University of Madrid. -- +-- -- +------------------------------------------------------------------------------ + +-- This package defines basic parameters used by the non tasking part of +-- the runtime. It contains MPU configuration. + +-- This is the TI AM64x/AM243x Cortex-R5 version of this package using the +-- following MPU layout: +-- * ATCM (first 32KB at 16#0000_0000#) +-- * BTCM (first 32KB at 16#4101_0000#) +-- * MSRAM (full 2MB non shared access) +-- * DDR (full 2GB non shared access) +-- * Background region read/write accessable + +with System.MPU_Definitions; + +package System.Board_Parameters is + pragma No_Elaboration_Code_All; + + package MD renames System.MPU_Definitions; + + MPU_Config : constant System.MPU_Definitions.MPU_Region_Config_Table := + ( + -- Background region (access to most MAIN peripherals via memory bus) + + 0 => (Base_Address => 16#0000_0000#, + Size_And_Enable => + (Sub_Region_Disable => 0, + Size => MD.Size_2GiB, + Enable => True), + Access_Control => + (XN => MD.Execute_Never, + AP => MD.Privileged_RW_User_RO, + TEX_S_C_B => MD.Strongly_Ordered)), + + -- ATCM (configured for dual core mode) + + 1 => (Base_Address => 16#0000_0000#, + Size_And_Enable => + (Sub_Region_Disable => 0, + Size => MD.Size_32KiB, + Enable => True), + Access_Control => + (XN => MD.Execute_All, + AP => MD.Privileged_RW_User_RO, + TEX_S_C_B => MD.Outer_Inner_NC_NS)), + + -- MAIN peripherals (via VBUSP peripheral port) + + 2 => (Base_Address => 16#2000_0000#, + Size_And_Enable => + (Sub_Region_Disable => 0, + Size => MD.Size_64MiB, + Enable => True), + Access_Control => + (XN => MD.Execute_Never, + AP => MD.Privileged_RW_User_RO, + TEX_S_C_B => MD.Strongly_Ordered)), + + -- BTCM (configured for dual core mode) + + 3 => (Base_Address => 16#4101_0000#, + Size_And_Enable => + (Sub_Region_Disable => 0, + Size => MD.Size_32KiB, + Enable => True), + Access_Control => + (XN => MD.Execute_All, + AP => MD.Privileged_RW_User_RO, + TEX_S_C_B => MD.Outer_Inner_NC_NS)), + + -- OSPI (FLASH) Memory. For production change the address and size to + -- match the memory region the application should have access to. + + 4 => (Base_Address => 16#6000_0000#, + Size_And_Enable => + (Sub_Region_Disable => 0, + Size => MD.Size_256MiB, + Enable => True), + Access_Control => + (XN => MD.Execute_All, + AP => MD.Privileged_RO_User_RO, + TEX_S_C_B => MD.Outer_Inner_WB_WA_NS)), + + -- MSRAM + + 5 => (Base_Address => 16#7000_0000#, + Size_And_Enable => + (Sub_Region_Disable => 0, + Size => MD.Size_2MiB, + Enable => True), + Access_Control => + (XN => MD.Execute_All, + AP => MD.Privileged_RW_User_RO, + TEX_S_C_B => MD.Outer_Inner_WB_WA_NS)), + + -- DDR + + 6 => (Base_Address => 16#8000_0000#, + Size_And_Enable => + (Sub_Region_Disable => 0, + Size => MD.Size_2GiB, + Enable => True), + Access_Control => + (XN => MD.Execute_All, + AP => MD.Privileged_RW_User_RW, + TEX_S_C_B => MD.Non_Shareable_Device)) + ); +end System.Board_Parameters; diff --git a/src/s-boapar__zynqmpr5.ads b/src/s-boapar__zynqmpr5.ads index 6d951ea0..2ea000c9 100644 --- a/src/s-boapar__zynqmpr5.ads +++ b/src/s-boapar__zynqmpr5.ads @@ -53,166 +53,111 @@ package System.Board_Parameters is Size_And_Enable => (Sub_Region_Disable => 2#1111_1111#, Size => MD.Size_4GiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_NA_User_NA, - TEX_S_C_B => MD.Strongly_Ordered, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Strongly_Ordered)), -- DDR 1 => (Base_Address => 16#0000_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_1GiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_All, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Outer_Inner_WB_WA_NS, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Outer_Inner_WB_WA_NS)), -- Strongly ordered memory for PL interface 2 => (Base_Address => 16#8000_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_1GiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Strongly_Ordered, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Strongly_Ordered)), -- QSPI 3 => (Base_Address => 16#C000_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_512MiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_All, AP => MD.Privileged_RO_User_RO, - TEX_S_C_B => MD.Non_Shareable_Device, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Non_Shareable_Device)), -- PCIe Low 4 => (Base_Address => 16#E000_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_256MiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Non_Shareable_Device, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Non_Shareable_Device)), -- STM_CORESIGHT 5 => (Base_Address => 16#F800_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_16MiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Non_Shareable_Device, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Non_Shareable_Device)), -- RPU_A53_GIC 6 => (Base_Address => 16#F900_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_1MiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Non_Shareable_Device, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Non_Shareable_Device)), -- FPS slaves 7 => (Base_Address => 16#FD00_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_16MiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Non_Shareable_Device, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Non_Shareable_Device)), -- Upper LPS slaves 8 => (Base_Address => 16#FE00_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_16MiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Non_Shareable_Device, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Non_Shareable_Device)), -- Lower LPS slaves 9 => (Base_Address => 16#FF00_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_16MiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Non_Shareable_Device, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)), + TEX_S_C_B => MD.Non_Shareable_Device)), -- OCM Ram 10 => (Base_Address => 16#FFFC_0000#, Size_And_Enable => (Sub_Region_Disable => 0, Size => MD.Size_256KiB, - Enable => True, - Reserved_1 => 0, - Reserved_2 => 0), + Enable => True), Access_Control => (XN => MD.Execute_Never, AP => MD.Privileged_RW_User_RW, - TEX_S_C_B => MD.Outer_Inner_WB_WA_NS, - Reserved_1 => 0, - Reserved_2 => 0, - Reserved_3 => 0)) + TEX_S_C_B => MD.Outer_Inner_WB_WA_NS)) ); end System.Board_Parameters; diff --git a/src/s-textio__16C750.adb b/src/s-textio__16C750.adb new file mode 100644 index 00000000..de683195 --- /dev/null +++ b/src/s-textio__16C750.adb @@ -0,0 +1,425 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME COMPONENTS -- +-- -- +-- S Y S T E M . T E X T _ I O -- +-- -- +-- B o d y -- +-- -- +-- Copyright (C) 1992-2020, Free Software Foundation, Inc. -- +-- -- +-- GNAT is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +------------------------------------------------------------------------------ + +-- Minimal version of Text_IO body for use on with 16C750-compatible UARTs + +-- This package is in charge of sending characters to the remote host +-- machine. The application output is sent through the UART, from which the +-- host machine extracts the application output. +-- +-- It's configured for 115200 baud rate, one stop bit, no parity using the +-- 48 MHz clock source + +with Interfaces; use Interfaces; +with System.BB.Parameters; use System.BB.Parameters; + +package body System.Text_IO is + + use System.BB.Parameters; + + ---------------- + -- UART Types -- + ---------------- + + -- Based on TI AM64x/AM243x Technical Reference Manual, 12.1.5 Universal + -- Asynchronous Receiver/Transmitter. Limited implementation to serve only + -- the needs to this package. + + pragma Warnings (Off, "*not referenced"); + -- Suppress warning for unreferenced enumeration values + + type UART_Config_Mode is + (Configuration_Mode_A, Configuration_Mode_B, Operational_Mode); + + type Enable_Bit is (Disable, Enable); + for Enable_Bit use (Disable => 0, Enable => 1); + + type Holding_Register is record + Data : Character; + end record with Size => 32, Volatile_Full_Access; + + for Holding_Register use record + Data at 0 range 0 .. 7; + end record; + + subtype Baud_Clock_Divisor_Low is Unsigned_32 range 0 .. 2 ** 8 - 1; + subtype Baud_Clock_Divisor_High is Unsigned_32 range 0 .. 2 ** 5 - 1; + + type Baud_Clock_Divisor is record + High : Baud_Clock_Divisor_High; + Low : Baud_Clock_Divisor_Low; + end record with Size => 64; + + for Baud_Clock_Divisor use record + Low at 0 range 0 .. 7; + High at 4 range 0 .. 5; + end record; + + type Interrupt_Enable is record + CTS_Interrupt : Enable_Bit; + RTS_Interrupt : Enable_Bit; + XOFF_Interrupt : Enable_Bit; + Sleep_Mode : Enable_Bit; + Modem_Status_Interrupt : Enable_Bit; + Line_Status_Interrupt : Enable_Bit; + THR_Interrupt : Enable_Bit; + RHR_Interrupt : Enable_Bit; + end record with Size => 32; + + for Interrupt_Enable use record + CTS_Interrupt at 0 range 7 .. 7; + RTS_Interrupt at 0 range 6 .. 6; + XOFF_Interrupt at 0 range 5 .. 5; + Sleep_Mode at 0 range 4 .. 4; + Modem_Status_Interrupt at 0 range 3 .. 3; + Line_Status_Interrupt at 0 range 2 .. 2; + THR_Interrupt at 0 range 1 .. 1; + RHR_Interrupt at 0 range 0 .. 0; + end record; + + type Software_Flow_Control_Bits is mod 2 ** 3; + + type Enhanced_Feature is record + Auto_CTS : Enable_Bit; + Auto_RTS : Enable_Bit; + Special_Char_Dectect : Enable_Bit; + Enhanced_Functions : Enable_Bit; + Software_Flow_Control : Software_Flow_Control_Bits; + end record with Size => 32; + + for Enhanced_Feature use record + Auto_CTS at 0 range 7 .. 7; + Auto_RTS at 0 range 6 .. 6; + Special_Char_Dectect at 0 range 5 .. 5; + Enhanced_Functions at 0 range 4 .. 4; + Software_Flow_Control at 0 range 0 .. 3; + end record; + + type Force_Parity_Format is (Not_Forced, Forced); + for Force_Parity_Format use (Not_Forced => 0, Forced => 1); + + type Parity_Type is (Odd, Even); + for Parity_Type use (Odd => 0, Even => 1); + + type Stop_Bits is (One_Bit, Two_Bits); + for Stop_Bits use (One_Bit => 0, Two_Bits => 1); + + type Word_Lengths is (Five_Bits, Six_Bits, Seven_Bits, Eight_Bits); + for Word_Lengths use + (Five_Bits => 0, Six_Bits => 1, Seven_Bits => 2, Eight_Bits => 3); + + type Line_Control is record + Divisor_Latch : Enable_Bit; + Break_Control_Bit : Enable_Bit; + Parity_Type_2 : Force_Parity_Format; + Parity_Type_1 : Parity_Type; + Parity : Enable_Bit; + Number_Of_Stop_Bits : Stop_Bits; + Word_Length : Word_Lengths; + end record with Size => 32, Volatile_Full_Access; + + for Line_Control use record + Divisor_Latch at 0 range 7 .. 7; + Break_Control_Bit at 0 range 6 .. 6; + Parity_Type_2 at 0 range 5 .. 5; + Parity_Type_1 at 0 range 4 .. 4; + Parity at 0 range 3 .. 3; + Number_Of_Stop_Bits at 0 range 2 .. 2; + Word_Length at 0 range 0 .. 1; + end record; + + type Line_Status_Type is record + TX_Shift_Reg_Empty : Boolean; + TX_FIFO_Empty : Boolean; + RX_FIFO_Has_Data : Boolean; + end record with Size => 32, Volatile_Full_Access; + + for Line_Status_Type use record + TX_Shift_Reg_Empty at 0 range 6 .. 6; + TX_FIFO_Empty at 0 range 5 .. 5; + RX_FIFO_Has_Data at 0 range 0 .. 0; + end record; + + type Module_Mode is + (UART_16x, SIR, UART_16x_Auto_Baud, + UART_13x, MIR, FIR, CIR, Disabled); + + for Module_Mode use + (UART_16x => 0, SIR => 1, UART_16x_Auto_Baud => 2, + UART_13x => 3, MIR => 4, FIR => 5, CIR => 6, Disabled => 7); + + type Mode_Definition_1 is record + Mode_Select : Module_Mode; + end record with Size => 32; + + for Mode_Definition_1 use record + Mode_Select at 0 range 0 .. 2; + end record; + + type Idle_Mode_Kind is + (Force_Idle, No_Idle, Smart_Idle, Smart_Idle_Wake_Up); + + type System_Config_Type is record + Idle_Mode : Idle_Mode_Kind; + Wakeup_Enabled : Boolean; + Software_Reset : Boolean; + Auto_Idle : Boolean; + end record with Size => 32; + + for System_Config_Type use record + Idle_Mode at 0 range 3 .. 4; + Wakeup_Enabled at 0 range 2 .. 2; + Software_Reset at 0 range 1 .. 1; + Auto_Idle at 0 range 0 .. 0; + end record; + + type System_Status_Type is record + Reset_Done : Boolean; + end record with Size => 32; + + for System_Status_Type use record + Reset_Done at 0 range 0 .. 0; + end record; + + pragma Warnings (Off, "*bits of*"); + -- Suppress warning of unused bits in UART_Modules. The unused bits is + -- expected for the UART module as each module is placed at 16#1_0000# + -- offsets. + + type UART_Modules (Mode : UART_Config_Mode := Operational_Mode) is record + Line_Control_Register : Line_Control; + Mode_Definition_1_Register : Mode_Definition_1; + System_Config_Register : System_Config_Type; + System_Status_Register : System_Status_Type; + + case Mode is + when Operational_Mode => + TX_RX_Holding_Register : Holding_Register; + Interrupt_Enable_Register : Interrupt_Enable; + Line_Status_Regsiter : Line_Status_Type; + + when Configuration_Mode_A => + null; + + when Configuration_Mode_B => + Baud_Clock_Divisor_Register : Baud_Clock_Divisor; + Enhanced_Feature_Register : Enhanced_Feature; + end case; + end record with Unchecked_Union, Size => 16#1_0000# * Storage_Unit; + + pragma Warnings (On, "*bits of*"); + + for UART_Modules use record + TX_RX_Holding_Register at 16#0# range 0 .. 31; + Interrupt_Enable_Register at 16#4# range 0 .. 31; + Baud_Clock_Divisor_Register at 16#0# range 0 .. 63; + Enhanced_Feature_Register at 16#8# range 0 .. 31; + Line_Control_Register at 16#C# range 0 .. 31; + Line_Status_Regsiter at 16#14# range 0 .. 31; + Mode_Definition_1_Register at 16#20# range 0 .. 31; + System_Config_Register at 16#54# range 0 .. 31; + System_Status_Register at 16#58# range 0 .. 31; + end record; + + pragma Warnings (On, "*not referenced"); + -- Reenable warning for unreferenced enumeration values + + -------------------- + -- UART Registers -- + -------------------- + + UART : array (UART_ID) of UART_Modules + with Address => UART_Base_Address, Volatile_Components; + -- Access to the UART peripherals + + --------- + -- Get -- + --------- + + function Get return Character is + begin + return UART (IO_Module).TX_RX_Holding_Register.Data; + end Get; + + ---------------- + -- Initialize -- + ---------------- + + procedure Initialize is + + procedure Enter_UART_Mode (Mode : UART_Config_Mode); + + procedure Enter_UART_Mode + (Mode : UART_Config_Mode; + Previous_LCR : out Line_Control); + + --------------------- + -- Enter_UART_Mode -- + --------------------- + + procedure Enter_UART_Mode (Mode : UART_Config_Mode) is + Old_LCR : Line_Control; + begin + Enter_UART_Mode (Mode, Old_LCR); + end Enter_UART_Mode; + + procedure Enter_UART_Mode + (Mode : UART_Config_Mode; + Previous_LCR : out Line_Control) is + begin + Previous_LCR := UART (IO_Module).Line_Control_Register; + case Mode is + when Configuration_Mode_A => + -- Configuration Mode A entered when LCR /= 16#BF# + + UART (IO_Module).Line_Control_Register := + (Divisor_Latch => Enable, + Break_Control_Bit => Disable, + Parity_Type_2 => Not_Forced, + Parity_Type_1 => Odd, + Parity => Disable, + Number_Of_Stop_Bits => One_Bit, + Word_Length => Five_Bits); + + when Configuration_Mode_B => + -- Configuration Mode B entered when LCR == 16#BF# + + UART (IO_Module).Line_Control_Register := + (Divisor_Latch => Enable, + Break_Control_Bit => Disable, + Parity_Type_2 => Not_Forced, + Parity_Type_1 => Odd, + Parity => Disable, + Number_Of_Stop_Bits => One_Bit, + Word_Length => Five_Bits); + + when Operational_Mode => + UART (IO_Module).Line_Control_Register.Divisor_Latch := Disable; + end case; + end Enter_UART_Mode; + + begin + -- Initialize UART module per the UART Programming Guide section in + -- the TI AM64x Technical Reference Manual + + -- Ensure the last character is sent before reseting the UART module + -- so we don't send garbage down the link. + + while not UART (IO_Module).Line_Status_Regsiter.TX_Shift_Reg_Empty loop + null; + end loop; + + -- Disable the module if it is enabled + + UART (IO_Module).Mode_Definition_1_Register := (Mode_Select => Disabled); + + -- Reset UART module + + UART (IO_Module).System_Config_Register.Software_Reset := True; + + loop + exit when UART (IO_Module).System_Status_Register.Reset_Done; + end loop; + + -- Disable module interrupts and sleep mode + + Enter_UART_Mode (Configuration_Mode_B); + UART (IO_Module).Enhanced_Feature_Register.Enhanced_Functions := Enable; + + Enter_UART_Mode (Operational_Mode); + UART (IO_Module).Interrupt_Enable_Register := (others => Disable); + + Enter_UART_Mode (Configuration_Mode_B); + UART (IO_Module).Enhanced_Feature_Register.Enhanced_Functions := Disable; + + -- Set baud rate to 115.2 kbps and enable UART module. For the standard + -- 48 MHz source clock we use the 16x baud multiple and a divider value + -- of 26. The clock divider is set while in Configuration_Mode_B. + + UART (IO_Module).Baud_Clock_Divisor_Register := + (High => 16#00#, Low => 16#1A#); + UART (IO_Module).Mode_Definition_1_Register := (Mode_Select => UART_16x); + + -- Configure Line Control Register with 8 data bits, no parity and 1 + -- stop bit. + + UART (IO_Module).Line_Control_Register := + (Divisor_Latch => Enable, + Break_Control_Bit => Enable, + Parity_Type_2 => Not_Forced, + Parity_Type_1 => Odd, + Parity => Disable, + Number_Of_Stop_Bits => One_Bit, + Word_Length => Eight_Bits); + + Enter_UART_Mode (Operational_Mode); + UART (IO_Module).Line_Control_Register.Break_Control_Bit := Disable; + + Initialized := True; + end Initialize; + + ----------------- + -- Is_Tx_Ready -- + ----------------- + + -- We use TX_FIFO_Empty rather than TX_Shift_Reg_Empty to indicate the + -- transmitter is ready as it allows the CPU to load the next character + -- straight after the previous character has moved to the transmit shift + -- register. + + function Is_Tx_Ready return Boolean is + (UART (IO_Module).Line_Status_Regsiter.TX_FIFO_Empty); + + ----------------- + -- Is_Rx_Ready -- + ----------------- + + function Is_Rx_Ready return Boolean is + (UART (IO_Module).Line_Status_Regsiter.RX_FIFO_Has_Data); + + --------- + -- Put -- + --------- + + procedure Put (C : Character) is + begin + UART (IO_Module).TX_RX_Holding_Register := (Data => C); + end Put; + + ---------------------------- + -- Use_Cr_Lf_For_New_Line -- + ---------------------------- + + function Use_Cr_Lf_For_New_Line return Boolean is + begin + return True; + end Use_Cr_Lf_For_New_Line; +end System.Text_IO; diff --git a/src/s-ti.ads b/src/s-ti.ads new file mode 100644 index 00000000..0dcbf9c3 --- /dev/null +++ b/src/s-ti.ads @@ -0,0 +1,36 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS -- +-- -- +-- S Y S T E M . T I -- +-- -- +-- S p e c -- +-- -- +-- Copyright (C) 2023, AdaCore -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNARL is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- The port of GNARL to bare board targets was initially developed by the -- +-- Real-Time Systems Group at the Technical University of Madrid. -- +-- -- +------------------------------------------------------------------------------ + +package System.TI with Pure is +end System.TI; diff --git a/src/s-tvinma.adb b/src/s-tvinma.adb new file mode 100644 index 00000000..660e08a1 --- /dev/null +++ b/src/s-tvinma.adb @@ -0,0 +1,209 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS -- +-- -- +-- S Y S T E M . T I . V E C T O R E D _ I N T E R R U P T _ M A N A G E R -- +-- -- +-- B o d y -- +-- -- +-- Copyright (C) 2023, AdaCore -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNARL is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- The port of GNARL to bare board targets was initially developed by the -- +-- Real-Time Systems Group at the Technical University of Madrid. -- +-- -- +------------------------------------------------------------------------------ + +with Interfaces.ARM_V7AR; +with System.BB.CPU_Primitives; +with System.Machine_Code; + +package body System.TI.Vectored_Interrupt_Manager is + use System.BB.CPU_Primitives, System.BB.Interrupts; + use Interfaces, Interfaces.ARM_V7AR; + use System.Machine_Code; + + ------------------------ + -- Interrupt Handlers -- + ------------------------ + + procedure IRQ_Handler; + pragma Import (Asm, IRQ_Handler, "__gnat_irq_trap"); + + procedure IRQ_Interrupt_Handler; + pragma Export (C, IRQ_Interrupt_Handler, "__gnat_irq_handler"); + -- Low-level interrupt handler + + procedure FIQ_Interrupt_Handler is null; + pragma Export (C, FIQ_Interrupt_Handler, "__gnat_fiq_handler"); + -- This runtime does not provide a FIQ handler + + ---------------- + -- Initialize -- + ---------------- + + procedure Initialize is + SCTLR : Unsigned_32; + begin + -- Enable the Vector Interrupt Controller (VIC) + + SCTLR := CP15.Get_SCTLR; + SCTLR := SCTLR or (2 ** 24); -- VE bit + CP15.Set_SCTLR (SCTLR); + + -- Reset the interrupt controller to its default state + + Disable_Interrupts; + + for Group in VIM_Interrupt_Group_Register'Range loop + VIM_Interrupt_Group_Register (Group).Interrupt_Disable_Register := + (others => Disable); + VIM_Interrupt_Group_Register (Group).Interrupt_Status_Register := + (others => Active_Clear); + VIM_Interrupt_Group_Register (Group).Interrupt_Map_Register := + (others => IRQ); + VIM_Interrupt_Group_Register (Group).Interrupt_Type_Register := + (others => Level); + end loop; + + -- Acknowledge and clear pending interrupt requests + + declare + Handler : Address with Volatile; + begin + Handler := VIM_IRQ_Vector_Register; + Handler := VIM_FIQ_Vector_Register; + + VIM_IRQ_Vector_Register := Handler; + VIM_FIQ_Vector_Register := Handler; + end; + end Initialize; + + ------------------------------- + -- Install_Interrupt_Handler -- + ------------------------------- + + procedure Install_Interrupt_Handler + (Interrupt : BB.Interrupts.Interrupt_ID; + Prio : Interrupt_Priority) + is + pragma Unreferenced (Prio); + + Group_ID : constant Interrupt_Group := VIM_Group_ID (Interrupt); + -- Register interrupt group the interrupt belongs to + + Sub_ID : constant Interrupt_Group := VIM_Sub_ID (Interrupt); + -- ID of the interrupt within the above group + + Interrupt_Group_Register renames + VIM_Interrupt_Group_Register (Group_ID); + + begin + -- While we could directly have installed a single fixed IRQ handler, + -- this would have required all IRQ go through Ravenscar run time, + -- which is a bit of a limitation for some applications. By using the + -- vector capability of the interrupt handler, it is possible to + -- handle some interrupts directly for best performance. + + VIM_Interrupt_Vector_Register (Interrupt) := IRQ_Handler'Address; + + Interrupt_Group_Register.Interrupt_Map_Register (Sub_ID) := IRQ; + + Interrupt_Group_Register.Interrupt_Enable_Register (Sub_ID) := Enable; + end Install_Interrupt_Handler; + + --------------------------- + -- IRQ_Interrupt_Handler -- + --------------------------- + + procedure IRQ_Interrupt_Handler is + Active_Request : constant VIM_Interrupt_Request := + VIM_Active_IRQ_Register; + + begin + if not Active_Request.Valid then + -- Spurious interrupt + return; + end if; + + declare + Group_ID : constant Interrupt_Group := + VIM_Group_ID (Active_Request.Number); + Sub_ID : constant Interrupt_Group := + VIM_Sub_ID (Active_Request.Number); + + IRQ_Group renames VIM_Interrupt_Group_Register (Group_ID); + + IRQ_Type : constant Interrupt_Type := + IRQ_Group.Interrupt_Type_Register (Sub_ID); + begin + + -- As per TI AM64x TRM 6.2.3.5.8.1 clear the status register before + -- the user clears the interrupt source if the IRQ type is set to + -- pulse. Otherwise, clear after the user handler. + + if IRQ_Type = Pulse then + IRQ_Group.Interrupt_Status_Register (Sub_ID) := Active_Clear; + end if; + + Interrupt_Wrapper (Active_Request.Number); + + if IRQ_Type = Level then + IRQ_Group.Interrupt_Status_Register (Sub_ID) := Active_Clear; + end if; + end; + + -- Clear the priority mask + + VIM_IRQ_Vector_Register := Null_Address; + end IRQ_Interrupt_Handler; + + --------------------------- + -- Priority_Of_Interrupt -- + --------------------------- + + -- Only one interrupt priority level is supported + + function Priority_Of_Interrupt + (Interrupt : System.BB.Interrupts.Interrupt_ID) + return System.Any_Priority is (Interrupt_Priority'Last); + + -------------------------- + -- Set_Current_Priority -- + -------------------------- + + -- Nested interrupts are not supported on this controller so there + -- is nothing to do. + + procedure Set_Current_Priority (Priority : Integer) is + begin + null; + end Set_Current_Priority; + + ---------------- + -- Power_Down -- + ---------------- + + procedure Power_Down is + begin + Asm ("wfi", Volatile => True); + end Power_Down; +end System.TI.Vectored_Interrupt_Manager; diff --git a/src/s-tvinma.ads b/src/s-tvinma.ads new file mode 100644 index 00000000..781c7db0 --- /dev/null +++ b/src/s-tvinma.ads @@ -0,0 +1,191 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME LIBRARY (GNARL) COMPONENTS -- +-- -- +-- S Y S T E M . T I . V E C T O R E D _ I N T E R R U P T _ M A N A G E R -- +-- -- +-- S p e c -- +-- -- +-- Copyright (C) 2023, AdaCore -- +-- -- +-- GNARL is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNARL is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNARL was developed by the GNARL team at Florida State University. -- +-- Extensive contributions were provided by Ada Core Technologies, Inc. -- +-- -- +-- The port of GNARL to bare board targets was initially developed by the -- +-- Real-Time Systems Group at the Technical University of Madrid. -- +-- -- +------------------------------------------------------------------------------ + +-- Provides the low level interface to TI's Vectored Interrupt Manager for the +-- TI Keystone Cortex-R5F. + +with System.BB.Interrupts; +with System.BB.Parameters; + +package System.TI.Vectored_Interrupt_Manager with Preelaborate is + + package Params renames System.BB.Parameters; + package BB_I renames System.BB.Interrupts; + + type VIM_Interrupt_Priority is range 0 .. 15; + + type VIM_Interrupt_Request is record + Valid : Boolean; + Pending_Priority : VIM_Interrupt_Priority; + Number : BB_I.Interrupt_ID; + end record with Size => 32; + + for VIM_Interrupt_Request use record + Valid at 0 range 31 .. 31; + Pending_Priority at 0 range 16 .. 19; + Number at 0 range 0 .. 9; + end record; + + subtype Interrupt_Group is BB.Parameters.Interrupt_Range range 0 .. 31; + + type VIM_Interrupt_Status is (Inactive, Active_Clear); + for VIM_Interrupt_Status use (Inactive => 0, Active_Clear => 1); + + type VIM_Group_Status is array (Interrupt_Group) of + VIM_Interrupt_Status with Pack; + + type VIM_Interrupt_Raw is (Inactive, Active_Set); + for VIM_Interrupt_Raw use (Inactive => 0, Active_Set => 1); + + type VIM_Group_Raw is array (Interrupt_Group) of VIM_Interrupt_Raw + with Pack, Size => 32; + + type Enable_Bit is (Disable, Enable); + for Enable_Bit use (Disable => 0, Enable => 1); + + type VIM_Group_Enable is array (Interrupt_Group) of Enable_Bit + with Pack, Size => 32; + + type Disable_Bit is (Inactive, Disable); + for Disable_Bit use (Inactive => 0, Disable => 1); + + type VIM_Group_Disable is array (Interrupt_Group) of Disable_Bit + with Pack, Size => 32; + + type Interrupt_Kind is (IRQ, FIQ); + for Interrupt_Kind use (IRQ => 0, FIQ => 1); + + type Interrupt_Map_Groups is array (Interrupt_Group) of Interrupt_Kind + with Pack, Size => 32; + + type Interrupt_Type is (Level, Pulse); + for Interrupt_Type use (Level => 0, Pulse => 1); + + type Interrupt_Type_Groups is array (Interrupt_Group) of Interrupt_Type + with Pack, Size => 32; + + type VIM_Priority is record + Priority : VIM_Interrupt_Priority; + end record with Size => 32; + + for VIM_Priority use record + Priority at 0 range 0 .. 3; + end record; + + type VIM_Interrupt_Group is record + Raw_Status_Register : VIM_Group_Raw; + Interrupt_Status_Register : VIM_Group_Status; + Interrupt_Enable_Register : VIM_Group_Enable; + Interrupt_Disable_Register : VIM_Group_Disable; + IRQ_Status_Register : VIM_Group_Status; + FIQ_Status_Register : VIM_Group_Status; + Interrupt_Map_Register : Interrupt_Map_Groups; + Interrupt_Type_Register : Interrupt_Type_Groups; + end record; + + for VIM_Interrupt_Group use record + Raw_Status_Register at 16#00# range 0 .. 31; + Interrupt_Status_Register at 16#04# range 0 .. 31; + Interrupt_Enable_Register at 16#08# range 0 .. 31; + Interrupt_Disable_Register at 16#0C# range 0 .. 31; + IRQ_Status_Register at 16#10# range 0 .. 31; + FIQ_Status_Register at 16#14# range 0 .. 31; + Interrupt_Map_Register at 16#18# range 0 .. 31; + Interrupt_Type_Register at 16#1C# range 0 .. 31; + end record; + + VIM_IRQ_Vector_Register : Address + with Address => System'To_Address (Params.VIM_Base_Address + 16#18#), + Volatile; + + VIM_FIQ_Vector_Register : Address + with Address => System'To_Address (Params.VIM_Base_Address + 16#1C#), + Volatile; + + VIM_Active_IRQ_Register : VIM_Interrupt_Request + with Address => System'To_Address (Params.VIM_Base_Address + 16#20#), + Volatile_Full_Access; + + VIM_Active_FIQ_Register : VIM_Interrupt_Request + with Address => System'To_Address (Params.VIM_Base_Address + 16#24#), + Volatile_Full_Access; + + VIM_Interrupt_Group_Register : array (0 .. 8) of VIM_Interrupt_Group + with Address => System'To_Address (Params.VIM_Base_Address + 16#400#), + Volatile_Components; + + VIM_Priority_Register : array (BB_I.Interrupt_ID) of VIM_Priority + with Address => System'To_Address (Params.VIM_Base_Address + 16#1000#), + Volatile_Components; + + VIM_Interrupt_Vector_Register : array (BB_I.Interrupt_ID) of Address + with Address => System'To_Address (Params.VIM_Base_Address + 16#2000#), + Volatile_Components; + + ---------------------- + -- Helper Functions -- + ---------------------- + + function VIM_Group_ID (Interrupt : BB_I.Interrupt_ID) return Interrupt_Group + is (Interrupt / (Interrupt_Group'Last + 1)); + -- Get the group number for the interrupt + + function VIM_Sub_ID (Interrupt : BB_I.Interrupt_ID) return Interrupt_Group + is (Interrupt mod (Interrupt_Group'Last + 1)); + -- Get the ID of the interrupt within the group + + -------------------- + -- VIM Operations -- + -------------------- + + procedure Initialize; + -- Initialize the VIM + + ---------------------------------------------------------- + -- Implementation of System.BB.Board_Support.Interrupts -- + ---------------------------------------------------------- + + procedure Install_Interrupt_Handler + (Interrupt : System.BB.Interrupts.Interrupt_ID; + Prio : System.Interrupt_Priority); + + function Priority_Of_Interrupt + (Interrupt : System.BB.Interrupts.Interrupt_ID) + return System.Any_Priority; + + procedure Set_Current_Priority (Priority : Integer); + + procedure Power_Down; + +end System.TI.Vectored_Interrupt_Manager; diff --git a/src/system/system-xi-arm-light-tasking-no-irq-nesting.ads b/src/system/system-xi-arm-light-tasking-no-irq-nesting.ads new file mode 100644 index 00000000..f9cc7309 --- /dev/null +++ b/src/system/system-xi-arm-light-tasking-no-irq-nesting.ads @@ -0,0 +1,181 @@ +------------------------------------------------------------------------------ +-- -- +-- GNAT RUN-TIME COMPONENTS -- +-- -- +-- S Y S T E M -- +-- -- +-- S p e c -- +-- (ARM Version) -- +-- -- +-- Copyright (C) 1992-2023, Free Software Foundation, Inc. -- +-- -- +-- This specification is derived from the Ada Reference Manual for use with -- +-- GNAT. The copyright notice above, and the license provisions that follow -- +-- apply solely to the contents of the part following the private keyword. -- +-- -- +-- GNAT is free software; you can redistribute it and/or modify it under -- +-- terms of the GNU General Public License as published by the Free Soft- -- +-- ware Foundation; either version 3, or (at your option) any later ver- -- +-- sion. GNAT is distributed in the hope that it will be useful, but WITH- -- +-- OUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY -- +-- or FITNESS FOR A PARTICULAR PURPOSE. -- +-- -- +-- As a special exception under Section 7 of GPL version 3, you are granted -- +-- additional permissions described in the GCC Runtime Library Exception, -- +-- version 3.1, as published by the Free Software Foundation. -- +-- -- +-- You should have received a copy of the GNU General Public License and -- +-- a copy of the GCC Runtime Library Exception along with this program; -- +-- see the files COPYING3 and COPYING.RUNTIME respectively. If not, see -- +-- . -- +-- -- +-- GNAT was originally developed by the GNAT team at New York University. -- +-- Extensive contributions were provided by Ada Core Technologies Inc. -- +-- -- +------------------------------------------------------------------------------ + +pragma Restrictions (No_Exception_Propagation); +-- Only local exception handling is supported in this profile + +pragma Restrictions (No_Exception_Registration); +-- Disable exception name registration. This capability is not used because +-- it is only required by exception stream attributes which are not supported +-- in this run time. + +pragma Restrictions (No_Implicit_Dynamic_Code); +-- Pointers to nested subprograms are not allowed in this run time, in order +-- to prevent the compiler from building "trampolines". + +pragma Restrictions (No_Finalization); +-- Controlled types are not supported in this run time + +pragma Profile (Jorvik); +-- This is a bare metal tasking runtime + +package System is + pragma Pure; + -- Note that we take advantage of the implementation permission to make + -- this unit Pure instead of Preelaborable; see RM 13.7.1(15). In Ada + -- 2005, this is Pure in any case (AI-362). + + pragma No_Elaboration_Code_All; + -- Allow the use of that restriction in units that WITH this unit + + type Name is (SYSTEM_NAME_GNAT); + System_Name : constant Name := SYSTEM_NAME_GNAT; + + -- System-Dependent Named Numbers + + Min_Int : constant := -2 ** (Standard'Max_Integer_Size - 1); + Max_Int : constant := 2 ** (Standard'Max_Integer_Size - 1) - 1; + + Max_Binary_Modulus : constant := 2 ** Standard'Max_Integer_Size; + Max_Nonbinary_Modulus : constant := 2 ** Integer'Size - 1; + + Max_Base_Digits : constant := Long_Long_Float'Digits; + Max_Digits : constant := Long_Long_Float'Digits; + + Max_Mantissa : constant := Standard'Max_Integer_Size - 1; + Fine_Delta : constant := 2.0 ** (-Max_Mantissa); + + Tick : constant := 0.000_001; + + -- Storage-related Declarations + + type Address is private; + pragma Preelaborable_Initialization (Address); + Null_Address : constant Address; + + Storage_Unit : constant := 8; + Word_Size : constant := Standard'Word_Size; + Memory_Size : constant := 2 ** Word_Size; + + -- Address comparison + + function "<" (Left, Right : Address) return Boolean; + function "<=" (Left, Right : Address) return Boolean; + function ">" (Left, Right : Address) return Boolean; + function ">=" (Left, Right : Address) return Boolean; + function "=" (Left, Right : Address) return Boolean; + + pragma Import (Intrinsic, "<"); + pragma Import (Intrinsic, "<="); + pragma Import (Intrinsic, ">"); + pragma Import (Intrinsic, ">="); + pragma Import (Intrinsic, "="); + + -- Other System-Dependent Declarations + + type Bit_Order is (High_Order_First, Low_Order_First); + Default_Bit_Order : constant Bit_Order := + Bit_Order'Val (Standard'Default_Bit_Order); + pragma Warnings (Off, Default_Bit_Order); -- kill constant condition warning + + -- Priority-related Declarations (RM D.1) + + -- 241 corresponds to IRQ interrupt level + -- 241 is the priority value that block all interrupts + -- 240 is the maximum value of priority that is not high enough to + -- require the blocking of one or more interrupts. + -- + -- The range of priorities is chosen to be similar other targets. + -- The number of interrupt priorities is chosen to match those that can + -- be masked/unmasked directly in the processor. + + Max_Priority : constant Positive := 240; + Max_Interrupt_Priority : constant Positive := 241; + + subtype Any_Priority is Integer range 0 .. 241; + subtype Priority is Any_Priority range 0 .. 240; + subtype Interrupt_Priority is Any_Priority range 241 .. 241; + + Default_Priority : constant Priority := 120; + -- By default, the priority assigned is the one in the middle of the + -- Priority range. + +private + + type Address is mod Memory_Size; + for Address'Size use Standard'Address_Size; + + Null_Address : constant Address := 0; + + -------------------------------------- + -- System Implementation Parameters -- + -------------------------------------- + + -- These parameters provide information about the target that is used + -- by the compiler. They are in the private part of System, where they + -- can be accessed using the special circuitry in the Targparm unit + -- whose source should be consulted for more detailed descriptions + -- of the individual switch values. + + Atomic_Sync_Default : constant Boolean := False; + Backend_Divide_Checks : constant Boolean := False; + Backend_Overflow_Checks : constant Boolean := True; + Command_Line_Args : constant Boolean := False; + Configurable_Run_Time : constant Boolean := True; + Denorm : constant Boolean := True; + Duration_32_Bits : constant Boolean := False; + Exit_Status_Supported : constant Boolean := False; + Fractional_Fixed_Ops : constant Boolean := False; + Frontend_Layout : constant Boolean := False; + Machine_Overflows : constant Boolean := False; + Machine_Rounds : constant Boolean := True; + Preallocated_Stacks : constant Boolean := True; + Signed_Zeros : constant Boolean := True; + Stack_Check_Default : constant Boolean := False; + Stack_Check_Probes : constant Boolean := False; + Stack_Check_Limits : constant Boolean := False; + Support_Aggregates : constant Boolean := True; + Support_Atomic_Primitives : constant Boolean := True; + Support_Composite_Assign : constant Boolean := True; + Support_Composite_Compare : constant Boolean := True; + Support_Long_Shifts : constant Boolean := True; + Always_Compatible_Rep : constant Boolean := True; + Suppress_Standard_Library : constant Boolean := True; + Use_Ada_Main_Program_Name : constant Boolean := False; + Frontend_Exceptions : constant Boolean := False; + ZCX_By_Default : constant Boolean := True; + +end System;