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AWS FPGA HDK is the official kit for developing an Amazon FPGA Image (AFI) which can be loaded on FPGAs in FPGA-enabled EC2 instances (i.e. F1 Instance).
Check out the release notes for information about the latest bug fixes, updates, and features added to the HDK.
The AWS FPGA HDK includes all the design files and scripts required to generate an Amazon FPGA Image (AFI). Developers can download the HDK and use it in their preferred design environment. AWS offers the FPGA Developer AMI on the AWS Marketplace with the required tools to develop, simulate, and build an AFI.
NOTE: The HDK is developed and tested in a Linux environment only
The documents directory provides the specification for the AWS Shell (SH) to Custom Logic (CL) interface, and best practices for CL design and development.
The common directory includes scripts, timing constraints and compile settings required during the AFI generation process. Developers should not change these files.
The Custom Logic (cl) directory is where the Custom Logic is expected to be developed. It includes a number of examples under the examples directory, as well as a placeholder for the developer's own Custom Logic under developer_designs directory.
The HDK also includes test benches for each provided example, and instructions on how to run RTL-level simulations.
To get started, the developer needs to have a development environment with Xilinx Vivado tools installed. An easy way to get this by using the AWS FPGA Developer AMI and following the instructions inside the README.md of that AMI.
Please refer to the release notes for the exact version of Vivado tools, and the required license components.
The AWS FPGA HDK can be cloned to your EC2 instance or server by executing:
$ git clone https://github.com/aws/aws-fpga
$ cd aws-fpga
$ source hdk_setup.sh
The Getting started with CL examples walks you through how to build, register, and use an AFI. The Hello World readme provides the steps to build an AFI from the provided Hello World example CL, and how to load it on an F1 instance. Other examples are available in the examples directory, each with its own README.md file.
The start your own CL design will guide you on how to setup your own CL project environment.
You can use Vivado XSIM simulator, or bring your own simulator (like Synopsys', Mentor's, or Cadence). Follow the verification environment setup to run these simulations
You can follow the build scripts readme for step-by-step instructions on how to setup the scripts and run the build process. This checklist should be consulted before you start the build process.
The current release of the HDK does not include DMA. Upcoming releases will include both Xilinx's XDMA and AWS EDMA in the HDK and their respective drivers in the SDK.
The current release of the HDK does not include OpenCL support.
The current release of the HDK does not include SDAccel support.
The HDK does not currently support chipscope debug, but this will be enabled in upcoming HDK/SDK releases.
The HDK supports dynamic partial reconfiguration (PR) of the Custom Logic. Each AFI is actually a partial bitstream, and AFI's can be swapped during operation. Using FPGA Management Tools provided by the SDK, the users can load/unload AFIs from within the instance. NOTE: Users can only load/unload AFI-id(s) that have been associated a priori to the instance-id or the AMI-id
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AWS FPGA HDK is the official kit for developing an Amazon FPGA Image (AFI) which can be loaded on FPGAs in FPGA-enabled EC2 instances (i.e. F1 Instance).
Check out the release notes for information about the latest bug fixes, updates, and features added to the HDK.
The AWS FPGA HDK includes all the design files and scripts required to generate an Amazon FPGA Image (AFI). Developers can download the HDK and use it in their preferred design environment. AWS offers the FPGA Developer AMI on the AWS Marketplace with the required tools to develop, simulate, and build an AFI.
NOTE: The HDK is developed and tested in a Linux environment only
The documents directory provides the specification for the AWS Shell (SH) to Custom Logic (CL) interface, and best practices for CL design and development.
The common directory includes scripts, timing constraints and compile settings required during the AFI generation process. Developers should not change these files.
The Custom Logic (cl) directory is where the Custom Logic is expected to be developed. It includes a number of examples under the examples directory, as well as a placeholder for the developer's own Custom Logic under developer_designs directory.
The HDK also includes test benches for each provided example, and instructions on how to run RTL-level simulations.
To get started, the developer needs to have a development environment with Xilinx Vivado tools installed. An easy way to get this by using the AWS FPGA Developer AMI and following the instructions inside the README.md of that AMI.
Please refer to the release notes for the exact version of Vivado tools, and the required license components.
The AWS FPGA HDK can be cloned to your EC2 instance or server by executing:
$ git clone https://github.com/aws/aws-fpga
$ cd aws-fpga
$ source hdk_setup.sh
The Getting started with CL examples walks you through how to build, register, and use an AFI. The Hello World readme provides the steps to build an AFI from the provided Hello World example CL, and how to load it on an F1 instance. Other examples are available in the examples directory, each with its own README.md file.
The start your own CL design will guide you on how to setup your own CL project environment.
You can use Vivado XSIM simulator, or bring your own simulator (like Synopsys', Mentor's, or Cadence). Follow the verification environment setup to run these simulations
You can follow the build scripts readme for step-by-step instructions on how to setup the scripts and run the build process. This checklist should be consulted before you start the build process.
The current release of the HDK does not include DMA. Upcoming releases will include both Xilinx's XDMA and AWS EDMA in the HDK and their respective drivers in the SDK.
The current release of the HDK does not include OpenCL support.
The current release of the HDK does not include SDAccel support.
The HDK does not currently support chipscope debug, but this will be enabled in upcoming HDK/SDK releases.
The HDK supports dynamic partial reconfiguration (PR) of the Custom Logic. Each AFI is actually a partial bitstream, and AFI's can be swapped during operation. Using FPGA Management Tools provided by the SDK, the users can load/unload AFIs from within the instance. NOTE: Users can only load/unload AFI-id(s) that have been associated a priori to the instance-id or the AMI-id
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