diff --git a/CMakeLists.txt b/CMakeLists.txt new file mode 100644 index 00000000..225026e6 --- /dev/null +++ b/CMakeLists.txt @@ -0,0 +1,106 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +# Set the minimum required version of CMake for the project +cmake_minimum_required(VERSION 3.17) + +project(sbsa-acs LANGUAGES) + +# cmake_policy +cmake_policy(SET CMP0001 NEW) + +### Tool dependency check - end ### + +get_filename_component(ROOT_DIR . ABSOLUTE) + +# Set internal build directory variable +set(BUILD ${CMAKE_CURRENT_BINARY_DIR} CACHE INTERNAL "Setting build directory to ${BUILD}" FORCE) +file(MAKE_DIRECTORY ${BUILD}/output/) + +# Set global compile list variable +set(COMPILE_LIST "") + +#### Include cmake support module ### +include(${ROOT_DIR}/tools/cmake/toolchain/utils.cmake) +include(${ROOT_DIR}/tools/cmake/toolchain/default.cmake) +#### + + +### Valid value range for command line argument ### + +list(APPEND ARM_ARCH_MAJOR_LIST 8 9) + +### + +# Check for valid targets +_get_sub_dir_list(TARGET_LIST ${ROOT_DIR}/platform/pal_baremetal/) +if(NOT DEFINED TARGET) + set(TARGET ${TARGET_DFLT} CACHE INTERNAL "Defaulting target to ${TARGET}" FORCE) +else() + set(TARGET ${TARGET} CACHE INTERNAL "TARGET is set to ${TARGET}" FORCE) +endif() + +if(NOT ${TARGET} IN_LIST TARGET_LIST) + message(FATAL_ERROR "[ACS] : Error: Unspported value for -DTARGET=, supported targets are : ${TARGET_LIST}") +else() + message(STATUS "[ACS] : TARGET is set to ${TARGET}") +endif() + +# Check for ARM_ARCH_MAJOR +if(NOT DEFINED ARM_ARCH_MAJOR) + set(ARM_ARCH_MAJOR "${ARM_ARCH_MAJOR_DFLT}" CACHE INTERNAL "Default ARM_ARCH_MAJOR value" FORCE) + message(STATUS "[ACS] : Defaulting ARM_ARCH_MAJOR to ${ARM_ARCH_MAJOR}") +else() + if(NOT ${ARM_ARCH_MAJOR} IN_LIST ARM_ARCH_MAJOR_LIST) + message(FATAL_ERROR "[ACS] : Error: Unspported value for -DARM_ARCH_MAJOR=, supported values are : ${ARM_ARCH_MAJOR_LIST}") + endif() + message(STATUS "[ACS] : ARM_ARCH_MAJOR is set to ${ARM_ARCH_MAJOR}") +endif() + +# Check for ARM_ARCH_MINOR +if(NOT DEFINED ARM_ARCH_MINOR) + set(ARM_ARCH_MINOR "${ARM_ARCH_MINOR_DFLT}" CACHE INTERNAL "Default ARM_ARCH_MINOR value" FORCE) + message(STATUS "[ACS] : Defaulting ARM_ARCH_MINOR to ${ARM_ARCH_MINOR}") +else() + message(STATUS "[ACS] : ARM_ARCH_MINOR is set to ${ARM_ARCH_MINOR}") +endif() + +# Setup toolchain parameters for compilation and link +include(${ROOT_DIR}/tools/cmake/toolchain/common.cmake) + + +### Cmake clean target ### +list(APPEND CLEAN_LIST + ${CMAKE_CURRENT_BINARY_DIR}/${OUTPUT_HEADER} + ${CMAKE_CURRENT_BINARY_DIR}/output +) + +# Include the files for make clean +foreach(clean_item ${CLEAN_LIST}) + set_property(DIRECTORY APPEND PROPERTY ADDITIONAL_MAKE_CLEAN_FILES ${clean_item}) +endforeach() +### + +add_subdirectory(${ROOT_DIR}/tools/cmake/acs_host) + +### Throw waring for the files which is not compiled ### + +list(REMOVE_DUPLICATES COMPILE_LIST) +execute_process(COMMAND python ${ROOT_DIR}/tools/scripts/compile_check.py "${COMPILE_LIST}" "${ROOT_DIR}" "${TARGET}" OUTPUT_VARIABLE NOT_COMPILED_FILES) +if(NOT ${NOT_COMPILED_FILES} MATCHES NULL) + message(WARNING "Following files are not compiled ${NOT_COMPILED_FILES}") +endif() diff --git a/Makefile b/Makefile deleted file mode 100644 index 2e753f58..00000000 --- a/Makefile +++ /dev/null @@ -1,66 +0,0 @@ -## @file - # Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. - # SPDX-License-Identifier : Apache-2.0 - # - # Licensed under the Apache License, Version 2.0 (the "License"); - # you may not use this file except in compliance with the License. - # You may obtain a copy of the License at - # - # http://www.apache.org/licenses/LICENSE-2.0 - # - # Unless required by applicable law or agreed to in writing, software - # distributed under the License is distributed on an "AS IS" BASIS, - # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - # See the License for the specific language governing permissions and - # limitations under the License. - ## - -default: all - -SBSA_ROOT:= $(SBSA_PATH) -SBSA_DIR := $(SBSA_ROOT)/baremetal_app/ - -CFLAGS += -I$(SBSA_ROOT)/ -CFLAGS += -I$(SBSA_ROOT)/baremetal_app - -OUT_DIR = $(SBSA_ROOT)/build -OBJ_DIR := $(SBSA_ROOT)/build/obj -LIB_DIR := $(SBSA_ROOT)/build/lib -FILES += $(foreach files,$(SBSA_DIR),$(wildcard $(files)/*.c)) -FILE = `find $(FILES) -type f -exec sh -c 'echo {} $$(basename {})' \; | sort -u --stable -k2,2 | awk '{print $$1}'` -FILE_1 := $(shell echo $(FILE)) -XYZ := $(foreach a,$(FILE_1),$(info $(a))) -PAL_OBJS :=$(addprefix $(OBJ_DIR)/,$(addsuffix .o, $(basename $(notdir $(foreach dirz,$(FILE_1),$(dirz)))))) - -CC = $(GCC49_AARCH64_PREFIX)gcc -march=armv8.2-a -DTARGET_EMULATION -AR = $(GCC49_AARCH64_PREFIX)ar - -compile: - make -f $(SBSA_ROOT)/platform/pal_baremetal.mk all - make -f $(SBSA_ROOT)/val/val.mk all - make -f $(SBSA_ROOT)/test_pool/test_pool.mk all - -create_dirs: - rm -rf ${OBJ_DIR} - rm -rf ${LIB_DIR} - rm -rf ${OUT_DIR} - @mkdir ${OUT_DIR} - @mkdir ${OBJ_DIR} - @mkdir ${LIB_DIR} - -$(OBJ_DIR)/%.o: $(SBSA_DIR)/%.c - $(CC) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(LIB_DIR)/lib_sbsa.a: $(PAL_OBJS) - $(AR) $(ARFLAGS) $@ $^ >> $(OUT_DIR)/link.log 2>&1 - -PAL_LIB: $(LIB_DIR)/lib_sbsa.a - -clean: - rm -rf ${OBJ_DIR} - rm -rf ${LIB_DIR} - rm -rf ${OUT_DIR} - -all: create_dirs compile PAL_LIB - -.PHONY: all PAL_LIB diff --git a/baremetal_app/SbsaAvs.h b/baremetal_app/SbsaAvs.h index 974fd2d4..9774ab40 100644 --- a/baremetal_app/SbsaAvs.h +++ b/baremetal_app/SbsaAvs.h @@ -18,18 +18,65 @@ #ifndef __SBSA_AVS_LEVEL_H__ #define __SBSA_AVS_LEVEL_H__ - #define SIZE_4K 0x100 +#include "platform_image_def.h" +#include "platform_override_fvp.h" - #define SBSA_ACS_MAJOR_VER 7 - #define SBSA_ACS_MINOR_VER 1 - #define SBSA_ACS_SUBMINOR_VER 3 +#define SBSA_ACS_MAJOR_VER 7 +#define SBSA_ACS_MINOR_VER 1 +#define SBSA_ACS_SUBMINOR_VER 3 - #define SBSA_MIN_LEVEL_SUPPORTED 3 - #define SBSA_MAX_LEVEL_SUPPORTED 7 +#define SIZE_4K 0x1000 - #ifdef _AARCH64_BUILD_ +#define SBSA_MIN_LEVEL_SUPPORTED 3 +#define SBSA_MAX_LEVEL_SUPPORTED 7 + +#define INVALID_MPIDR 0xffffffff + +#define STACK_SIZE 0x1000 + +#define VAL_TG0_4K 0x0 +#define VAL_TG0_64K 0x1 +#define VAL_TG0_16K 0x2 +#define PAGE_SIZE_4K 0x1000 +#define PAGE_SIZE_16K (4 * 0x1000) +#define PAGE_SIZE_64K (16 * 0x1000) +#define PAGE_BITS_4K 12 +#define PAGE_BITS_16K 14 +#define PAGE_BITS_64K 16 + +#define PLATFORM_CPU_COUNT PLATFORM_OVERRIDE_PE_CNT + +#if (PLATFORM_PAGE_SIZE == PAGE_SIZE_4K) + #define PAGE_ALIGNMENT PAGE_SIZE_4K + #define PAGE_SIZE PAGE_SIZE_4K + #define TCR_TG0 VAL_TG0_4K +#elif (PLATFORM_PAGE_SIZE == PAGE_SIZE_16K) + #define PAGE_ALIGNMENT PAGE_SIZE_16K + #define PAGE_SIZE PAGE_SIZE_16K + #define TCR_TG0 VAL_TG0_16K +#elif (PLATFORM_PAGE_SIZE == PAGE_SIZE_64K) + #define PAGE_ALIGNMENT PAGE_SIZE_64K + #define PAGE_SIZE PAGE_SIZE_64K + #define TCR_TG0 VAL_TG0_64K +#else + #error "Undefined value for PLATFORM_PAGE_SIZE" +#endif + +/******************************************************************************* + * Used to align variables on the biggest cache line size in the platform. + * This is known only to the platform as it might have a combination of + * integrated and external caches. + ******************************************************************************/ +#define CACHE_WRITEBACK_SHIFT 6 +#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) + +#ifdef _AARCH64_BUILD_ unsigned long __stack_chk_guard = 0xBAAAAAAD; unsigned long __stack_chk_fail = 0xBAAFAAAD; - #endif - #endif + +#define SCTLR_I_BIT (1 << 12) +#define SCTLR_M_BIT (1 << 0) +#define DISABLE_MMU_BIT (0xFFFFFFFFFFFFFFFE) + +#endif /* __SBSA_AVS_LEVEL_H__ */ diff --git a/baremetal_app/SbsaAvsMain.c b/baremetal_app/SbsaAvsMain.c index 0ccfddc3..2eb598d5 100644 --- a/baremetal_app/SbsaAvsMain.c +++ b/baremetal_app/SbsaAvsMain.c @@ -20,7 +20,6 @@ #include "val/include/sbsa_avs_val.h" #include "val/include/sbsa_avs_memory.h" -#include "platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h" #include "SbsaAvs.h" uint32_t g_sbsa_level; @@ -40,6 +39,13 @@ uint32_t *g_skip_test_num; uint32_t *g_execute_tests; uint32_t *g_execute_modules; +extern uint32_t g_skip_array[]; +extern uint32_t g_num_skip; +extern uint32_t g_test_array[]; +extern uint32_t g_num_tests; +extern uint32_t g_module_array[]; +extern uint32_t g_num_modules; + uint32_t createPeInfoTable( ) @@ -244,9 +250,19 @@ createInfoTable( } void -freeSbsaAvsMem() +createRas2InfoTable( +) { + uint64_t ras2_size = sizeof(RAS2_INFO_TABLE) + + PLATFORM_OVERRIDE_NUM_RAS2_BLOCK * sizeof(RAS2_BLOCK) + + PLATFORM_OVERRIDE_NUM_RAS2_MEM_BLOCK * sizeof(RAS2_MEM_INFO); + createInfoTable(val_ras2_create_info_table, ras2_size, "RAS2"); + +} +void +freeSbsaAvsMem() +{ val_pe_free_info_table(); val_gic_free_info_table(); val_timer_free_info_table(); @@ -279,15 +295,6 @@ ShellAppMainsbsa( uint32_t Status; void *branch_label; - g_skip_test_num = &g_skip_array[0]; - if (g_num_tests) { - g_execute_tests = &g_test_array[0]; - } - - if (g_num_modules) { - g_execute_modules = &g_module_array[0]; - } - g_print_level = PLATFORM_OVERRIDE_PRINT_LEVEL; if (g_print_level < AVS_PRINT_INFO) { @@ -300,6 +307,16 @@ ShellAppMainsbsa( g_print_level = AVS_PRINT_ERR; } +#ifdef TARGET_BM_BOOT + /* Write page tables */ + if (val_setup_mmu()) + return AVS_STATUS_FAIL; + + /* Enable Stage-1 MMU */ + if (val_enable_mmu()) + return AVS_STATUS_FAIL; +#endif + g_sbsa_level = PLATFORM_OVERRIDE_SBSA_LEVEL; if (g_sbsa_level < SBSA_MIN_LEVEL_SUPPORTED) { @@ -312,6 +329,25 @@ ShellAppMainsbsa( g_sbsa_level = SBSA_MAX_LEVEL_SUPPORTED; } + val_print(AVS_PRINT_TEST, "\n\n SBSA Architecture Compliance Suite \n", 0); + val_print(AVS_PRINT_TEST, " Version %d.", SBSA_ACS_MAJOR_VER); + val_print(AVS_PRINT_TEST, "%d.", SBSA_ACS_MINOR_VER); + val_print(AVS_PRINT_TEST, "%d \n", SBSA_ACS_SUBMINOR_VER); + + val_print(AVS_PRINT_TEST, "\n Starting tests for level %2d", g_sbsa_level); + val_print(AVS_PRINT_TEST, " (Print level is %2d)\n\n", g_print_level); + + val_print(AVS_PRINT_TEST, " Creating Platform Information Tables \n", 0); + + g_skip_test_num = &g_skip_array[0]; + if (g_num_tests) { + g_execute_tests = &g_test_array[0]; + } + + if (g_num_modules) { + g_execute_modules = &g_module_array[0]; + } + g_execute_nist = FALSE; g_print_mmio = FALSE; g_wakeup_timeout = PLATFORM_OVERRIDE_TIMEOUT; @@ -323,16 +359,6 @@ ShellAppMainsbsa( g_sbsa_tests_pass = 0; g_sbsa_tests_fail = 0; - val_print(AVS_PRINT_TEST, "\n\n SBSA Architecture Compliance Suite \n", 0); - val_print(AVS_PRINT_TEST, " Version %d.", SBSA_ACS_MAJOR_VER); - val_print(AVS_PRINT_TEST, "%d.", SBSA_ACS_MINOR_VER); - val_print(AVS_PRINT_TEST, "%d \n", SBSA_ACS_SUBMINOR_VER); - - val_print(AVS_PRINT_TEST, "\n Starting tests for level %2d", g_sbsa_level); - val_print(AVS_PRINT_TEST, " (Print level is %2d)\n\n", g_print_level); - - val_print(AVS_PRINT_TEST, " Creating Platform Information Tables \n", 0); - Status = createPeInfoTable(); if (Status) return Status; @@ -342,6 +368,7 @@ ShellAppMainsbsa( return Status; createTimerInfoTable(); + createWatchdogInfoTable(); createCacheInfoTable(); @@ -352,16 +379,16 @@ ShellAppMainsbsa( createSratInfoTable(); - uint64_t ras2_size = sizeof(RAS2_INFO_TABLE) - + PLATFORM_OVERRIDE_NUM_RAS2_BLOCK * sizeof(RAS2_BLOCK) - + PLATFORM_OVERRIDE_NUM_RAS2_MEM_BLOCK * sizeof(RAS2_MEM_INFO); - createInfoTable(val_ras2_create_info_table, ras2_size, "RAS2"); - createPcieVirtInfoTable(); + createPeripheralInfoTable(); + createPmuInfoTable(); + createRasInfoTable(); + createRas2InfoTable(); + val_allocate_shared_mem(); /* Initialise exception vector, so any unexpected exception gets handled @@ -421,6 +448,6 @@ ShellAppMainsbsa( val_pe_context_restore(AA64WriteSp(g_stack_pointer)); - + while (1); return 0; } diff --git a/platform/pal_baremetal.mk b/platform/pal_baremetal.mk deleted file mode 100644 index 0092ccd1..00000000 --- a/platform/pal_baremetal.mk +++ /dev/null @@ -1,90 +0,0 @@ -## @file - # Copyright (c) 2022-2023, Arm Limited or its affiliates. All rights reserved. - # SPDX-License-Identifier : Apache-2.0 - # - # Licensed under the Apache License, Version 2.0 (the "License"); - # you may not use this file except in compliance with the License. - # You may obtain a copy of the License at - # - # http://www.apache.org/licenses/LICENSE-2.0 - # - # Unless required by applicable law or agreed to in writing, software - # distributed under the License is distributed on an "AS IS" BASIS, - # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - # See the License for the specific language governing permissions and - # limitations under the License. - ## - -SBSA_ROOT:= $(SBSA_PATH) -SBSA_DIR := $(SBSA_ROOT)/platform/pal_baremetal/src/ -SBSA_A64_DIR := $(SBSA_ROOT)/platform/pal_baremetal/src/AArch64/ -FVP_DIR := $(SBSA_ROOT)/platform/pal_baremetal/FVP/RDN2/src/ - -CFLAGS += -I$(SBSA_ROOT)/ -CFLAGS += -I$(SBSA_ROOT)/val/include/ -CFLAGS += -I$(SBSA_ROOT)/platform/pal_baremetal/ -CFLAGS += -I$(SBSA_ROOT)/platform/pal_baremetal/FVP/RDN2/ -CFLAGS += -I$(SBSA_ROOT)/platform/pal_baremetal/FVP/RDN2/include/ -ASFLAGS += -I$(SBSA_ROOT)/platform/pal_baremetal/src/AArch64/ - -OUT_DIR = $(SBSA_ROOT)/build/ -OBJ_DIR := $(SBSA_ROOT)/build/obj -LIB_DIR := $(SBSA_ROOT)/build/lib - -CC = $(GCC49_AARCH64_PREFIX)gcc -march=armv8.2-a -DTARGET_EMULATION -AR = $(GCC49_AARCH64_PREFIX)ar -CC_FLAGS = -g -Os -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wextra -Wmissing-declarations -Wstrict-prototypes -Wconversion -Wsign-conversion -Wstrict-overflow - -DEPS = $(SBSA_ROOT)/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h -DEPS += $(SBSA_ROOT)/val/include/pal_interface.h - -FILES += $(foreach files,$(SBSA_DIR)/,$(wildcard $(files)/*.S)) -FILES += $(foreach files,$(SBSA_DIR)/,$(wildcard $(files)/*.c)) -FILES += $(foreach files,$(SBSA_A64_DIR),$(wildcard $(files)/*.S)) -FILES += $(foreach files,$(FVP_DIR)/,$(wildcard $(files)/*.S)) -FILES += $(foreach files,$(FVP_DIR)/,$(wildcard $(files)/*.c)) - -FILE = `find $(FILES) -type f -exec sh -c 'echo {} $$(basename {})' \; | sort -u --stable -k2,2 | awk '{print $$1}'` -FILE_1 := $(shell echo $(FILE)) -PAL_OBJS +=$(addprefix $(OBJ_DIR)/,$(addsuffix .o, $(basename $(notdir $(foreach dirz,$(FILE_1),$(dirz)))))) - -all: PAL_LIB - echo $(PAL_OBJS) - -create_dirs: - rm -rf ${OBJ_DIR} - rm -rf ${LIB_DIR} - rm -rf ${OUT_DIR} - @mkdir ${OUT_DIR} - @mkdir ${OBJ_DIR} - @mkdir ${LIB_DIR} - -$(OBJ_DIR)/%.o: $(DEPS) - $(CC) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_A64_DIR)/%.S - $(CC) $(CFLAGS) $(ASFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_DIR)/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_DIR)/%.S - $(CC) $(CFLAGS) $(ASFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(FVP_DIR)/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_DIR)/AArch64/%.S - $(CC) $(CFLAGS) $(ASFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(LIB_DIR)/lib_pal.a: $(PAL_OBJS) - $(AR) $(ARFLAGS) $@ $^ >> $(OUT_DIR)/link.log 2>&1 - -PAL_LIB: $(LIB_DIR)/lib_pal.a -clean: - rm -rf ${OBJ_DIR} - rm -rf ${LIB_DIR} - rm -rf ${OUT_DIR} - -.PHONY: all PAL_LIB - diff --git a/platform/pal_baremetal/FVP/RDN1/include/platform_override_fvp.h b/platform/pal_baremetal/FVP/RDN1/include/platform_override_fvp.h deleted file mode 100644 index 462ff27d..00000000 --- a/platform/pal_baremetal/FVP/RDN1/include/platform_override_fvp.h +++ /dev/null @@ -1,635 +0,0 @@ -/** @file - * Copyright (c) 2020-2022, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - -#include -#include - -/** Begin config **/ - -/* Settings */ -#define PLATFORM_OVERRIDE_SBSA_LEVEL 0x4 //The permissible levels are 3,4,5 and 6 -#define PLATFORM_OVERRIDE_PRINT_LEVEL 0x3 //The permissible levels are 1,2,3,4 and 5 - -/* PCIe BAR config parameters*/ -#define PLATFORM_OVERRIDE_PCIE_BAR64_VAL 0x500000000 -#define PLATFORM_OVERRIDE_PCIE_BAR32NP_VAL 0x70200000 -#define PLATFORM_OVERRIDE_PCIE_BAR32P_VAL 0x70000000 - -/* PE platform config paramaters */ -#define PLATFORM_OVERRIDE_PE_CNT 0x8 -#define PLATFORM_OVERRIDE_PE0_INDEX 0x0 -#define PLATFORM_OVERRIDE_PE0_MPIDR 0x0 -#define PLATFORM_OVERRIDE_PE0_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE1_INDEX 0x1 -#define PLATFORM_OVERRIDE_PE1_MPIDR 0x100 -#define PLATFORM_OVERRIDE_PE1_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE2_INDEX 0x2 -#define PLATFORM_OVERRIDE_PE2_MPIDR 0x200 -#define PLATFORM_OVERRIDE_PE2_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE3_INDEX 0x3 -#define PLATFORM_OVERRIDE_PE3_MPIDR 0x300 -#define PLATFORM_OVERRIDE_PE3_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE4_INDEX 0x4 -#define PLATFORM_OVERRIDE_PE4_MPIDR 0x10000 -#define PLATFORM_OVERRIDE_PE4_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE5_INDEX 0x5 -#define PLATFORM_OVERRIDE_PE5_MPIDR 0x10100 -#define PLATFORM_OVERRIDE_PE5_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE6_INDEX 0x6 -#define PLATFORM_OVERRIDE_PE6_MPIDR 0x10200 -#define PLATFORM_OVERRIDE_PE6_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE7_INDEX 0x7 -#define PLATFORM_OVERRIDE_PE7_MPIDR 0x10300 -#define PLATFORM_OVERRIDE_PE7_PMU_GSIV 0x17 - -/* GIC platform config parameters*/ -#define PLATFORM_OVERRIDE_GIC_VERSION 0x3 -#define PLATFORM_OVERRIDE_CORE_COUNT 0x4 -#define PLATFORM_OVERRIDE_CLUSTER_COUNT 0x2 -#define PLATFORM_OVERRIDE_GICC_COUNT (PLATFORM_OVERRIDE_CORE_COUNT * PLATFORM_OVERRIDE_CLUSTER_COUNT) -#define PLATFORM_OVERRIDE_GICD_COUNT 0x1 -#define PLATFORM_OVERRIDE_GICRD_COUNT 0x1 -#define PLATFORM_OVERRIDE_GICITS_COUNT 0x1 -#define PLATFORM_OVERRIDE_GICH_COUNT 0x1 -#define PLATFORM_OVERRIDE_GICMSIFRAME_COUNT 0x0 -#define PLATFORM_OVERRIDE_GICC_TYPE 0x1000 -#define PLATFORM_OVERRIDE_GICD_TYPE 0x1001 -#define PLATFORM_OVERRIDE_GICC_GICRD_TYPE 0x1002 -#define PLATFORM_OVERRIDE_GICR_GICRD_TYPE 0x1003 -#define PLATFORM_OVERRIDE_GICITS_TYPE 0x1004 -#define PLATFORM_OVERRIDE_GICMSIFRAME_TYPE 0x1005 -#define PLATFORM_OVERRIDE_GICH_TYPE 0x1006 -#define PLATFORM_OVERRIDE_GICC_BASE 0x30000000 -#define PLATFORM_OVERRIDE_GICD_BASE 0x30000000 -#define PLATFORM_OVERRIDE_GICRD_BASE 0x300C0000 -#define PLATFORM_OVERRIDE_GICITS_BASE 0x30040000 -#define PLATFORM_OVERRIDE_GICH_BASE 0x2C010000 -#define PLATFORM_OVERRIDE_GICITS_ID 0 -#define PLATFORM_OVERRIDE_GICIRD_LENGTH (0x20000*8) - -/* - *Secure EL1 timer Flags, Non-Secure EL1 timer Flags, EL2 timer Flags, - *and Virtual timer Flags all can have the same definition as follows. - */ -#define INTERRUPT_IS_LEVEL_TRIGGERED 0x0 -#define INTERRUPT_IS_EDGE_TRIGGERED 0x1 -#define INTERRUPT_IS_ACTIVE_HIGH 0x0 -#define INTERRUPT_IS_ACTIVE_LOW 0x1 - -#define TIMER_MODE INTERRUPT_IS_LEVEL_TRIGGERED -#define TIMER_POLARITY INTERRUPT_IS_ACTIVE_LOW - -#define TIMER_IS_SECURE 0x1 - -#define TIMER_IS_ALWAYS_ON_CAPABLE 0x1 - -/* Timer platform config parameters */ -#define PLATFORM_OVERRIDE_S_EL1_TIMER_FLAGS ((TIMER_POLARITY << 1) | (TIMER_MODE << 0)) -#define PLATFORM_OVERRIDE_NS_EL1_TIMER_FLAGS ((TIMER_POLARITY << 1) | (TIMER_MODE << 0)) -#define PLATFORM_OVERRIDE_NS_EL2_TIMER_FLAGS ((TIMER_POLARITY << 1) | (TIMER_MODE << 0)) -#define PLATFORM_OVERRIDE_VIRTUAL_TIMER_FLAGS ((TIMER_POLARITY << 1) | (TIMER_MODE << 0)) -#define PLATFORM_OVERRIDE_S_EL1_TIMER_GSIV 0x1D -#define PLATFORM_OVERRIDE_NS_EL1_TIMER_GSIV 0x1E -#define PLATFORM_OVERRIDE_NS_EL2_TIMER_GSIV 0x1A -#define PLATFORM_OVERRIDE_VIRTUAL_TIMER_GSIV 0x1B -#define PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV 28 -#define PLATFORM_OVERRIDE_PLATFORM_TIMER_COUNT 0x2 - -#define PLATFORM_OVERRIDE_SYS_TIMER_TYPE 0x2001 -#define PLATFORM_OVERRIDE_TIMER_TYPE PLATFORM_OVERRIDE_SYS_TIMER_TYPE -#define PLATFORM_OVERRIDE_TIMER_COUNT 0x2 -#define PLATFORM_OVERRIDE_TIMER_CNTCTL_BASE 0x2a810000 - -#define PLATFORM_OVERRIDE_TIMER_CNTBASE_0 0x2a830000 -#define PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_0 0xFFFFFFFFFFFFFFFF -#define PLATFORM_OVERRIDE_TIMER_GSIV_0 0x5c -#define PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_0 0x0 -#define PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_0 0x0 -#define PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_0 0x0 -#define PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_0 ((TIMER_IS_ALWAYS_ON_CAPABLE << 1) | (!TIMER_IS_SECURE << 0)) -#define PLATFORM_OVERRIDE_TIMER_FLAGS_0 ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_0 << 16) | \ - (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_0 << 8) | \ - (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_0)) - -#define PLATFORM_OVERRIDE_TIMER_CNTBASE_1 0x2a820000 -#define PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_1 0xFFFFFFFFFFFFFFFF -#define PLATFORM_OVERRIDE_TIMER_GSIV_1 0x5B -#define PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_1 0x0 -#define PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1 0x0 -#define PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1 0x0 -#define PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1 ((TIMER_IS_ALWAYS_ON_CAPABLE << 1) | (TIMER_IS_SECURE << 0)) -#define PLATFORM_OVERRIDE_TIMER_FLAGS_1 ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1 << 16) | \ - (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1 << 8) | \ - (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1)) -#define PLATFORM_OVERRIDE_TIMER_CNTFRQ 0x0 -#define PLATFORM_OVERRIDE_TIMEOUT 1 -/* Define the Timeout values to be used */ -#define PLATFORM_OVERRIDE_TIMEOUT_LARGE 0x100000 -#define PLATFORM_OVERRIDE_TIMEOUT_MEDIUM 0x10000 -#define PLATFORM_OVERRIDE_TIMEOUT_SMALL 0x100 - -/* Watchdog platform config parameters */ -#define WD_MODE INTERRUPT_IS_LEVEL_TRIGGERED -#define WD_POLARITY INTERRUPT_IS_ACTIVE_HIGH - -#define WD_IS_SECURE 0x1 - -#define PLATFORM_OVERRIDE_WD_TIMER_COUNT 0x2 -#define PLATFORM_OVERRIDE_WD_REFRESH_BASE 0x2A450000 -#define PLATFORM_OVERRIDE_WD_CTRL_BASE 0x2A440000 -#define PLATFORM_OVERRIDE_WD_GSIV_0 0x5D -#define PLATFORM_OVERRIDE_WD_FLAGS_0 ((!WD_IS_SECURE << 2) | (WD_POLARITY << 1) | (WD_MODE << 0)) -#define PLATFORM_OVERRIDE_WD_GSIV_1 0x5E -#define PLATFORM_OVERRIDE_WD_FLAGS_1 ((WD_IS_SECURE << 2) | (WD_POLARITY << 1) | (WD_MODE << 0)) - - - -/* PCIE platform config parameters */ -#define PLATFORM_OVERRIDE_NUM_ECAM 1 - -/* Offset from the memory range to be accesed - * Modify this macro w.r.t to the requirement */ -#define MEM_OFFSET_SMALL 0x10 -#define MEM_OFFSET_MEDIUM 0x1000 - -/* Platform config parameters for ECAM_0 */ -#define PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_0 0x60000000 -#define PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_0 0x0 -#define PLATFORM_OVERRIDE_PCIE_START_BUS_NUM_0 0x0 -#define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_0 0xFF - -#define PLATFORM_OVERRIDE_PCIE_MAX_BUS 256 -#define PLATFORM_OVERRIDE_PCIE_MAX_DEV 32 -#define PLATFORM_OVERRIDE_PCIE_MAX_FUNC 8 - -/* Sample macros for ECAM_1 - * #define PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_1 0x00000000 - * #define PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_1 0x0 - * #define PLATFORM_OVERRIDE_PCIE_START_BUS_NUM_1 0x0 - * #define PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_1 0x0 - */ - -/* PCIE device hierarchy table */ - -#define PLATFORM_PCIE_NUM_ENTRIES 21 -#define PLATFORM_PCIE_P2P_NOT_SUPPORTED 1 - -#define PLATFORM_PCIE_DEV0_CLASSCODE 0x6040000 -#define PLATFORM_PCIE_DEV0_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV0_DEV_ID 0xDEF -#define PLATFORM_PCIE_DEV0_BUS_NUM 0 -#define PLATFORM_PCIE_DEV0_DEV_NUM 1 -#define PLATFORM_PCIE_DEV0_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV0_SEG_NUM 0 -#define PLATFORM_PCIE_DEV0_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV0_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV0_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV0_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV0_BEHIND_SMMU 1 -#define PLATFORM_PCIE_DEV0_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV1_CLASSCODE 0x6040000 -#define PLATFORM_PCIE_DEV1_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV1_DEV_ID 0xDEF -#define PLATFORM_PCIE_DEV1_BUS_NUM 0 -#define PLATFORM_PCIE_DEV1_DEV_NUM 2 -#define PLATFORM_PCIE_DEV1_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV1_SEG_NUM 0 -#define PLATFORM_PCIE_DEV1_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV1_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV1_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV1_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV1_BEHIND_SMMU 1 -#define PLATFORM_PCIE_DEV1_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV2_CLASSCODE 0x6040000 -#define PLATFORM_PCIE_DEV2_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV2_DEV_ID 0xDEF -#define PLATFORM_PCIE_DEV2_BUS_NUM 0 -#define PLATFORM_PCIE_DEV2_DEV_NUM 3 -#define PLATFORM_PCIE_DEV2_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV2_SEG_NUM 0 -#define PLATFORM_PCIE_DEV2_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV2_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV2_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV2_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV2_BEHIND_SMMU 1 -#define PLATFORM_PCIE_DEV2_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV3_CLASSCODE 0xED000001 -#define PLATFORM_PCIE_DEV3_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV3_DEV_ID 0xED01 -#define PLATFORM_PCIE_DEV3_BUS_NUM 0 -#define PLATFORM_PCIE_DEV3_DEV_NUM 0x1E -#define PLATFORM_PCIE_DEV3_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV3_SEG_NUM 0 -#define PLATFORM_PCIE_DEV3_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV3_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV3_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV3_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV3_BEHIND_SMMU 1 -#define PLATFORM_PCIE_DEV3_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV4_CLASSCODE 0xED000001 -#define PLATFORM_PCIE_DEV4_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV4_DEV_ID 0xED01 -#define PLATFORM_PCIE_DEV4_BUS_NUM 0 -#define PLATFORM_PCIE_DEV4_DEV_NUM 0x1E -#define PLATFORM_PCIE_DEV4_FUNC_NUM 1 -#define PLATFORM_PCIE_DEV4_SEG_NUM 0 -#define PLATFORM_PCIE_DEV4_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV4_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV4_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV4_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV4_BEHIND_SMMU 1 -#define PLATFORM_PCIE_DEV4_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV5_CLASSCODE 0x1060101 -#define PLATFORM_PCIE_DEV5_VENDOR_ID 0x0ABC -#define PLATFORM_PCIE_DEV5_DEV_ID 0xACED -#define PLATFORM_PCIE_DEV5_BUS_NUM 0 -#define PLATFORM_PCIE_DEV5_DEV_NUM 0x1F -#define PLATFORM_PCIE_DEV5_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV5_SEG_NUM 0 -#define PLATFORM_PCIE_DEV5_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV5_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV5_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV5_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV5_BEHIND_SMMU 1 -#define PLATFORM_PCIE_DEV5_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV6_CLASSCODE 0x1060101 -#define PLATFORM_PCIE_DEV6_VENDOR_ID 0x0ABC -#define PLATFORM_PCIE_DEV6_DEV_ID 0xACED -#define PLATFORM_PCIE_DEV6_BUS_NUM 1 -#define PLATFORM_PCIE_DEV6_DEV_NUM 0 -#define PLATFORM_PCIE_DEV6_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV6_SEG_NUM 0 -#define PLATFORM_PCIE_DEV6_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV6_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV6_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV6_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV6_BEHIND_SMMU 1 -#define PLATFORM_PCIE_DEV6_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV7_CLASSCODE 0xED000000 -#define PLATFORM_PCIE_DEV7_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV7_DEV_ID 0xED01 -#define PLATFORM_PCIE_DEV7_BUS_NUM 2 -#define PLATFORM_PCIE_DEV7_DEV_NUM 0 -#define PLATFORM_PCIE_DEV7_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV7_SEG_NUM 0 -#define PLATFORM_PCIE_DEV7_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV7_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV7_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV7_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV7_BEHIND_SMMU 1 -#define PLATFORM_PCIE_DEV7_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV8_CLASSCODE 0xED000000 -#define PLATFORM_PCIE_DEV8_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV8_DEV_ID 0xED01 -#define PLATFORM_PCIE_DEV8_BUS_NUM 2 -#define PLATFORM_PCIE_DEV8_DEV_NUM 0 -#define PLATFORM_PCIE_DEV8_FUNC_NUM 4 -#define PLATFORM_PCIE_DEV8_SEG_NUM 0 -#define PLATFORM_PCIE_DEV8_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV8_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV8_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV8_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV8_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV8_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV9_CLASSCODE 0x6040000 -#define PLATFORM_PCIE_DEV9_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV9_DEV_ID 0xDEF -#define PLATFORM_PCIE_DEV9_BUS_NUM 3 -#define PLATFORM_PCIE_DEV9_DEV_NUM 0 -#define PLATFORM_PCIE_DEV9_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV9_SEG_NUM 0 -#define PLATFORM_PCIE_DEV9_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV9_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV9_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV9_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV9_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV9_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV10_CLASSCODE 0x6040000 -#define PLATFORM_PCIE_DEV10_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV10_DEV_ID 0xDEF -#define PLATFORM_PCIE_DEV10_BUS_NUM 4 -#define PLATFORM_PCIE_DEV10_DEV_NUM 0 -#define PLATFORM_PCIE_DEV10_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV10_SEG_NUM 0 -#define PLATFORM_PCIE_DEV10_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV10_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV10_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV10_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV10_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV10_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV11_CLASSCODE 0x6040000 -#define PLATFORM_PCIE_DEV11_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV11_DEV_ID 0xDEF -#define PLATFORM_PCIE_DEV11_BUS_NUM 4 -#define PLATFORM_PCIE_DEV11_DEV_NUM 1 -#define PLATFORM_PCIE_DEV11_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV11_SEG_NUM 0 -#define PLATFORM_PCIE_DEV11_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV11_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV11_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV11_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV11_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV11_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV12_CLASSCODE 0x6040000 -#define PLATFORM_PCIE_DEV12_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV12_DEV_ID 0xDEF -#define PLATFORM_PCIE_DEV12_BUS_NUM 4 -#define PLATFORM_PCIE_DEV12_DEV_NUM 2 -#define PLATFORM_PCIE_DEV12_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV12_SEG_NUM 0 -#define PLATFORM_PCIE_DEV12_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV12_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV12_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV12_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV12_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV12_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV13_CLASSCODE 0x1060101 -#define PLATFORM_PCIE_DEV13_VENDOR_ID 0xABC -#define PLATFORM_PCIE_DEV13_DEV_ID 0xACED -#define PLATFORM_PCIE_DEV13_BUS_NUM 5 -#define PLATFORM_PCIE_DEV13_DEV_NUM 0 -#define PLATFORM_PCIE_DEV13_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV13_SEG_NUM 0 -#define PLATFORM_PCIE_DEV13_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV13_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV13_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV13_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV13_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV13_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV14_CLASSCODE 0xED000000 -#define PLATFORM_PCIE_DEV14_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV14_DEV_ID 0xED01 -#define PLATFORM_PCIE_DEV14_BUS_NUM 6 -#define PLATFORM_PCIE_DEV14_DEV_NUM 0 -#define PLATFORM_PCIE_DEV14_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV14_SEG_NUM 0 -#define PLATFORM_PCIE_DEV14_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV14_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV14_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV14_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV14_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV14_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV15_CLASSCODE 0xED000000 -#define PLATFORM_PCIE_DEV15_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV15_DEV_ID 0xED01 -#define PLATFORM_PCIE_DEV15_BUS_NUM 6 -#define PLATFORM_PCIE_DEV15_DEV_NUM 0 -#define PLATFORM_PCIE_DEV15_FUNC_NUM 7 -#define PLATFORM_PCIE_DEV15_SEG_NUM 0 -#define PLATFORM_PCIE_DEV15_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV15_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV15_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV15_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV15_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV15_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV16_CLASSCODE 0xFF000000 -#define PLATFORM_PCIE_DEV16_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV16_DEV_ID 0xFF80 -#define PLATFORM_PCIE_DEV16_BUS_NUM 7 -#define PLATFORM_PCIE_DEV16_DEV_NUM 0 -#define PLATFORM_PCIE_DEV16_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV16_SEG_NUM 0 -#define PLATFORM_PCIE_DEV16_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV16_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV16_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV16_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV16_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV16_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV17_CLASSCODE 0xFF000000 -#define PLATFORM_PCIE_DEV17_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV17_DEV_ID 0xFF80 -#define PLATFORM_PCIE_DEV17_BUS_NUM 7 -#define PLATFORM_PCIE_DEV17_DEV_NUM 0 -#define PLATFORM_PCIE_DEV17_FUNC_NUM 3 -#define PLATFORM_PCIE_DEV17_SEG_NUM 0 -#define PLATFORM_PCIE_DEV17_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV17_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV17_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV17_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV17_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV17_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV18_CLASSCODE 0xFF000000 -#define PLATFORM_PCIE_DEV18_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV18_DEV_ID 0xFF80 -#define PLATFORM_PCIE_DEV18_BUS_NUM 8 -#define PLATFORM_PCIE_DEV18_DEV_NUM 0 -#define PLATFORM_PCIE_DEV18_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV18_SEG_NUM 0 -#define PLATFORM_PCIE_DEV18_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV18_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV18_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV18_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV18_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV18_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV19_CLASSCODE 0xFF000000 -#define PLATFORM_PCIE_DEV19_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV19_DEV_ID 0xFF80 -#define PLATFORM_PCIE_DEV19_BUS_NUM 8 -#define PLATFORM_PCIE_DEV19_DEV_NUM 0 -#define PLATFORM_PCIE_DEV19_FUNC_NUM 1 -#define PLATFORM_PCIE_DEV19_SEG_NUM 0 -#define PLATFORM_PCIE_DEV19_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV19_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV19_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV19_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV19_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV19_ATC_SUPPORT 0 - -#define PLATFORM_PCIE_DEV20_CLASSCODE 0x6040000 -#define PLATFORM_PCIE_DEV20_VENDOR_ID 0x13B5 -#define PLATFORM_PCIE_DEV20_DEV_ID 0x0DEF -#define PLATFORM_PCIE_DEV20_BUS_NUM 0 -#define PLATFORM_PCIE_DEV20_DEV_NUM 4 -#define PLATFORM_PCIE_DEV20_FUNC_NUM 0 -#define PLATFORM_PCIE_DEV20_SEG_NUM 0 -#define PLATFORM_PCIE_DEV20_DMA_SUPPORT 0 -#define PLATFORM_PCIE_DEV20_DMA_COHERENT 0 -#define PLATFORM_PCIE_DEV20_P2P_SUPPORT 1 -#define PLATFORM_PCIE_DEV20_DMA_64BIT 0 -#define PLATFORM_PCIE_DEV20_BEHIND_SMMU 0 -#define PLATFORM_PCIE_DEV20_ATC_SUPPORT 0 - -/* PERIPHERAL platform config parameters */ -#define PLATFORM_OVERRIDE_PERIPHERAL_COUNT 3 //UART + USB + SATA - -#define UART_ADDRESS 0xF9750000 -#define BASE_ADDRESS_ADDRESS_SPACE_ID 0x0 -#define BASE_ADDRESS_REGISTER_BIT_WIDTH 0x20 -#define BASE_ADDRESS_REGISTER_BIT_OFFSET 0x0 -#define BASE_ADDRESS_ADDRESS_SIZE 0x3 -#define BASE_ADDRESS_ADDRESS 0x7FF80000 -#define UART_INTERRUPT_TYPE 8 -#define UART_IRQ 0 -#define UART_GLOBAL_SYSTEM_INTERRUPT 0x93 -#define UART_PCI_DEVICE_ID 0xFFFF -#define UART_PCI_VENDOR_ID 0xFFFF -#define UART_PCI_BUS_NUMBER 0x0 -#define UART_PCI_DEV_NUMBER 0x0 -#define UART_PCI_FUNC_NUMBER 0x0 -#define UART_PCI_FLAGS 0x0 -#define UART_PCI_SEGMENT 0x0 - -/* IOVIRT platform config parameters */ -#define IOVIRT_ADDRESS 0xF9780000 -#define IORT_NODE_COUNT 3 -#define IOVIRT_ITS_COUNT 1 -#define IOVIRT_SMMUV3_COUNT 1 -#define IOVIRT_RC_COUNT 1 -#define IOVIRT_SMMUV2_COUNT 0 -#define IOVIRT_NAMED_COMPONENT_COUNT 0 -#define IOVIRT_PMCG_COUNT 0 -#define IOVIRT_SMMUV3_BASE_ADDRESS 0x4F000000 -#define IOVIRT_SMMU_CTX_INT_OFFSET 0x0 -#define IOVIRT_SMMU_CTX_INT_CNT 0x0 -#define IOVIRT_RC_PCI_SEG_NUM 0x0 -#define IOVIRT_RC_MEMORY_PROPERTIES 0x1 -#define IOVIRT_RC_ATS_ATTRIBUTE 0x0 -#define RC_MAP0_INPUT_BASE 0x0 -#define RC_MAP0_ID_COUNT 0xFFFF -#define RC_MAP0_OUTPUT_BASE 0x0 -#define RC_MAP0_OUTPUT_REF 0x134 - -#define SMMUV3_ID_MAP0_INPUT_BASE 0x0 -#define SMMUV3_ID_MAP0_ID_COUNT 0xFFFF -#define SMMUV3_ID_MAP0_OUTPUT_BASE 0x0 -#define SMMUV3_ID_MAP0_OUTPUT_REF 0x30 -#define SMMUV3_ID_MAP1_INPUT_BASE 0x0 -#define SMMUV3_ID_MAP1_ID_COUNT 0x1 -#define SMMUV3_ID_MAP1_OUTPUT_BASE 0x10000 -#define SMMUV3_ID_MAP1_OUTPUT_REF 0x30 -#define IOVIRT_RC_NUM_MAP 1 -#define IOVIRT_SMMUV3_NUM_MAP 2 -#define IOVIRT_MAX_NUM_MAP 3 - -/* DMA platform config parameters */ -#define PLATFORM_OVERRIDE_DMA_CNT 0 - -/*Exerciser platform config details*/ -#define TEST_REG_COUNT 10 -#define EXERCISER_ID 0xED0113B5 -#define PCIE_CAP_CTRL_OFFSET 0x4// offset from the extended capability header - -/* Exerciser MMIO Offsets */ -#define INTXCTL 0x004 -#define MSICTL 0x000 -#define DMACTL1 0x08 -#define DMA_BUS_ADDR 0x010 -#define DMA_LEN 0x018 -#define DMASTATUS 0x01C -#define PCI_MAX_BUS 255 -#define PCI_MAX_DEVICE 31 -#define PASID_VAL 0x020 -#define ATSCTL 0x024 -#define ATS_ADDR 0x028 - -#define PCI_EXT_CAP_ID 0x10 -#define PASID 0x1B -#define PCIE 0x1 -#define PCI 0x0 - -/* PCI/PCIe express extended capability structure's - next capability pointer mask and cap ID mask */ -#define PCIE_NXT_CAP_PTR_MASK 0x0FFF -#define PCIE_CAP_ID_MASK 0xFFFF -#define PCI_CAP_ID_MASK 0x00FF -#define PCI_NXT_CAP_PTR_MASK 0x00FF -#define CAP_PTR_MASK 0x00FF - -#define CLR_INTR_MASK 0xFFFFFFFE -#define PASID_TLP_STOP_MASK 0xFFFFFFBF -#define PASID_VAL_MASK ((0x1ul << 20) - 1) -#define PASID_VAL_SHIFT 12 -#define PASID_LEN_SHIFT 7 -#define PASID_LEN_MASK 0x7ul -#define PASID_EN_SHIFT 6 -#define DMA_TO_DEVICE_MASK 0xFFFFFFEF - -/* shift_bit */ -#define SHIFT_1BIT 1 -#define SHIFT_2BIT 2 -#define SHIFT_4BIT 4 -#define SHITT_8BIT 8 -#define MASK_BIT 1 -#define PREFETCHABLE_BIT_SHIFT 3 - -#define PCI_CAP_PTR_OFFSET 8 -#define PCIE_CAP_PTR_OFFSET 20 - -#define MSI_GENERATION_MASK (1 << 31) - -#define NO_SNOOP_START_MASK 0x20 -#define NO_SNOOP_STOP_MASK 0xFFFFFFDF -#define PCIE_CAP_DIS_MASK 0xFFFEFFFF -#define PCIE_CAP_EN_MASK (1 << 16) -#define PASID_EN_MASK (1 << 6) - -/* PCIe Config space Offset */ -#define BAR0_OFFSET 0x10 -#define COMMAND_REG_OFFSET 0x04 -#define CAP_PTR_OFFSET 0x34 -#define PCIE_CAP_OFFSET 0x100 - - -#define RID_CTL_REG 0x3C -#define RID_VALUE_MASK 0xFFFF -#define RID_VALID_MASK (1ul << 31) -#define RID_VALID 1 -#define RID_NOT_VALID 0 -#define ATS_TRIGGER 1 -#define ATS_STATUS (1ul << 7) - -#define PCIE_CAP_CTRL_OFFSET 0x4// offset from the extended capability header - -/* Memory config */ -#define PLATFORM_OVERRIDE_MEMORY_ENTRY_COUNT 0x4 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_PHY_ADDR 0xC000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_VIRT_ADDR 0xC000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_SIZE 0x4000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY0_TYPE MEMORY_TYPE_DEVICE -#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_PHY_ADDR 0x10000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_VIRT_ADDR 0x10000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_SIZE 0xC170000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY1_TYPE MEMORY_TYPE_NOT_POPULATED -#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_PHY_ADDR 0xFF600000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_VIRT_ADDR 0xFF600000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_SIZE 0x10000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY2_TYPE MEMORY_TYPE_RESERVED -#define PLATFORM_OVERRIDE_MEMORY_ENTRY3_PHY_ADDR 0x80000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY3_VIRT_ADDR 0x80000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY3_SIZE 0x7F000000 -#define PLATFORM_OVERRIDE_MEMORY_ENTRY3_TYPE MEMORY_TYPE_NORMAL - -/** End config **/ diff --git a/platform/pal_baremetal/FVP/RDN1/include/platform_override_struct.h b/platform/pal_baremetal/FVP/RDN1/include/platform_override_struct.h deleted file mode 100644 index a6810984..00000000 --- a/platform/pal_baremetal/FVP/RDN1/include/platform_override_struct.h +++ /dev/null @@ -1,216 +0,0 @@ -/** @file - * Copyright (c) 2020-2022, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - -#include -#include -#include "platform_override_fvp.h" - -typedef struct { - uint32_t gic_version; - uint32_t num_gicc; - uint32_t num_gicd; - uint32_t num_gicrd; - uint32_t num_gicits; - uint32_t num_gich; - uint32_t num_msiframes; - uint32_t gicc_type; - uint32_t gicd_type; - uint32_t gicrd_type; - uint32_t gicrd_length; - uint32_t gicits_type; - uint64_t gicc_base[PLATFORM_OVERRIDE_GICC_COUNT]; - uint64_t gicd_base[PLATFORM_OVERRIDE_GICD_COUNT]; - uint64_t gicrd_base[PLATFORM_OVERRIDE_GICRD_COUNT]; - uint64_t gicits_base[PLATFORM_OVERRIDE_GICITS_COUNT]; - uint64_t gicits_id[PLATFORM_OVERRIDE_GICITS_COUNT]; - uint64_t gich_base[PLATFORM_OVERRIDE_GICH_COUNT]; - uint64_t gicmsiframe_base[PLATFORM_OVERRIDE_GICMSIFRAME_COUNT]; - uint64_t gicmsiframe_id[PLATFORM_OVERRIDE_GICMSIFRAME_COUNT]; - uint32_t gicmsiframe_flags[PLATFORM_OVERRIDE_GICMSIFRAME_COUNT]; - uint32_t gicmsiframe_spi_count[PLATFORM_OVERRIDE_GICMSIFRAME_COUNT]; - uint32_t gicmsiframe_spi_base[PLATFORM_OVERRIDE_GICMSIFRAME_COUNT]; -} PLATFORM_OVERRIDE_GIC_INFO_TABLE; - -typedef struct { - uint32_t s_el1_timer_flags; - uint32_t ns_el1_timer_flags; - uint32_t el2_timer_flags; - uint32_t s_el1_timer_gsiv; - uint32_t ns_el1_timer_gsiv; - uint32_t el2_timer_gsiv; - uint32_t virtual_timer_flags; - uint32_t virtual_timer_gsiv; - uint32_t el2_virt_timer_gsiv; - uint32_t num_platform_timer; -} PLATFORM_OVERRIDE_TIMER_INFO_HDR; - -typedef struct { - uint32_t type; - uint32_t timer_count; - uint64_t block_cntl_base; - uint64_t GtCntBase[PLATFORM_OVERRIDE_TIMER_COUNT]; - uint64_t GtCntEl0Base[PLATFORM_OVERRIDE_TIMER_COUNT]; - uint32_t gsiv[PLATFORM_OVERRIDE_TIMER_COUNT]; - uint32_t virt_gsiv[PLATFORM_OVERRIDE_TIMER_COUNT]; - uint32_t flags[PLATFORM_OVERRIDE_TIMER_COUNT]; -} PLATFORM_OVERRIDE_TIMER_INFO_GTBLOCK; - -typedef struct { - PLATFORM_OVERRIDE_TIMER_INFO_HDR header; - PLATFORM_OVERRIDE_TIMER_INFO_GTBLOCK gt_info; -} PLATFORM_OVERRIDE_TIMER_INFO_TABLE; - -typedef struct { - uint32_t arch_major_rev; ///< Version 1 or 2 or 3 - uint64_t base; ///< SMMU Controller base address - uint64_t context_interrupt_offset; - uint32_t context_interrupt_count; -} PLATFORM_OVERRIDE_SMMU_INFO_BLOCK; - -typedef struct { - uint32_t segment; - uint32_t ats_attr; - uint32_t cca; //Cache Coherency Attribute - uint64_t smmu_base; -} PLATFORM_OVERRIDE_IOVIRT_RC_INFO_BLOCK; - -typedef struct { - uint64_t base; - uint32_t overflow_gsiv; - uint32_t node_ref; -} PLATFORM_OVERRIDE_IOVIRT_PMCG_INFO_BLOCK; - -#define MAX_NAMED_COMP_LENGTH 256 - -typedef struct { - char name[MAX_NAMED_COMP_LENGTH]; - PLATFORM_OVERRIDE_IOVIRT_RC_INFO_BLOCK rc; - PLATFORM_OVERRIDE_IOVIRT_PMCG_INFO_BLOCK pmcg; - uint32_t its_count; - PLATFORM_OVERRIDE_SMMU_INFO_BLOCK smmu; -} PLATFORM_OVERRIDE_NODE_DATA; - -typedef struct { - uint32_t input_base[IOVIRT_MAX_NUM_MAP]; - uint32_t id_count[IOVIRT_MAX_NUM_MAP]; - uint32_t output_base[IOVIRT_MAX_NUM_MAP]; - uint32_t output_ref[IOVIRT_MAX_NUM_MAP]; -} PLATFORM_OVERRIDE_NODE_DATA_MAP; - -typedef struct { - uint64_t Address; - uint32_t node_count; - uint32_t type[IORT_NODE_COUNT]; - uint32_t num_map[IORT_NODE_COUNT]; - PLATFORM_OVERRIDE_NODE_DATA_MAP map[IORT_NODE_COUNT]; -} PLATFORM_OVERRIDE_IOVIRT_INFO_TABLE; - -struct ecam_reg_data { - uint32_t offset; //Offset into 4096 bytes ecam config reg space - uint32_t attribute; - uint32_t value; -}; - -struct exerciser_data_cfg_space { - struct ecam_reg_data reg[TEST_REG_COUNT]; -}; - -typedef enum { - MMIO_PREFETCHABLE = 0x0, - MMIO_NON_PREFETCHABLE = 0x1 -} BAR_MEM_TYPE; - -struct exerciser_data_bar_space { - void *base_addr; - BAR_MEM_TYPE type; -}; - -typedef enum { - MMIO = 0, - IO = 1 -} BAR_MEM_INDICATOR_TYPE; - -typedef enum { - BITS_32 = 0, - BITS_64 = 2 -} BAR_MEM_DECODE_TYPE; - -typedef union exerciser_data { - struct exerciser_data_cfg_space cfg_space; - struct exerciser_data_bar_space bar_space; -} exerciser_data_t; - -typedef enum { - EXERCISER_DATA_CFG_SPACE = 0x1, - EXERCISER_DATA_BAR0_SPACE = 0x2, - EXERCISER_DATA_MMIO_SPACE = 0x3, -} EXERCISER_DATA_TYPE; - -typedef enum { - ACCESS_TYPE_RD = 0x0, - ACCESS_TYPE_RW = 0x1 -} ECAM_REG_ATTRIBUTE; - -typedef enum { - TYPE0 = 0x0, - TYPE1 = 0x1, -} EXERCISER_CFG_HEADER_TYPE; - - -typedef enum { - CFG_READ = 0x0, - CFG_WRITE = 0x1, -} EXERCISER_CFG_TXN_ATTR; - - -typedef enum { - TXN_REQ_ID = 0x0, - TXN_ADDR_TYPE = 0x1, - TXN_REQ_ID_VALID = 0x2, -} EXERCISER_TXN_ATTR; - -typedef enum { - AT_UNTRANSLATED = 0x0, - AT_TRANS_REQ = 0x1, - AT_TRANSLATED = 0x2, - AT_RESERVED = 0x3 -} EXERCISER_TXN_ADDR_TYPE; - - -typedef enum { - DEVICE_nGnRnE = 0x0, - DEVICE_nGnRE = 0x1, - DEVICE_nGRE = 0x2, - DEVICE_GRE = 0x3 -} ARM_DEVICE_MEM; - -typedef enum { - NORMAL_NC = 0x4, - NORMAL_WT = 0x5 -} ARM_NORMAL_MEM; - -typedef struct { - uint64_t phy_addr; - uint64_t virt_addr; - uint64_t size; - uint64_t type; -} MEMORY_INFO; - -typedef struct { - uint32_t count; - MEMORY_INFO info[]; -} PLATFORM_OVERRIDE_MEMORY_INFO_TABLE; diff --git a/platform/pal_baremetal/FVP/RDN1/src/platform_cfg_fvp.c b/platform/pal_baremetal/FVP/RDN1/src/platform_cfg_fvp.c deleted file mode 100644 index 92bafe43..00000000 --- a/platform/pal_baremetal/FVP/RDN1/src/platform_cfg_fvp.c +++ /dev/null @@ -1,530 +0,0 @@ -/** @file - * Copyright (c) 2020-2022, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" - -PE_INFO_TABLE platform_pe_cfg = { - - .header.num_of_pe = PLATFORM_OVERRIDE_PE_CNT, - - .pe_info[0].pe_num = PLATFORM_OVERRIDE_PE0_INDEX, - .pe_info[0].mpidr = PLATFORM_OVERRIDE_PE0_MPIDR, - .pe_info[0].pmu_gsiv = PLATFORM_OVERRIDE_PE0_PMU_GSIV, - - .pe_info[1].pe_num = PLATFORM_OVERRIDE_PE1_INDEX, - .pe_info[1].mpidr = PLATFORM_OVERRIDE_PE1_MPIDR, - .pe_info[1].pmu_gsiv = PLATFORM_OVERRIDE_PE1_PMU_GSIV, - - .pe_info[2].pe_num = PLATFORM_OVERRIDE_PE2_INDEX, - .pe_info[2].mpidr = PLATFORM_OVERRIDE_PE2_MPIDR, - .pe_info[2].pmu_gsiv = PLATFORM_OVERRIDE_PE2_PMU_GSIV, - - .pe_info[3].pe_num = PLATFORM_OVERRIDE_PE3_INDEX, - .pe_info[3].mpidr = PLATFORM_OVERRIDE_PE3_MPIDR, - .pe_info[3].pmu_gsiv = PLATFORM_OVERRIDE_PE3_PMU_GSIV, - - .pe_info[4].pe_num = PLATFORM_OVERRIDE_PE4_INDEX, - .pe_info[4].mpidr = PLATFORM_OVERRIDE_PE4_MPIDR, - .pe_info[4].pmu_gsiv = PLATFORM_OVERRIDE_PE4_PMU_GSIV, - - .pe_info[5].pe_num = PLATFORM_OVERRIDE_PE5_INDEX, - .pe_info[5].mpidr = PLATFORM_OVERRIDE_PE5_MPIDR, - .pe_info[5].pmu_gsiv = PLATFORM_OVERRIDE_PE5_PMU_GSIV, - - .pe_info[6].pe_num = PLATFORM_OVERRIDE_PE6_INDEX, - .pe_info[6].mpidr = PLATFORM_OVERRIDE_PE6_MPIDR, - .pe_info[6].pmu_gsiv = PLATFORM_OVERRIDE_PE6_PMU_GSIV, - - .pe_info[7].pe_num = PLATFORM_OVERRIDE_PE7_INDEX, - .pe_info[7].mpidr = PLATFORM_OVERRIDE_PE7_MPIDR, - .pe_info[7].pmu_gsiv = PLATFORM_OVERRIDE_PE7_PMU_GSIV - -}; - - -PLATFORM_OVERRIDE_GIC_INFO_TABLE platform_gic_cfg = { - - .gic_version = PLATFORM_OVERRIDE_GIC_VERSION, - .num_gicc = PLATFORM_OVERRIDE_GICC_COUNT, - .num_gicd = PLATFORM_OVERRIDE_GICD_COUNT, - .num_gicrd = PLATFORM_OVERRIDE_GICRD_COUNT, - .num_gicits = PLATFORM_OVERRIDE_GICITS_COUNT, - .num_gich = PLATFORM_OVERRIDE_GICH_COUNT, - .num_msiframes = PLATFORM_OVERRIDE_GICMSIFRAME_COUNT, - - .gicrd_length = PLATFORM_OVERRIDE_GICIRD_LENGTH, - - .gicc_base[0] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[1] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[2] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[3] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[4] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[5] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[6] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[7] = PLATFORM_OVERRIDE_GICC_BASE, - - .gicd_base[0] = PLATFORM_OVERRIDE_GICD_BASE, - .gicrd_base[0] = PLATFORM_OVERRIDE_GICRD_BASE, - .gicits_base[0] = PLATFORM_OVERRIDE_GICITS_BASE, - .gicits_id[0] = PLATFORM_OVERRIDE_GICITS_ID, - .gich_base[0] = PLATFORM_OVERRIDE_GICH_BASE - -}; - -PLATFORM_OVERRIDE_TIMER_INFO_TABLE platform_timer_cfg = { - - .header.s_el1_timer_flags = PLATFORM_OVERRIDE_S_EL1_TIMER_FLAGS, - .header.ns_el1_timer_flags = PLATFORM_OVERRIDE_NS_EL1_TIMER_FLAGS, - .header.el2_timer_flags = PLATFORM_OVERRIDE_NS_EL2_TIMER_FLAGS, - .header.s_el1_timer_gsiv = PLATFORM_OVERRIDE_S_EL1_TIMER_GSIV, - .header.ns_el1_timer_gsiv = PLATFORM_OVERRIDE_NS_EL1_TIMER_GSIV, - .header.el2_timer_gsiv = PLATFORM_OVERRIDE_NS_EL2_TIMER_GSIV, - .header.virtual_timer_flags = PLATFORM_OVERRIDE_VIRTUAL_TIMER_FLAGS, - .header.virtual_timer_gsiv = PLATFORM_OVERRIDE_VIRTUAL_TIMER_GSIV, - .header.el2_virt_timer_gsiv = PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV, - .header.num_platform_timer = PLATFORM_OVERRIDE_PLATFORM_TIMER_COUNT, - - .gt_info.type = PLATFORM_OVERRIDE_TIMER_TYPE, - .gt_info.timer_count = PLATFORM_OVERRIDE_TIMER_COUNT, - .gt_info.block_cntl_base = PLATFORM_OVERRIDE_TIMER_CNTCTL_BASE, - .gt_info.GtCntBase[0] = PLATFORM_OVERRIDE_TIMER_CNTBASE_0, - .gt_info.GtCntBase[1] = PLATFORM_OVERRIDE_TIMER_CNTBASE_1, - .gt_info.GtCntEl0Base[0] = PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_0, - .gt_info.GtCntEl0Base[1] = PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_1, - .gt_info.gsiv[0] = PLATFORM_OVERRIDE_TIMER_GSIV_0, - .gt_info.gsiv[1] = PLATFORM_OVERRIDE_TIMER_GSIV_1, - .gt_info.virt_gsiv[0] = PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_0, - .gt_info.virt_gsiv[1] = PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_1, - .gt_info.flags[0] = PLATFORM_OVERRIDE_TIMER_FLAGS_0, - .gt_info.flags[1] = PLATFORM_OVERRIDE_TIMER_FLAGS_1 - -}; - -WD_INFO_TABLE platform_wd_cfg = { - .header.num_wd = PLATFORM_OVERRIDE_WD_TIMER_COUNT, - .wd_info[0].wd_ctrl_base = PLATFORM_OVERRIDE_WD_CTRL_BASE, - .wd_info[0].wd_refresh_base = PLATFORM_OVERRIDE_WD_REFRESH_BASE, - .wd_info[0].wd_gsiv = PLATFORM_OVERRIDE_WD_GSIV_0, - .wd_info[0].wd_flags = PLATFORM_OVERRIDE_WD_FLAGS_0, - .wd_info[1].wd_ctrl_base = PLATFORM_OVERRIDE_WD_CTRL_BASE, - .wd_info[1].wd_refresh_base = PLATFORM_OVERRIDE_WD_REFRESH_BASE, - .wd_info[1].wd_gsiv = PLATFORM_OVERRIDE_WD_GSIV_1, - .wd_info[1].wd_flags = PLATFORM_OVERRIDE_WD_FLAGS_1 - -}; - -PCIE_INFO_TABLE platform_pcie_cfg = { - .num_entries = PLATFORM_OVERRIDE_NUM_ECAM, - .block[0].ecam_base = PLATFORM_OVERRIDE_PCIE_ECAM_BASE_ADDR_0, - .block[0].segment_num = PLATFORM_OVERRIDE_PCIE_SEGMENT_GRP_NUM_0, - .block[0].start_bus_num = PLATFORM_OVERRIDE_PCIE_START_BUS_NUM_0, - .block[0].end_bus_num = PLATFORM_OVERRIDE_PCIE_END_BUS_NUM_0 - -/** Configure more PCIe info details as per specification for more than 1 ECAM - Refer to platform_override_fvp.h file for an example -**/ -}; - -PLATFORM_OVERRIDE_IOVIRT_INFO_TABLE platform_iovirt_cfg = { - .Address = IOVIRT_ADDRESS, - .node_count = IORT_NODE_COUNT, - .type[0] = IOVIRT_NODE_ITS_GROUP, - .type[2] = IOVIRT_NODE_PCI_ROOT_COMPLEX, - .type[1] = IOVIRT_NODE_SMMU_V3, - .num_map[2] = IOVIRT_RC_NUM_MAP, - .num_map[1] = IOVIRT_SMMUV3_NUM_MAP, - .map[2].input_base[0] = RC_MAP0_INPUT_BASE, - .map[2].id_count[0] = RC_MAP0_ID_COUNT, - .map[2].output_base[0]= RC_MAP0_OUTPUT_BASE, - .map[2].output_ref[0] = RC_MAP0_OUTPUT_REF, - .map[1].input_base[0] = SMMUV3_ID_MAP0_INPUT_BASE, - .map[1].id_count[0] = SMMUV3_ID_MAP0_ID_COUNT, - .map[1].output_base[0]= SMMUV3_ID_MAP0_OUTPUT_BASE, - .map[1].output_ref[0] = SMMUV3_ID_MAP0_OUTPUT_REF, - .map[1].input_base[1] = SMMUV3_ID_MAP1_INPUT_BASE, - .map[1].id_count[1] = SMMUV3_ID_MAP1_ID_COUNT, - .map[1].output_base[1]= SMMUV3_ID_MAP1_OUTPUT_BASE, - .map[1].output_ref[1] = SMMUV3_ID_MAP1_OUTPUT_REF - -}; - -PLATFORM_OVERRIDE_NODE_DATA platform_node_type = { - .its_count = IOVIRT_ITS_COUNT, - .smmu.base = IOVIRT_SMMUV3_BASE_ADDRESS, - .smmu.context_interrupt_offset = IOVIRT_SMMU_CTX_INT_OFFSET, - .smmu.context_interrupt_count = IOVIRT_SMMU_CTX_INT_CNT, - .rc.segment = IOVIRT_RC_PCI_SEG_NUM, - .rc.cca = IOVIRT_RC_MEMORY_PROPERTIES, - .rc.ats_attr = IOVIRT_RC_ATS_ATTRIBUTE - -}; - -PLATFORM_OVERRIDE_UART_INFO_TABLE platform_uart_cfg = { - .Address = UART_ADDRESS, - .BaseAddress.Address = BASE_ADDRESS_ADDRESS, - .GlobalSystemInterrupt = UART_GLOBAL_SYSTEM_INTERRUPT, - .PciDeviceId = UART_PCI_DEVICE_ID, - .PciVendorId = UART_PCI_VENDOR_ID, - .PciBusNumber = UART_PCI_BUS_NUMBER, - .PciDeviceNumber = UART_PCI_DEV_NUMBER, - .PciFunctionNumber = UART_PCI_FUNC_NUMBER, - .PciFlags = UART_PCI_FLAGS, - .PciSegment = UART_PCI_SEGMENT -}; - -DMA_INFO_TABLE platform_dma_cfg = { - .num_dma_ctrls = PLATFORM_OVERRIDE_DMA_CNT - - /** Place holder - .info[0].target = TARGET, - .info[0].port = PORT, - .info[0].host = HOST, - .info[0].flags = FLAGS, - .info[0].type = TYPE**/ - -}; - -PLATFORM_OVERRIDE_MEMORY_INFO_TABLE platform_mem_cfg = { - .count = PLATFORM_OVERRIDE_MEMORY_ENTRY_COUNT, - .info[0].phy_addr = PLATFORM_OVERRIDE_MEMORY_ENTRY0_PHY_ADDR, - .info[0].virt_addr = PLATFORM_OVERRIDE_MEMORY_ENTRY0_VIRT_ADDR, - .info[0].size = PLATFORM_OVERRIDE_MEMORY_ENTRY0_SIZE, - .info[0].type = PLATFORM_OVERRIDE_MEMORY_ENTRY0_TYPE, - .info[1].phy_addr = PLATFORM_OVERRIDE_MEMORY_ENTRY1_PHY_ADDR, - .info[1].virt_addr = PLATFORM_OVERRIDE_MEMORY_ENTRY1_VIRT_ADDR, - .info[1].size = PLATFORM_OVERRIDE_MEMORY_ENTRY1_SIZE, - .info[1].type = PLATFORM_OVERRIDE_MEMORY_ENTRY1_TYPE, - .info[2].phy_addr = PLATFORM_OVERRIDE_MEMORY_ENTRY2_PHY_ADDR, - .info[2].virt_addr = PLATFORM_OVERRIDE_MEMORY_ENTRY2_VIRT_ADDR, - .info[2].size = PLATFORM_OVERRIDE_MEMORY_ENTRY2_SIZE, - .info[2].type = PLATFORM_OVERRIDE_MEMORY_ENTRY2_TYPE, - .info[3].phy_addr = PLATFORM_OVERRIDE_MEMORY_ENTRY3_PHY_ADDR, - .info[3].virt_addr = PLATFORM_OVERRIDE_MEMORY_ENTRY3_VIRT_ADDR, - .info[3].size = PLATFORM_OVERRIDE_MEMORY_ENTRY3_SIZE, - .info[3].type = PLATFORM_OVERRIDE_MEMORY_ENTRY3_TYPE, -}; - -PCIE_READ_TABLE platform_pcie_device_hierarchy = { - .num_entries = PLATFORM_PCIE_NUM_ENTRIES, - - .device[0].class_code = PLATFORM_PCIE_DEV0_CLASSCODE, - .device[0].vendor_id = PLATFORM_PCIE_DEV0_VENDOR_ID, - .device[0].device_id = PLATFORM_PCIE_DEV0_DEV_ID, - .device[0].bus = PLATFORM_PCIE_DEV0_BUS_NUM, - .device[0].dev = PLATFORM_PCIE_DEV0_DEV_NUM, - .device[0].func = PLATFORM_PCIE_DEV0_FUNC_NUM, - .device[0].seg = PLATFORM_PCIE_DEV0_SEG_NUM, - .device[0].dma_support = PLATFORM_PCIE_DEV0_DMA_SUPPORT, - .device[0].dma_coherent = PLATFORM_PCIE_DEV0_DMA_COHERENT, - .device[0].p2p_support = PLATFORM_PCIE_DEV0_P2P_SUPPORT, - .device[0].dma_64bit = PLATFORM_PCIE_DEV0_DMA_64BIT, - .device[0].behind_smmu = PLATFORM_PCIE_DEV0_BEHIND_SMMU, - .device[0].atc_present = PLATFORM_PCIE_DEV0_ATC_SUPPORT, - - .device[1].class_code = PLATFORM_PCIE_DEV1_CLASSCODE, - .device[1].vendor_id = PLATFORM_PCIE_DEV1_VENDOR_ID, - .device[1].device_id = PLATFORM_PCIE_DEV1_DEV_ID, - .device[1].bus = PLATFORM_PCIE_DEV1_BUS_NUM, - .device[1].dev = PLATFORM_PCIE_DEV1_DEV_NUM, - .device[1].func = PLATFORM_PCIE_DEV1_FUNC_NUM, - .device[1].seg = PLATFORM_PCIE_DEV1_SEG_NUM, - .device[1].dma_support = PLATFORM_PCIE_DEV1_DMA_SUPPORT, - .device[1].dma_coherent = PLATFORM_PCIE_DEV1_DMA_COHERENT, - .device[1].p2p_support = PLATFORM_PCIE_DEV1_P2P_SUPPORT, - .device[1].dma_64bit = PLATFORM_PCIE_DEV1_DMA_64BIT, - .device[1].behind_smmu = PLATFORM_PCIE_DEV1_BEHIND_SMMU, - .device[1].atc_present = PLATFORM_PCIE_DEV1_ATC_SUPPORT, - - .device[2].class_code = PLATFORM_PCIE_DEV2_CLASSCODE, - .device[2].vendor_id = PLATFORM_PCIE_DEV2_VENDOR_ID, - .device[2].device_id = PLATFORM_PCIE_DEV2_DEV_ID, - .device[2].bus = PLATFORM_PCIE_DEV2_BUS_NUM, - .device[2].dev = PLATFORM_PCIE_DEV2_DEV_NUM, - .device[2].func = PLATFORM_PCIE_DEV2_FUNC_NUM, - .device[2].seg = PLATFORM_PCIE_DEV2_SEG_NUM, - .device[2].dma_support = PLATFORM_PCIE_DEV2_DMA_SUPPORT, - .device[2].dma_coherent = PLATFORM_PCIE_DEV2_DMA_COHERENT, - .device[2].p2p_support = PLATFORM_PCIE_DEV2_P2P_SUPPORT, - .device[2].dma_64bit = PLATFORM_PCIE_DEV2_DMA_64BIT, - .device[2].behind_smmu = PLATFORM_PCIE_DEV2_BEHIND_SMMU, - .device[2].atc_present = PLATFORM_PCIE_DEV2_ATC_SUPPORT, - - .device[3].class_code = PLATFORM_PCIE_DEV3_CLASSCODE, - .device[3].vendor_id = PLATFORM_PCIE_DEV3_VENDOR_ID, - .device[3].device_id = PLATFORM_PCIE_DEV3_DEV_ID, - .device[3].bus = PLATFORM_PCIE_DEV3_BUS_NUM, - .device[3].dev = PLATFORM_PCIE_DEV3_DEV_NUM, - .device[3].func = PLATFORM_PCIE_DEV3_FUNC_NUM, - .device[3].seg = PLATFORM_PCIE_DEV3_SEG_NUM, - .device[3].dma_support = PLATFORM_PCIE_DEV3_DMA_SUPPORT, - .device[3].dma_coherent = PLATFORM_PCIE_DEV3_DMA_COHERENT, - .device[3].p2p_support = PLATFORM_PCIE_DEV3_P2P_SUPPORT, - .device[3].dma_64bit = PLATFORM_PCIE_DEV3_DMA_64BIT, - .device[3].behind_smmu = PLATFORM_PCIE_DEV3_BEHIND_SMMU, - .device[3].atc_present = PLATFORM_PCIE_DEV3_ATC_SUPPORT, - /* IRQ list of interrupt pin INTC# */ - .device[3].irq_map.legacy_irq_map[2].irq_count = 1, - .device[3].irq_map.legacy_irq_map[2].irq_list[0] = 200, - - .device[4].class_code = PLATFORM_PCIE_DEV4_CLASSCODE, - .device[4].vendor_id = PLATFORM_PCIE_DEV4_VENDOR_ID, - .device[4].device_id = PLATFORM_PCIE_DEV4_DEV_ID, - .device[4].bus = PLATFORM_PCIE_DEV4_BUS_NUM, - .device[4].dev = PLATFORM_PCIE_DEV4_DEV_NUM, - .device[4].func = PLATFORM_PCIE_DEV4_FUNC_NUM, - .device[4].seg = PLATFORM_PCIE_DEV4_SEG_NUM, - .device[4].dma_support = PLATFORM_PCIE_DEV4_DMA_SUPPORT, - .device[4].dma_coherent = PLATFORM_PCIE_DEV4_DMA_COHERENT, - .device[4].p2p_support = PLATFORM_PCIE_DEV4_P2P_SUPPORT, - .device[4].dma_64bit = PLATFORM_PCIE_DEV4_DMA_64BIT, - .device[4].behind_smmu = PLATFORM_PCIE_DEV4_BEHIND_SMMU, - .device[4].atc_present = PLATFORM_PCIE_DEV4_ATC_SUPPORT, - - .device[5].class_code = PLATFORM_PCIE_DEV5_CLASSCODE, - .device[5].vendor_id = PLATFORM_PCIE_DEV5_VENDOR_ID, - .device[5].device_id = PLATFORM_PCIE_DEV5_DEV_ID, - .device[5].bus = PLATFORM_PCIE_DEV5_BUS_NUM, - .device[5].dev = PLATFORM_PCIE_DEV5_DEV_NUM, - .device[5].func = PLATFORM_PCIE_DEV5_FUNC_NUM, - .device[5].seg = PLATFORM_PCIE_DEV5_SEG_NUM, - .device[5].dma_support = PLATFORM_PCIE_DEV5_DMA_SUPPORT, - .device[5].dma_coherent = PLATFORM_PCIE_DEV5_DMA_COHERENT, - .device[5].p2p_support = PLATFORM_PCIE_DEV5_P2P_SUPPORT, - .device[5].dma_64bit = PLATFORM_PCIE_DEV5_DMA_64BIT, - .device[5].behind_smmu = PLATFORM_PCIE_DEV5_BEHIND_SMMU, - .device[5].atc_present = PLATFORM_PCIE_DEV5_ATC_SUPPORT, - - .device[6].class_code = PLATFORM_PCIE_DEV6_CLASSCODE, - .device[6].vendor_id = PLATFORM_PCIE_DEV6_VENDOR_ID, - .device[6].device_id = PLATFORM_PCIE_DEV6_DEV_ID, - .device[6].bus = PLATFORM_PCIE_DEV6_BUS_NUM, - .device[6].dev = PLATFORM_PCIE_DEV6_DEV_NUM, - .device[6].func = PLATFORM_PCIE_DEV6_FUNC_NUM, - .device[6].seg = PLATFORM_PCIE_DEV6_SEG_NUM, - .device[6].dma_support = PLATFORM_PCIE_DEV6_DMA_SUPPORT, - .device[6].dma_coherent = PLATFORM_PCIE_DEV6_DMA_COHERENT, - .device[6].p2p_support = PLATFORM_PCIE_DEV6_P2P_SUPPORT, - .device[6].dma_64bit = PLATFORM_PCIE_DEV6_DMA_64BIT, - .device[6].behind_smmu = PLATFORM_PCIE_DEV6_BEHIND_SMMU, - .device[6].atc_present = PLATFORM_PCIE_DEV6_ATC_SUPPORT, - - .device[7].class_code = PLATFORM_PCIE_DEV7_CLASSCODE, - .device[7].vendor_id = PLATFORM_PCIE_DEV7_VENDOR_ID, - .device[7].device_id = PLATFORM_PCIE_DEV7_DEV_ID, - .device[7].bus = PLATFORM_PCIE_DEV7_BUS_NUM, - .device[7].dev = PLATFORM_PCIE_DEV7_DEV_NUM, - .device[7].func = PLATFORM_PCIE_DEV7_FUNC_NUM, - .device[7].seg = PLATFORM_PCIE_DEV7_SEG_NUM, - .device[7].dma_support = PLATFORM_PCIE_DEV7_DMA_SUPPORT, - .device[7].dma_coherent = PLATFORM_PCIE_DEV7_DMA_COHERENT, - .device[7].p2p_support = PLATFORM_PCIE_DEV7_P2P_SUPPORT, - .device[7].dma_64bit = PLATFORM_PCIE_DEV7_DMA_64BIT, - .device[7].behind_smmu = PLATFORM_PCIE_DEV7_BEHIND_SMMU, - .device[7].atc_present = PLATFORM_PCIE_DEV7_ATC_SUPPORT, - /* IRQ list of interrupt pin INTC# */ - .device[7].irq_map.legacy_irq_map[2].irq_count = 1, - .device[7].irq_map.legacy_irq_map[2].irq_list[0] = 200, - - .device[8].class_code = PLATFORM_PCIE_DEV8_CLASSCODE, - .device[8].vendor_id = PLATFORM_PCIE_DEV8_VENDOR_ID, - .device[8].device_id = PLATFORM_PCIE_DEV8_DEV_ID, - .device[8].bus = PLATFORM_PCIE_DEV8_BUS_NUM, - .device[8].dev = PLATFORM_PCIE_DEV8_DEV_NUM, - .device[8].func = PLATFORM_PCIE_DEV8_FUNC_NUM, - .device[8].seg = PLATFORM_PCIE_DEV8_SEG_NUM, - .device[8].dma_support = PLATFORM_PCIE_DEV8_DMA_SUPPORT, - .device[8].dma_coherent = PLATFORM_PCIE_DEV8_DMA_COHERENT, - .device[8].p2p_support = PLATFORM_PCIE_DEV8_P2P_SUPPORT, - .device[8].dma_64bit = PLATFORM_PCIE_DEV8_DMA_64BIT, - .device[8].behind_smmu = PLATFORM_PCIE_DEV8_BEHIND_SMMU, - .device[8].atc_present = PLATFORM_PCIE_DEV8_ATC_SUPPORT, - /* IRQ list of interrupt pin INTC# */ - .device[8].irq_map.legacy_irq_map[2].irq_count = 1, - .device[8].irq_map.legacy_irq_map[2].irq_list[0] = 200, - - .device[9].class_code = PLATFORM_PCIE_DEV9_CLASSCODE, - .device[9].vendor_id = PLATFORM_PCIE_DEV9_VENDOR_ID, - .device[9].device_id = PLATFORM_PCIE_DEV9_DEV_ID, - .device[9].bus = PLATFORM_PCIE_DEV9_BUS_NUM, - .device[9].dev = PLATFORM_PCIE_DEV9_DEV_NUM, - .device[9].func = PLATFORM_PCIE_DEV9_FUNC_NUM, - .device[9].seg = PLATFORM_PCIE_DEV9_SEG_NUM, - .device[9].dma_support = PLATFORM_PCIE_DEV9_DMA_SUPPORT, - .device[9].dma_coherent = PLATFORM_PCIE_DEV9_DMA_COHERENT, - .device[9].p2p_support = PLATFORM_PCIE_DEV9_P2P_SUPPORT, - .device[9].dma_64bit = PLATFORM_PCIE_DEV9_DMA_64BIT, - .device[9].behind_smmu = PLATFORM_PCIE_DEV9_BEHIND_SMMU, - .device[9].atc_present = PLATFORM_PCIE_DEV9_ATC_SUPPORT, - - .device[10].class_code = PLATFORM_PCIE_DEV10_CLASSCODE, - .device[10].vendor_id = PLATFORM_PCIE_DEV10_VENDOR_ID, - .device[10].device_id = PLATFORM_PCIE_DEV10_DEV_ID, - .device[10].bus = PLATFORM_PCIE_DEV10_BUS_NUM, - .device[10].dev = PLATFORM_PCIE_DEV10_DEV_NUM, - .device[10].func = PLATFORM_PCIE_DEV10_FUNC_NUM, - .device[10].seg = PLATFORM_PCIE_DEV10_SEG_NUM, - .device[10].dma_support = PLATFORM_PCIE_DEV10_DMA_SUPPORT, - .device[10].dma_coherent = PLATFORM_PCIE_DEV10_DMA_COHERENT, - .device[10].p2p_support = PLATFORM_PCIE_DEV10_P2P_SUPPORT, - .device[10].dma_64bit = PLATFORM_PCIE_DEV10_DMA_64BIT, - .device[10].behind_smmu = PLATFORM_PCIE_DEV10_BEHIND_SMMU, - .device[10].atc_present = PLATFORM_PCIE_DEV10_ATC_SUPPORT, - - .device[11].class_code = PLATFORM_PCIE_DEV11_CLASSCODE, - .device[11].vendor_id = PLATFORM_PCIE_DEV11_VENDOR_ID, - .device[11].device_id = PLATFORM_PCIE_DEV11_DEV_ID, - .device[11].bus = PLATFORM_PCIE_DEV11_BUS_NUM, - .device[11].dev = PLATFORM_PCIE_DEV11_DEV_NUM, - .device[11].func = PLATFORM_PCIE_DEV11_FUNC_NUM, - .device[11].seg = PLATFORM_PCIE_DEV11_SEG_NUM, - .device[11].dma_support = PLATFORM_PCIE_DEV11_DMA_SUPPORT, - .device[11].dma_coherent = PLATFORM_PCIE_DEV11_DMA_COHERENT, - .device[11].p2p_support = PLATFORM_PCIE_DEV11_P2P_SUPPORT, - .device[11].dma_64bit = PLATFORM_PCIE_DEV11_DMA_64BIT, - .device[11].behind_smmu = PLATFORM_PCIE_DEV11_BEHIND_SMMU, - .device[11].atc_present = PLATFORM_PCIE_DEV11_ATC_SUPPORT, - - .device[12].class_code = PLATFORM_PCIE_DEV12_CLASSCODE, - .device[12].vendor_id = PLATFORM_PCIE_DEV12_VENDOR_ID, - .device[12].device_id = PLATFORM_PCIE_DEV12_DEV_ID, - .device[12].bus = PLATFORM_PCIE_DEV12_BUS_NUM, - .device[12].dev = PLATFORM_PCIE_DEV12_DEV_NUM, - .device[12].func = PLATFORM_PCIE_DEV12_FUNC_NUM, - .device[12].seg = PLATFORM_PCIE_DEV12_SEG_NUM, - .device[12].dma_support = PLATFORM_PCIE_DEV12_DMA_SUPPORT, - .device[12].dma_coherent = PLATFORM_PCIE_DEV12_DMA_COHERENT, - .device[12].p2p_support = PLATFORM_PCIE_DEV12_P2P_SUPPORT, - .device[12].dma_64bit = PLATFORM_PCIE_DEV12_DMA_64BIT, - .device[12].behind_smmu = PLATFORM_PCIE_DEV12_BEHIND_SMMU, - .device[12].atc_present = PLATFORM_PCIE_DEV12_ATC_SUPPORT, - - .device[13].class_code = PLATFORM_PCIE_DEV13_CLASSCODE, - .device[13].vendor_id = PLATFORM_PCIE_DEV13_VENDOR_ID, - .device[13].device_id = PLATFORM_PCIE_DEV13_DEV_ID, - .device[13].bus = PLATFORM_PCIE_DEV13_BUS_NUM, - .device[13].dev = PLATFORM_PCIE_DEV13_DEV_NUM, - .device[13].func = PLATFORM_PCIE_DEV13_FUNC_NUM, - .device[13].seg = PLATFORM_PCIE_DEV13_SEG_NUM, - .device[13].dma_support = PLATFORM_PCIE_DEV13_DMA_SUPPORT, - .device[13].dma_coherent = PLATFORM_PCIE_DEV13_DMA_COHERENT, - .device[13].p2p_support = PLATFORM_PCIE_DEV13_P2P_SUPPORT, - .device[13].dma_64bit = PLATFORM_PCIE_DEV13_DMA_64BIT, - .device[13].behind_smmu = PLATFORM_PCIE_DEV13_BEHIND_SMMU, - .device[13].atc_present = PLATFORM_PCIE_DEV13_ATC_SUPPORT, - - .device[14].class_code = PLATFORM_PCIE_DEV14_CLASSCODE, - .device[14].vendor_id = PLATFORM_PCIE_DEV14_VENDOR_ID, - .device[14].device_id = PLATFORM_PCIE_DEV14_DEV_ID, - .device[14].bus = PLATFORM_PCIE_DEV14_BUS_NUM, - .device[14].dev = PLATFORM_PCIE_DEV14_DEV_NUM, - .device[14].func = PLATFORM_PCIE_DEV14_FUNC_NUM, - .device[14].seg = PLATFORM_PCIE_DEV14_SEG_NUM, - .device[14].dma_support = PLATFORM_PCIE_DEV14_DMA_SUPPORT, - .device[14].dma_coherent = PLATFORM_PCIE_DEV14_DMA_COHERENT, - .device[14].p2p_support = PLATFORM_PCIE_DEV14_P2P_SUPPORT, - .device[14].dma_64bit = PLATFORM_PCIE_DEV14_DMA_64BIT, - .device[14].behind_smmu = PLATFORM_PCIE_DEV14_BEHIND_SMMU, - .device[14].atc_present = PLATFORM_PCIE_DEV14_ATC_SUPPORT, - /* IRQ list of interrupt pin INTA# */ - .device[14].irq_map.legacy_irq_map[0].irq_count = 1, - .device[14].irq_map.legacy_irq_map[0].irq_list[0] = 500, - - .device[15].class_code = PLATFORM_PCIE_DEV15_CLASSCODE, - .device[15].vendor_id = PLATFORM_PCIE_DEV15_VENDOR_ID, - .device[15].device_id = PLATFORM_PCIE_DEV15_DEV_ID, - .device[15].bus = PLATFORM_PCIE_DEV15_BUS_NUM, - .device[15].dev = PLATFORM_PCIE_DEV15_DEV_NUM, - .device[15].func = PLATFORM_PCIE_DEV15_FUNC_NUM, - .device[15].seg = PLATFORM_PCIE_DEV15_SEG_NUM, - .device[15].dma_support = PLATFORM_PCIE_DEV15_DMA_SUPPORT, - .device[15].dma_coherent = PLATFORM_PCIE_DEV15_DMA_COHERENT, - .device[15].p2p_support = PLATFORM_PCIE_DEV15_P2P_SUPPORT, - .device[15].dma_64bit = PLATFORM_PCIE_DEV15_DMA_64BIT, - .device[15].behind_smmu = PLATFORM_PCIE_DEV15_BEHIND_SMMU, - .device[15].atc_present = PLATFORM_PCIE_DEV15_ATC_SUPPORT, - - .device[16].class_code = PLATFORM_PCIE_DEV16_CLASSCODE, - .device[16].vendor_id = PLATFORM_PCIE_DEV16_VENDOR_ID, - .device[16].device_id = PLATFORM_PCIE_DEV16_DEV_ID, - .device[16].bus = PLATFORM_PCIE_DEV16_BUS_NUM, - .device[16].dev = PLATFORM_PCIE_DEV16_DEV_NUM, - .device[16].func = PLATFORM_PCIE_DEV16_FUNC_NUM, - .device[16].seg = PLATFORM_PCIE_DEV16_SEG_NUM, - .device[16].dma_support = PLATFORM_PCIE_DEV16_DMA_SUPPORT, - .device[16].dma_coherent = PLATFORM_PCIE_DEV16_DMA_COHERENT, - .device[16].p2p_support = PLATFORM_PCIE_DEV16_P2P_SUPPORT, - .device[16].dma_64bit = PLATFORM_PCIE_DEV16_DMA_64BIT, - .device[16].behind_smmu = PLATFORM_PCIE_DEV16_BEHIND_SMMU, - .device[16].atc_present = PLATFORM_PCIE_DEV16_ATC_SUPPORT, - - .device[17].class_code = PLATFORM_PCIE_DEV17_CLASSCODE, - .device[17].vendor_id = PLATFORM_PCIE_DEV17_VENDOR_ID, - .device[17].device_id = PLATFORM_PCIE_DEV17_DEV_ID, - .device[17].bus = PLATFORM_PCIE_DEV17_BUS_NUM, - .device[17].dev = PLATFORM_PCIE_DEV17_DEV_NUM, - .device[17].func = PLATFORM_PCIE_DEV17_FUNC_NUM, - .device[17].seg = PLATFORM_PCIE_DEV17_SEG_NUM, - .device[17].dma_support = PLATFORM_PCIE_DEV17_DMA_SUPPORT, - .device[17].dma_coherent = PLATFORM_PCIE_DEV17_DMA_COHERENT, - .device[17].p2p_support = PLATFORM_PCIE_DEV17_P2P_SUPPORT, - .device[17].dma_64bit = PLATFORM_PCIE_DEV17_DMA_64BIT, - .device[17].behind_smmu = PLATFORM_PCIE_DEV17_BEHIND_SMMU, - .device[17].atc_present = PLATFORM_PCIE_DEV17_ATC_SUPPORT, - - .device[18].class_code = PLATFORM_PCIE_DEV18_CLASSCODE, - .device[18].vendor_id = PLATFORM_PCIE_DEV18_VENDOR_ID, - .device[18].device_id = PLATFORM_PCIE_DEV18_DEV_ID, - .device[18].bus = PLATFORM_PCIE_DEV18_BUS_NUM, - .device[18].dev = PLATFORM_PCIE_DEV18_DEV_NUM, - .device[18].func = PLATFORM_PCIE_DEV18_FUNC_NUM, - .device[18].seg = PLATFORM_PCIE_DEV18_SEG_NUM, - .device[18].dma_support = PLATFORM_PCIE_DEV18_DMA_SUPPORT, - .device[18].dma_coherent = PLATFORM_PCIE_DEV18_DMA_COHERENT, - .device[18].p2p_support = PLATFORM_PCIE_DEV18_P2P_SUPPORT, - .device[18].dma_64bit = PLATFORM_PCIE_DEV18_DMA_64BIT, - .device[18].behind_smmu = PLATFORM_PCIE_DEV18_BEHIND_SMMU, - .device[18].atc_present = PLATFORM_PCIE_DEV18_ATC_SUPPORT, - - .device[19].class_code = PLATFORM_PCIE_DEV19_CLASSCODE, - .device[19].vendor_id = PLATFORM_PCIE_DEV19_VENDOR_ID, - .device[19].device_id = PLATFORM_PCIE_DEV19_DEV_ID, - .device[19].bus = PLATFORM_PCIE_DEV19_BUS_NUM, - .device[19].dev = PLATFORM_PCIE_DEV19_DEV_NUM, - .device[19].func = PLATFORM_PCIE_DEV19_FUNC_NUM, - .device[19].seg = PLATFORM_PCIE_DEV19_SEG_NUM, - .device[19].dma_support = PLATFORM_PCIE_DEV19_DMA_SUPPORT, - .device[19].dma_coherent = PLATFORM_PCIE_DEV19_DMA_COHERENT, - .device[19].p2p_support = PLATFORM_PCIE_DEV19_P2P_SUPPORT, - .device[19].dma_64bit = PLATFORM_PCIE_DEV19_DMA_64BIT, - .device[19].behind_smmu = PLATFORM_PCIE_DEV19_BEHIND_SMMU, - .device[19].atc_present = PLATFORM_PCIE_DEV19_ATC_SUPPORT, - - .device[20].class_code = PLATFORM_PCIE_DEV20_CLASSCODE, - .device[20].vendor_id = PLATFORM_PCIE_DEV20_VENDOR_ID, - .device[20].device_id = PLATFORM_PCIE_DEV20_DEV_ID, - .device[20].bus = PLATFORM_PCIE_DEV20_BUS_NUM, - .device[20].dev = PLATFORM_PCIE_DEV20_DEV_NUM, - .device[20].func = PLATFORM_PCIE_DEV20_FUNC_NUM, - .device[20].seg = PLATFORM_PCIE_DEV20_SEG_NUM, - .device[20].dma_support = PLATFORM_PCIE_DEV20_DMA_SUPPORT, - .device[20].dma_coherent = PLATFORM_PCIE_DEV20_DMA_COHERENT, - .device[20].p2p_support = PLATFORM_PCIE_DEV20_P2P_SUPPORT, - .device[20].dma_64bit = PLATFORM_PCIE_DEV20_DMA_64BIT, - .device[20].behind_smmu = PLATFORM_PCIE_DEV20_BEHIND_SMMU, - .device[20].atc_present = PLATFORM_PCIE_DEV20_ATC_SUPPORT, -}; diff --git a/platform/pal_baremetal/FVP/src/pal_bm_exerciser.c b/platform/pal_baremetal/FVP/src/pal_bm_exerciser.c deleted file mode 100644 index 61233cb0..00000000 --- a/platform/pal_baremetal/FVP/src/pal_bm_exerciser.c +++ /dev/null @@ -1,124 +0,0 @@ -/** @file - * Copyright (c) 2023,Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" -#include "include/platform_override_struct.h" - -uint64_t -pal_exerciser_get_ecam(uint32_t Bdf); - -uint64_t -pal_exerciser_get_pcie_config_offset(uint32_t Bdf); - -uint64_t -pal_exerciser_get_ecsr_base(uint32_t Bdf, uint32_t BarIndex); - -uint32_t -pal_exerciser_find_pcie_capability (uint32_t ID, uint32_t Bdf, uint32_t Value, uint32_t *Offset); -/** - @brief This API returns if the device is a exerciser - @param bdf - Bus/Device/Function - @return 1 - true 0 - false -**/ -uint32_t -pal_is_bdf_exerciser(uint32_t bdf) -{ - return 0; -} - -/** - @brief This API writes the configuration parameters of the PCIe stimulus generation hardware - @param Type - Parameter type that needs to be set in the stimulus hadrware - @param Value1 - Parameter 1 that needs to be set - @param Value2 - Parameter 2 that needs to be set - @param Instance - Stimulus hardware instance number - @return Status - SUCCESS if the input paramter type is successfully written -**/ -uint32_t pal_exerciser_set_param(EXERCISER_PARAM_TYPE Type, uint64_t Value1, uint64_t Value2, uint32_t Bdf) -{ - return 1; -} - -/** - @brief This function triggers the DMA operation -**/ -uint32_t pal_exerciser_start_dma_direction (uint64_t Base, EXERCISER_DMA_ATTR Direction) -{ - return 0; -} - - -/** - @brief This API reads the configuration parameters of the PCIe stimulus generation hardware - @param Type - Parameter type that needs to be read from the stimulus hadrware - @param Value1 - Parameter 1 that is read from hardware - @param Value2 - Parameter 2 that is read from hardware - @param Instance - Stimulus hardware instance number - @return Status - SUCCESS if the requested paramter type is successfully read -**/ -uint32_t pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, uint64_t *Value1, uint64_t *Value2, uint32_t Bdf) -{ - return 0; -} - -/** - @brief This API obtains the state of the PCIe stimulus generation hardware - @param State - State that is read from the stimulus hadrware - @param Bdf - Stimulus hardware bdf number - @return Status - SUCCESS if the state is successfully read from hardware -**/ -uint32_t pal_exerciser_get_state(EXERCISER_STATE *State, uint32_t Bdf) -{ - return 0; -} - -/** - @brief This API performs the input operation using the PCIe stimulus generation hardware - @param Ops - Operation thta needs to be performed with the stimulus hadrware - @param Value - Additional information to perform the operation - @param Instance - Stimulus hardware instance number - @return Status - SUCCESS if the operation is successfully performed using the hardware -**/ -uint32_t pal_exerciser_ops(EXERCISER_OPS Ops, uint64_t Param, uint32_t Bdf) -{ - return 1; -} - -/** - @brief This API sets the state of the PCIe stimulus generation hardware - @param State - State that needs to be set for the stimulus hadrware - @param Value - Additional information associated with the state - @param Instance - Stimulus hardware instance number - @return Status - SUCCESS if the input state is successfully written to hardware -**/ -uint32_t pal_exerciser_set_state (EXERCISER_STATE State, uint64_t *Value, uint32_t Instance) -{ - return 0; -} - -/** - @brief This API returns test specific data from the PCIe stimulus generation hardware - @param type - data type for which the data needs to be returned - @param data - test specific data to be be filled by pal layer - @param instance - Stimulus hardware instance number - @return status - SUCCESS if the requested data is successfully filled -**/ -uint32_t pal_exerciser_get_data(EXERCISER_DATA_TYPE Type, exerciser_data_t *Data, uint32_t Bdf, uint64_t Ecam) -{ - return NOT_IMPLEMENTED; -} diff --git a/platform/pal_baremetal/RDN2/include/platform_image_def.h b/platform/pal_baremetal/RDN2/include/platform_image_def.h new file mode 100644 index 00000000..d52be4b8 --- /dev/null +++ b/platform/pal_baremetal/RDN2/include/platform_image_def.h @@ -0,0 +1,44 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#ifndef _PAL_CONFIG_H_ +#define _PAL_CONFIG_H_ + +/* + * Device Info in physical addresses. + */ +#define PLATFORM_NORMAL_WORLD_IMAGE_SIZE 0x4000000 +#define PLATFORM_HOST_IMAGE_SIZE (PLATFORM_NORMAL_WORLD_IMAGE_SIZE / 2) +#define PLATFORM_MEMORY_POOL_SIZE (250 * 0x100000) +#define PLATFORM_SHARED_REGION_SIZE 0x100000 +#define PLATFORM_HEAP_REGION_SIZE (PLATFORM_MEMORY_POOL_SIZE \ + - PLATFORM_SHARED_REGION_SIZE) + +/* + * Run-time address of the ACS Non-secure image. It has to match + * the location where the DUT software loads the ACS NS Image. + */ +#define PLATFORM_NORMAL_WORLD_IMAGE_BASE 0xE0000000 +#define PLATFORM_HOST_IMAGE_BASE PLATFORM_NORMAL_WORLD_IMAGE_BASE +#define PLATFORM_MEMORY_POOL_BASE (PLATFORM_NORMAL_WORLD_IMAGE_BASE \ + + PLATFORM_NORMAL_WORLD_IMAGE_SIZE) + +#define PLATFORM_SHARED_REGION_BASE PLATFORM_MEMORY_POOL_BASE +#define PLATFORM_HEAP_REGION_BASE (PLATFORM_SHARED_REGION_BASE + \ + PLATFORM_SHARED_REGION_SIZE) + +#endif /* _PAL_CONFIG_H_ */ diff --git a/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h b/platform/pal_baremetal/RDN2/include/platform_override_fvp.h similarity index 99% rename from platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h rename to platform/pal_baremetal/RDN2/include/platform_override_fvp.h index e3e92126..53e7cbc1 100644 --- a/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h +++ b/platform/pal_baremetal/RDN2/include/platform_override_fvp.h @@ -15,26 +15,22 @@ * limitations under the License. **/ -#include -#include - -/** Begin config **/ - -extern uint32_t g_skip_array[]; -extern uint32_t g_num_skip; -extern uint32_t g_test_array[]; -extern uint32_t g_num_tests; -extern uint32_t g_module_array[]; -extern uint32_t g_num_modules; - /* Settings */ #define PLATFORM_OVERRIDE_SBSA_LEVEL 0x7 //The permissible levels are 3,4,5,6 and 7 #define PLATFORM_OVERRIDE_PRINT_LEVEL 0x3 //The permissible levels are 1,2,3,4 and 5 /* PCIe BAR config parameters*/ -#define PLATFORM_OVERRIDE_PCIE_BAR64_VAL 0x4000000000 +#define PLATFORM_OVERRIDE_PCIE_BAR64_VAL 0x4000100000 +#define PLATFORM_OVERRIDE_RP_BAR64_VAL 0x4000000000 #define PLATFORM_OVERRIDE_PCIE_BAR32NP_VAL 0x60000000 -#define PLATFORM_OVERRIDE_PCIE_BAR32P_VAL 0x60500000 +#define PLATFORM_OVERRIDE_PCIE_BAR32P_VAL 0x60600000 +#define PLATOFRM_OVERRIDE_RP_BAR32_VAL 0x60850000 + + +/* MMU PGT config parameters */ +#define PLATFORM_PAGE_SIZE 0x1000 +#define PLATFORM_OVERRIDE_MMU_PGT_IAS 48 +#define PLATFORM_OVERRIDE_MMU_PGT_OAS 48 /* PE platform config paramaters */ #define PLATFORM_OVERRIDE_PE_CNT 16 @@ -559,6 +555,8 @@ extern uint32_t g_num_modules; #define BASE_ADDRESS_REGISTER_BIT_OFFSET 0x0 #define BASE_ADDRESS_ADDRESS_SIZE 0x3 #define BASE_ADDRESS_ADDRESS 0x2A400000 +#define UART_BAUD_RATE 115200 +#define UART_CLK_RATE_HZ 24000000 #define UART_INTERRUPT_TYPE 8 #define UART_IRQ 0 #define UART_GLOBAL_SYSTEM_INTERRUPT 0x70 @@ -571,7 +569,7 @@ extern uint32_t g_num_modules; #define UART_PCI_SEGMENT 0x0 /* IOVIRT platform config parameters */ -#define IOVIRT_ADDRESS 0xF981EB18 +#define IOVIRT_ADDRESS 0xF98DEB18 #define IORT_NODE_COUNT 13 #define NUM_ITS_COUNT 5 #define IOVIRT_ITS_COUNT 1 diff --git a/platform/pal_baremetal/FVP/RDN2/include/platform_override_struct.h b/platform/pal_baremetal/RDN2/include/platform_override_struct.h similarity index 100% rename from platform/pal_baremetal/FVP/RDN2/include/platform_override_struct.h rename to platform/pal_baremetal/RDN2/include/platform_override_struct.h diff --git a/platform/pal_baremetal/FVP/src/pal_bm_dma.c b/platform/pal_baremetal/RDN2/src/pal_bm_dma.c similarity index 83% rename from platform/pal_baremetal/FVP/src/pal_bm_dma.c rename to platform/pal_baremetal/RDN2/src/pal_bm_dma.c index 49c67625..244e8e06 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_dma.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_dma.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,8 +16,8 @@ **/ -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" /** @@ -34,9 +34,13 @@ uint64_t pal_dma_mem_alloc(void **buffer, uint32_t length, void *dev, uint32_t flag) { - *buffer = (void *)memalign(MEM_ALIGN_4K, length); + (void) dev; + (void) flag; - return 0; + uint32_t alignment = MEM_ALIGN_4K; + buffer = (void *)pal_aligned_alloc(alignment, length); + + return (uint64_t) buffer; } /** @@ -50,8 +54,11 @@ pal_dma_mem_alloc(void **buffer, uint32_t length, void *dev, uint32_t flag) **/ void pal_dma_mem_free(void *buffer, uint64_t mem_dma, unsigned int length, void *port, unsigned int flags) { - - free(buffer); + (void) mem_dma; + (void) length; + (void) port; + (void) flags; + pal_mem_free_aligned(buffer); return; } @@ -69,6 +76,11 @@ pal_dma_start_from_device(void *dma_target_buf, unsigned int length, void *host, void *dev) { + (void) dma_target_buf; + (void) length; + (void) host; + (void) dev; + return 0; } @@ -86,7 +98,14 @@ unsigned int pal_dma_start_to_device(void *dma_source_buf, unsigned int length, void *host, void *target, unsigned int timeout) { - return 0; + + (void) dma_source_buf; + (void) length; + (void) host; + (void) target; + (void) timeout; + + return 0; } /** @@ -105,6 +124,11 @@ pal_dma_scsi_get_dma_addr(void *port, void *dma_addr, unsigned int *dma_len) /* *dma_addr = dma_address; * *dma_len = dma_length; */ + (void) port; + (void) dma_addr; + (void) dma_len; + + return; } /** @@ -124,5 +148,9 @@ pal_dma_mem_get_attrs(void *buf, uint32_t *attr, uint32_t *sh) * and shareable domain (sh) */ + (void) buf; + (void) attr; + (void) sh; + return 1; } diff --git a/platform/pal_baremetal/RDN2/src/pal_bm_exerciser.c b/platform/pal_baremetal/RDN2/src/pal_bm_exerciser.c new file mode 100644 index 00000000..3a36404f --- /dev/null +++ b/platform/pal_baremetal/RDN2/src/pal_bm_exerciser.c @@ -0,0 +1,517 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include "pal_common_support.h" +#include "pal_pcie_enum.h" +#include "platform_override_struct.h" + +uint64_t +pal_exerciser_get_ecam(uint32_t Bdf); + +uint64_t +pal_exerciser_get_pcie_config_offset(uint32_t Bdf); + +uint64_t +pal_exerciser_get_ecsr_base(uint32_t Bdf, uint32_t BarIndex); + +uint32_t +pal_exerciser_find_pcie_capability (uint32_t ID, uint32_t Bdf, uint32_t Value, uint32_t *Offset); +/** + @brief This API returns if the device is a exerciser + @param bdf - Bus/Device/Function + @return 1 - true 0 - false +**/ +uint32_t +pal_is_bdf_exerciser(uint32_t bdf) +{ + /* Below code is not applicable for Bare-metal + * Only for FVP OOB experience + */ + + uint64_t Ecam; + uint32_t vendor_dev_id; + Ecam = pal_exerciser_get_ecam(bdf); + + vendor_dev_id = pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(bdf)); + if (vendor_dev_id == EXERCISER_ID) + return 1; + else + return 0; +} + +/** + @brief This API writes the configuration parameters of the PCIe stimulus generation hardware + @param Type - Parameter type that needs to be set in the stimulus hadrware + @param Value1 - Parameter 1 that needs to be set + @param Value2 - Parameter 2 that needs to be set + @param Instance - Stimulus hardware instance number + @return Status - SUCCESS if the input paramter type is successfully written +**/ +uint32_t pal_exerciser_set_param(EXERCISER_PARAM_TYPE Type, uint64_t Value1, uint64_t Value2, uint32_t Bdf) +{ + /* Below code is not applicable for Bare-metal + * Only for FVP OOB experience + */ + + uint32_t CapabilityOffset = 0; + uint32_t Data; + uint64_t Base; + uint64_t Ecam; + + Base = pal_exerciser_get_ecsr_base(Bdf,0); + Ecam = pal_exerciser_get_ecam(Bdf); // Getting the ECAM address + + switch (Type) { + + case SNOOP_ATTRIBUTES: + return 0; + + case LEGACY_IRQ: + return 0; + + case DMA_ATTRIBUTES: + pal_mmio_write(Base + DMA_BUS_ADDR,Value1);// wrting into the DMA Control Register 2 + pal_mmio_write(Base + DMA_LEN,Value2);// writing into the DMA Control Register 3 + return 0; + + case P2P_ATTRIBUTES: + return 0; + + case PASID_ATTRIBUTES: + Data = pal_mmio_read(Base + DMACTL1); + Data &= ~(PASID_LEN_MASK << PASID_LEN_SHIFT); + Data |= ((Value1 - 16) & PASID_LEN_MASK) << PASID_LEN_SHIFT; + pal_mmio_write(Base + DMACTL1, Data); + return 0; + + case MSIX_ATTRIBUTES: + return 0; + + case CFG_TXN_ATTRIBUTES: + switch (Value1) { + + case TXN_REQ_ID: + /* Change Requester ID for DMA Transaction.*/ + Data = (Value2 & RID_VALUE_MASK) | RID_VALID_MASK; + pal_mmio_write(Base + RID_CTL_REG, Data); + return 0; + case TXN_REQ_ID_VALID: + switch (Value2) + { + case RID_VALID: + Data = pal_mmio_read(Base + RID_CTL_REG); + Data |= RID_VALID_MASK; + pal_mmio_write(Base + RID_CTL_REG, Data); + return 0; + case RID_NOT_VALID: + pal_mmio_write(Base + RID_CTL_REG, 0); + return 0; + } + return 0; + case TXN_ADDR_TYPE: + /* Change Address Type for DMA Transaction.*/ + switch (Value2) + { + case AT_UNTRANSLATED: + Data = 0x1; + pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10)); + break; + case AT_TRANSLATED: + Data = 0x2; + pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10)); + break; + case AT_RESERVED: + Data = 0x3; + pal_mmio_write(Base + DMACTL1, pal_mmio_read(Base + DMACTL1) | (Data << 10)); + break; + } + return 0; + default: + return 1; + } + + case ERROR_INJECT_TYPE: + pal_exerciser_find_pcie_capability(DVSEC, Bdf, PCIE, &CapabilityOffset); + Data = pal_mmio_read(Ecam + CapabilityOffset + + pal_exerciser_get_pcie_config_offset(Bdf) + DVSEC_CTRL); + Data = ((Value1 << ERR_CODE_SHIFT) | (Value2 << FATAL_SHIFT)); + pal_mmio_write(Ecam + CapabilityOffset + DVSEC_CTRL + + pal_exerciser_get_pcie_config_offset(Bdf), Data); + if (Value1 <= 0x7) + return 2; + else + return 3; + default: + return 1; + } +} + +/** + @brief This function triggers the DMA operation +**/ +uint32_t pal_exerciser_start_dma_direction (uint64_t Base, EXERCISER_DMA_ATTR Direction) +{ + /* Below code is not applicable for Bare-metal + * Only for FVP OOB experience + */ + + uint32_t Mask; + uint32_t Status; + + if (Direction == EDMA_TO_DEVICE) { + + Mask = DMA_TO_DEVICE_MASK;// DMA direction:to Device + // Setting DMA direction in DMA control register 1 + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) & Mask)); + } + if (Direction == EDMA_FROM_DEVICE) { + Mask = (MASK_BIT << SHIFT_4BIT);// DMA direction:from device + // Setting DMA direction in DMA control register 1 + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) | Mask)); + } + // Triggering the DMA + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) | MASK_BIT)); + + // Reading the Status of the DMA + + Status = (pal_mmio_read(Base + DMASTATUS) & ((MASK_BIT << 1) | MASK_BIT)); + return Status; +} + +/** + @brief This API reads the configuration parameters of the PCIe stimulus generation hardware + @param Type - Parameter type that needs to be read from the stimulus hadrware + @param Value1 - Parameter 1 that is read from hardware + @param Value2 - Parameter 2 that is read from hardware + @param Instance - Stimulus hardware instance number + @return Status - SUCCESS if the requested paramter type is successfully read +**/ +uint32_t pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, uint64_t *Value1, uint64_t *Value2, uint32_t Bdf) +{ + /* Below code is not applicable for Bare-metal + * Only for FVP OOB experience + */ + + uint32_t Status; + uint32_t Temp; + uint64_t Base; + uint32_t tx_attr; + uint32_t addr_low = 0; + uint32_t addr_high = 0; + uint32_t data_low = 0; + uint32_t data_high = 0; + + Base = pal_exerciser_get_ecsr_base(Bdf,0); + switch (Type) { + + case SNOOP_ATTRIBUTES: + return 0; + case LEGACY_IRQ: + *Value1 = pal_mmio_read(Base + INTXCTL); + return pal_mmio_read(Base + INTXCTL) | MASK_BIT ; + case DMA_ATTRIBUTES: + *Value1 = pal_mmio_read(Base + DMA_BUS_ADDR); // Reading the data from DMA Control Register 2 + *Value2 = pal_mmio_read(Base + DMA_LEN); // Reading the data from DMA Control Register 3 + Temp = pal_mmio_read(Base + DMASTATUS); + Status = Temp & MASK_BIT;// returning the DMA status + return Status; + case P2P_ATTRIBUTES: + return 0; + case PASID_ATTRIBUTES: + *Value1 = ((pal_mmio_read(Base + DMACTL1) >> PASID_LEN_SHIFT) & PASID_LEN_MASK) + 16; + return 0; + case MSIX_ATTRIBUTES: + *Value1 = pal_mmio_read(Base + MSICTL); + return pal_mmio_read(Base + MSICTL) | MASK_BIT; + case ATS_RES_ATTRIBUTES: + *Value1 = pal_mmio_read(Base + ATS_ADDR); + return 0; + case CFG_TXN_ATTRIBUTES: + case TRANSACTION_TYPE: + case ADDRESS_ATTRIBUTES: + case DATA_ATTRIBUTES: + /* Get the first entry and check for validity */ + tx_attr = pal_mmio_read(Base + TXN_TRACE); + if (tx_attr == TXN_INVALID) + return 1; + + /* Obtain all the recorded information of the packet in the format. + ________________________________ + | TX ATTRIBUTES | + | CFG/MEM ADDRESS_LO | + | CFG/MEM ADDRESS_HI | + | DATA_LO | + | DATA_HI | + |________________________________| + */ + addr_low = pal_mmio_read(Base + TXN_TRACE); + addr_high = pal_mmio_read(Base + TXN_TRACE); + data_low = pal_mmio_read(Base + TXN_TRACE); + data_high = pal_mmio_read(Base + TXN_TRACE); + + if (Type == CFG_TXN_ATTRIBUTES) + *Value1 = tx_attr & MASK_BIT; + + /* 0 - Read, 1 - Write */ + else if (Type == TRANSACTION_TYPE) + if (tx_attr & 0x2) + *Value2 = CFG_READ; + else + *Value2 = CFG_WRITE; + + else if (Type == ADDRESS_ATTRIBUTES) + *Value1 = addr_low | ((uint64_t)addr_high << 32); + + else if (Type == DATA_ATTRIBUTES) + *Value1 = data_low | ((uint64_t)data_high << 32); + + return 0; + default: + return 1; + } +} + +/** + @brief This API obtains the state of the PCIe stimulus generation hardware + @param State - State that is read from the stimulus hadrware + @param Bdf - Stimulus hardware bdf number + @return Status - SUCCESS if the state is successfully read from hardware +**/ +uint32_t pal_exerciser_get_state(EXERCISER_STATE *State, uint32_t Bdf) +{ + /* Below code is not applicable for Bare-metal + * Only for FVP OOB experience + */ + (void) Bdf; + + *State = EXERCISER_ON; + return 0; +} + +/** + @brief This API performs the input operation using the PCIe stimulus generation hardware + @param Ops - Operation thta needs to be performed with the stimulus hadrware + @param Value - Additional information to perform the operation + @param Instance - Stimulus hardware instance number + @return Status - SUCCESS if the operation is successfully performed using the hardware +**/ +uint32_t pal_exerciser_ops(EXERCISER_OPS Ops, uint64_t Param, uint32_t Bdf) +{ + /* Below code is not applicable for Bare-metal + * Only for FVP OOB experience + */ + + uint64_t Base; + uint64_t Ecam; + uint32_t CapabilityOffset = 0; + uint32_t data; + + Base = pal_exerciser_get_ecsr_base(Bdf,0); + Ecam = pal_exerciser_get_ecam(Bdf); // Getting the ECAM address + + switch(Ops){ + + case START_DMA: + switch (Param) { + + case EDMA_NO_SUPPORT: + return 0; + case EDMA_COHERENT: + return 0; + case EDMA_NOT_COHERENT: + return 0; + case EDMA_FROM_DEVICE: + return pal_exerciser_start_dma_direction(Base, EDMA_FROM_DEVICE);// DMA from Device + case EDMA_TO_DEVICE: + return pal_exerciser_start_dma_direction(Base, EDMA_TO_DEVICE);// DMA to Device + default: + return 1; + } + + case GENERATE_MSI: + /* Param is the msi_index */ + pal_mmio_write( Base + MSICTL ,(pal_mmio_read(Base + MSICTL) | (MSI_GENERATION_MASK) | (Param))); + return 0; + + case GENERATE_L_INTR: + pal_mmio_write(Base + INTXCTL , (pal_mmio_read(Base + INTXCTL) | MASK_BIT)); + return 0; //Legacy interrupt + + case MEM_READ: + return 0; + + case MEM_WRITE: + return 0; + + case CLEAR_INTR: + pal_mmio_write(Base + INTXCTL , (pal_mmio_read(Base + INTXCTL) & CLR_INTR_MASK)); + return 0; + + case PASID_TLP_START: + data = pal_mmio_read(Base + DMACTL1); + data |= (MASK_BIT << PASID_EN_SHIFT); + pal_mmio_write(Base + DMACTL1, data); + data = ((Param & PASID_VAL_MASK)); + pal_mmio_write(Base + PASID_VAL, data); + + if (!pal_exerciser_find_pcie_capability(PASID, Bdf, PCIE, &CapabilityOffset)) { + + pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET, + (pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET)) | PCIE_CAP_EN_MASK); + return 0; + } + return 1; + + case PASID_TLP_STOP: + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) & PASID_TLP_STOP_MASK)); + + if (!pal_exerciser_find_pcie_capability(PASID, Bdf, PCIE, &CapabilityOffset)) { + pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET, + (pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET)) & PCIE_CAP_DIS_MASK); + return 0; + } + return 1; + + case TXN_NO_SNOOP_ENABLE: + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1)) | NO_SNOOP_START_MASK);//enabling the NO SNOOP + return 0; + + case TXN_NO_SNOOP_DISABLE: + pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1)) & NO_SNOOP_STOP_MASK);//disabling the NO SNOOP + return 0; + + case ATS_TXN_REQ: + pal_mmio_write(Base + DMA_BUS_ADDR, Param); + pal_mmio_write(Base + ATSCTL, ATS_TRIGGER); + return !(pal_mmio_read(Base + ATSCTL) & ATS_STATUS); + + case START_TXN_MONITOR: + pal_mmio_write(Base + TXN_CTRL_BASE, TXN_START); + return 0; + + case STOP_TXN_MONITOR: + pal_mmio_write(Base + TXN_CTRL_BASE, TXN_STOP); + return 0; + + case INJECT_ERROR: + pal_exerciser_find_pcie_capability(DVSEC, Bdf, PCIE, &CapabilityOffset); + data = pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + + CapabilityOffset + DVSEC_CTRL); + data = data | (1 << ERROR_INJECT_BIT); + pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + + DVSEC_CTRL, data); + return Param; + + default: + return PCIE_CAP_NOT_FOUND; + } +} + + + +/** + @brief This API sets the state of the PCIe stimulus generation hardware + @param State - State that needs to be set for the stimulus hadrware + @param Value - Additional information associated with the state + @param Instance - Stimulus hardware instance number + @return Status - SUCCESS if the input state is successfully written to hardware +**/ +uint32_t pal_exerciser_set_state (EXERCISER_STATE State, uint64_t *Value, uint32_t Instance) +{ + (void) State; + (void) Value; + (void) Instance; + + return 0; +} + +/** + @brief This API returns test specific data from the PCIe stimulus generation hardware + @param type - data type for which the data needs to be returned + @param data - test specific data to be be filled by pal layer + @param instance - Stimulus hardware instance number + @return status - SUCCESS if the requested data is successfully filled +**/ +uint32_t pal_exerciser_get_data(EXERCISER_DATA_TYPE Type, exerciser_data_t *Data, uint32_t Bdf, uint64_t Ecam) +{ + /* Below code is not applicable for Bare-metal + * Only for FVP OOB experience + */ + + uint32_t Index; + uint64_t EcamBase; + uint64_t EcamBAR0; + uint64_t EcamBAR; + + EcamBase = (Ecam + pal_exerciser_get_pcie_config_offset(Bdf)); + + //In the Latest version of SBSA 6.0 this part of the test is obsolete hence filling the reg with same data + uint32_t offset_table[TEST_REG_COUNT] = {0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08,0x00,0x08}; + uint32_t attr_table[TEST_REG_COUNT] = {ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD, + ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,ACCESS_TYPE_RD,}; + + switch(Type){ + case EXERCISER_DATA_CFG_SPACE: + for (Index = 0; Index < TEST_REG_COUNT; Index++) { + Data->cfg_space.reg[Index].offset = (offset_table[Index] + pal_exerciser_get_pcie_config_offset (Bdf)); + Data->cfg_space.reg[Index].attribute = attr_table[Index]; + Data->cfg_space.reg[Index].value = pal_mmio_read(EcamBase + offset_table[Index]); + } + return 0; + case EXERCISER_DATA_BAR0_SPACE: + EcamBAR0 = pal_exerciser_get_ecsr_base(Bdf, 0); + Data->bar_space.base_addr = (void *)EcamBAR0; + if (((pal_exerciser_get_ecsr_base(Bdf,0) >> PREFETCHABLE_BIT_SHIFT) & MASK_BIT) == 0x1) + Data->bar_space.type = MMIO_PREFETCHABLE; + else + Data->bar_space.type = MMIO_NON_PREFETCHABLE; + return 0; + case EXERCISER_DATA_MMIO_SPACE: + Index = 0; + Data->bar_space.base_addr = 0; + while (Index < TYPE0_MAX_BARS) + { + EcamBAR = pal_exerciser_get_ecsr_base(Bdf, Index * 4); + + /* Check if the BAR is Memory Mapped IO type */ + if (((EcamBAR >> BAR_MIT_SHIFT) & BAR_MIT_MASK) == MMIO) + { + Data->bar_space.base_addr = (void *)(EcamBAR); + if (((EcamBAR >> PREFETCHABLE_BIT_SHIFT) & MASK_BIT) == 0x1) + Data->bar_space.type = MMIO_PREFETCHABLE; + else + Data->bar_space.type = MMIO_NON_PREFETCHABLE; + + Data->bar_space.base_addr = (void *)EcamBAR; + return 0; + } + + if (((EcamBAR >> BAR_MDT_SHIFT) & BAR_MDT_MASK) == BITS_64) + { + /* Adjust the index to skip next sequential BAR */ + Index++; + } + + /* Adjust index to point to next BAR */ + Index++; + } + + return 1; + default: + return 1; + } +} diff --git a/platform/pal_baremetal/FVP/src/pal_bm_gic.c b/platform/pal_baremetal/RDN2/src/pal_bm_gic.c similarity index 92% rename from platform/pal_baremetal/FVP/src/pal_bm_gic.c rename to platform/pal_baremetal/RDN2/src/pal_bm_gic.c index 55fa9428..26b0f917 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_gic.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_gic.c @@ -15,7 +15,7 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" +#include "pal_common_support.h" /** @@ -38,7 +38,8 @@ pal_gic_install_isr(uint32_t int_id, void (*isr)()) * Enable Interrupt. * Install isr for int_id. */ - + (void) int_id; + (void) isr; return 0; } @@ -53,7 +54,7 @@ pal_gic_install_isr(uint32_t int_id, void (*isr)()) uint32_t pal_gic_end_of_interrupt(uint32_t int_id) { - + (void) int_id; return 0; } @@ -73,7 +74,10 @@ pal_gic_request_irq ( void *Isr ) { - return 0; + (void) IrqNum; + (void) MappedIrqNum; + (void) Isr; + return 0; } /** @@ -89,7 +93,8 @@ pal_gic_free_irq ( uint32_t MappedIrqNum ) { - + (void) IrqNum; + (void) MappedIrqNum; } /** @@ -103,6 +108,7 @@ pal_gic_free_irq ( uint32_t pal_gic_set_intr_trigger(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e trigger_type) { - + (void) int_id; + (void) trigger_type; return 0; } diff --git a/platform/pal_baremetal/FVP/src/pal_bm_iovirt.c b/platform/pal_baremetal/RDN2/src/pal_bm_iovirt.c similarity index 92% rename from platform/pal_baremetal/FVP/src/pal_bm_iovirt.c rename to platform/pal_baremetal/RDN2/src/pal_bm_iovirt.c index 54d1a6ef..9b3c1b7f 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_iovirt.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_iovirt.c @@ -15,7 +15,7 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" +#include "pal_common_support.h" /** @brief Platform defined method to check if CATU is behind an ETR device @@ -27,6 +27,8 @@ uint32_t pal_smmu_is_etr_behind_catu(char *etr_path) { - return NOT_IMPLEMENTED; + (void) etr_path; + + return NOT_IMPLEMENTED; } diff --git a/platform/pal_baremetal/FVP/src/pal_bm_misc.c b/platform/pal_baremetal/RDN2/src/pal_bm_misc.c similarity index 57% rename from platform/pal_baremetal/FVP/src/pal_bm_misc.c rename to platform/pal_baremetal/RDN2/src/pal_bm_misc.c index c4e98eb2..03f2eaba 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_misc.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_misc.c @@ -16,8 +16,25 @@ **/ -#include "include/pal_pcie_enum.h" -#include "include/pal_common_support.h" +#include "pal_pcie_enum.h" +#include "pal_common_support.h" +#include "platform_image_def.h" +#include "platform_override_fvp.h" + +#define __ADDR_ALIGN_MASK(a, mask) (((a) + (mask)) & ~(mask)) +#define ADDR_ALIGN(a, b) __ADDR_ALIGN_MASK(a, (typeof(a))(b) - 1) + +void *mem_alloc(size_t alignment, size_t size); +void mem_free(void *ptr); + +typedef struct { + uint64_t base; + uint64_t size; +} val_host_alloc_region_ts; + +static uint64_t heap_base; +static uint64_t heap_top; +static uint64_t heap_init_done = 0; /** @@ -31,7 +48,8 @@ void pal_print(char *string, uint64_t data) { - + (void) string; + (void) data; } /** @@ -50,7 +68,9 @@ pal_mem_alloc_at_address ( uint64_t Size ) { - + (void) mem_base; + (void) Size; + return (void*) NULL; } /** @@ -64,7 +84,8 @@ pal_mem_free_at_address(uint64_t mem_base, uint64_t Size ) { - + (void) mem_base; + (void) Size; } /** @@ -77,7 +98,9 @@ pal_mem_free_at_address(uint64_t mem_base, void * pal_mem_alloc_cacheable(uint32_t Bdf, uint32_t Size, void **Pa) { - + (void) Bdf; + *Pa = mem_alloc(MEM_ALIGN_4K, Size); + return (void *) *Pa; return 0; } @@ -92,7 +115,10 @@ pal_mem_alloc_cacheable(uint32_t Bdf, uint32_t Size, void **Pa) void pal_mem_free_cacheable(uint32_t Bdf, uint32_t Size, void *Va, void *Pa) { - + (void) Bdf; + (void) Size; + (void) Pa; + (void) Va; } /** @@ -139,6 +165,7 @@ uint64_t pal_time_delay_ms(uint64_t MicroSeconds) { /**Need to implement**/ + (void) MicroSeconds; return 0; } @@ -150,7 +177,7 @@ pal_time_delay_ms(uint64_t MicroSeconds) uint32_t pal_mem_page_size() { - return 0; + return PLATFORM_PAGE_SIZE; } /** @@ -162,7 +189,7 @@ pal_mem_page_size() void * pal_mem_alloc_pages (uint32_t NumPages) { - return 0; + return (void *)mem_alloc(MEM_ALIGN_4K, NumPages * PLATFORM_PAGE_SIZE); } /** @@ -173,7 +200,8 @@ pal_mem_alloc_pages (uint32_t NumPages) void pal_mem_free_pages(void *PageBase, uint32_t NumPages) { - + (void) PageBase; + (void) NumPages; } /** @@ -187,7 +215,7 @@ pal_mem_free_pages(void *PageBase, uint32_t NumPages) void *pal_aligned_alloc( uint32_t alignment, uint32_t size ) { - return (void *)memalign(alignment, size); + return (void *)mem_alloc(alignment, size); } /** @@ -201,6 +229,96 @@ void void pal_mem_free_aligned(void *Buffer) { - free(Buffer); + mem_free(Buffer); + return; } +/* Functions implemented below are used to allocate memory from heap. Baremetal implementation + of memory allocation. +*/ + +static int is_power_of_2(uint32_t n) +{ + return n && !(n & (n - 1)); +} + +/** + * @brief Allocates contiguous memory of requested size(no_of_bytes) and alignment. + * @param alignment - alignment for the address. It must be in power of 2. + * @param Size - Size of the region. It must not be zero. + * @return - Returns allocated memory base address if allocation is successful. + * Otherwise returns NULL. + **/ +void *heap_alloc(size_t alignment, size_t size) +{ + uint64_t addr; + + addr = ADDR_ALIGN(heap_base, alignment); + size += addr - heap_base; + + if ((heap_top - heap_base) < size) + { + return NULL; + } + + heap_base += size; + + return (void *)addr; +} + +/** + * @brief Initialisation of allocation data structure + * @param void + * @return Void + **/ +void mem_alloc_init(void) +{ + heap_base = PLATFORM_HEAP_REGION_BASE; + heap_top = PLATFORM_HEAP_REGION_BASE + PLATFORM_HEAP_REGION_SIZE; + heap_init_done = 1; +} + +/** + * @brief Allocates contiguous memory of requested size(no_of_bytes) and alignment. + * @param alignment - alignment for the address. It must be in power of 2. + * @param Size - Size of the region. It must not be zero. + * @return - Returns allocated memory base address if allocation is successful. + * Otherwise returns NULL. + **/ +void *mem_alloc(size_t alignment, size_t size) +{ + void *addr = NULL; + + if(heap_init_done != 1) + mem_alloc_init(); + + if (size <= 0) + { + return NULL; + } + + if (!is_power_of_2((uint32_t)alignment)) + { + return NULL; + } + + size += alignment - 1; + addr = heap_alloc(alignment, size); + + return addr; +} + +/** + * TODO: Free the memory for given memory address + * Currently acs code is initialisazing from base for every test, + * the regions data structure is internal and below code only setting to zero + * not actually freeing memory. + * If require can revisit in future. + **/ +void mem_free(void *ptr) +{ + if (!ptr) + return; + + return; +} diff --git a/platform/pal_baremetal/FVP/src/pal_bm_pcie.c b/platform/pal_baremetal/RDN2/src/pal_bm_pcie.c similarity index 91% rename from platform/pal_baremetal/FVP/src/pal_bm_pcie.c rename to platform/pal_baremetal/RDN2/src/pal_bm_pcie.c index 885f245f..c681147e 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_pcie.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_pcie.c @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" +#include "pal_common_support.h" +#include "platform_override_struct.h" /** @brief This API checks the PCIe hierarchy fo P2P support @@ -43,6 +43,10 @@ pal_pcie_p2p_support(void) uint32_t pal_pcie_device_driver_present(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn) { + (void) seg; + (void) bus; + (void) dev; + (void) fn; return 1; @@ -62,6 +66,11 @@ pal_pcie_device_driver_present(uint32_t seg, uint32_t bus, uint32_t dev, uint32_ uint32_t pal_get_msi_vectors(uint32_t Seg, uint32_t Bus, uint32_t Dev, uint32_t Fn, PERIPHERAL_VECTOR_LIST **MVector) { + (void) Seg; + (void) Bus; + (void) Dev; + (void) Fn; + (void) MVector; return 0; } @@ -80,6 +89,11 @@ pal_get_msi_vectors(uint32_t Seg, uint32_t Bus, uint32_t Dev, uint32_t Fn, PERIP uint32_t pal_pcie_get_rp_transaction_frwd_support(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn) { + (void) seg; + (void) bus; + (void) dev; + (void) fn; + return 1; } @@ -93,6 +107,8 @@ pal_pcie_get_rp_transaction_frwd_support(uint32_t seg, uint32_t bus, uint32_t de uint32_t pal_pcie_is_onchip_peripheral(uint32_t bdf) { + (void) bdf; + return 0; } @@ -111,5 +127,7 @@ pal_pcie_check_device_valid(uint32_t bdf) need to be ignored for a BDF for any reason */ + (void) bdf; + return 0; } diff --git a/platform/pal_baremetal/FVP/src/pal_bm_pe.c b/platform/pal_baremetal/RDN2/src/pal_bm_pe.c similarity index 60% rename from platform/pal_baremetal/FVP/src/pal_bm_pe.c rename to platform/pal_baremetal/RDN2/src/pal_bm_pe.c index 50fd9dd6..828a0158 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_pe.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_pe.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -14,9 +14,9 @@ * See the License for the specific language governing permissions and * limitations under the License. **/ - -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" +#include "platform_override_fvp.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" /** Conduits for service calls (SMC vs HVC). @@ -25,6 +25,54 @@ #define CONDUIT_HVC 1 #define CONDUIT_NONE -2 +/* Populate phy_mpid_array with mpidr value of CPUs available + * in the system. */ +static const uint64_t phy_mpidr_array[PLATFORM_OVERRIDE_PE_CNT] = { + PLATFORM_OVERRIDE_PE0_MPIDR, +#if (PLATFORM_OVERRIDE_PE_CNT > 1) + PLATFORM_OVERRIDE_PE1_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 2) + PLATFORM_OVERRIDE_PE2_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 3) + PLATFORM_OVERRIDE_PE3_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 4) + PLATFORM_OVERRIDE_PE4_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 5) + PLATFORM_OVERRIDE_PE5_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 6) + PLATFORM_OVERRIDE_PE6_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 7) + PLATFORM_OVERRIDE_PE7_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 8) + PLATFORM_OVERRIDE_PE8_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 9) + PLATFORM_OVERRIDE_PE9_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 10) + PLATFORM_OVERRIDE_PE10_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 11) + PLATFORM_OVERRIDE_PE11_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 12) + PLATFORM_OVERRIDE_PE12_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 13) + PLATFORM_OVERRIDE_PE13_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 14) + PLATFORM_OVERRIDE_PE14_MPIDR, +#elif (PLATFORM_OVERRIDE_PE_CNT > 15) + PLATFORM_OVERRIDE_PE15_MPIDR, +#endif + +}; + +uint32_t pal_get_pe_count(void) +{ + return PLATFORM_OVERRIDE_PE_CNT; +} + +uint64_t *pal_get_phy_mpidr_list_base(void) +{ + return (uint64_t *)&phy_mpidr_array[0]; +} + /** @brief Install Exception Handler through BAREMETAL Interrupt registration @@ -43,6 +91,8 @@ pal_pe_install_esr(uint32_t ExceptionType, void (*esr)(uint64_t, void *)) * 2. Register the handler to receive interrupts */ + (void) ExceptionType; + (void) esr; return 1; } @@ -60,6 +110,8 @@ pal_pe_update_elr(void *context, uint64_t offset) /* TO DO - Baremetal * Place holder to save offset into context saving structure ELR */ + (void)context; + (void) offset; } /** @@ -75,6 +127,7 @@ pal_pe_get_esr(void *context) /*TO DO - Baremetal * Place holder to return ESR from context saving structure */ + (void)context; return 0; } @@ -91,6 +144,7 @@ pal_pe_get_far(void *context) /* TO DO - Baremetal * Place holder to return FAR from context saving structure */ + (void)context; return 0; } diff --git a/platform/pal_baremetal/FVP/src/pal_bm_peripherals.c b/platform/pal_baremetal/RDN2/src/pal_bm_peripherals.c similarity index 91% rename from platform/pal_baremetal/FVP/src/pal_bm_peripherals.c rename to platform/pal_baremetal/RDN2/src/pal_bm_peripherals.c index 04bc9b41..843f1241 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_peripherals.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_peripherals.c @@ -15,19 +15,20 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" +#include "pal_common_support.h" uint64_t pal_memory_ioremap(void *ptr, uint32_t size, uint32_t attr) { - + (void) size; + (void) attr; return (uint64_t)ptr; } void pal_memory_unmap(void *ptr) { - + (void) ptr; return; } diff --git a/platform/pal_baremetal/FVP/src/pal_bm_pmu.c b/platform/pal_baremetal/RDN2/src/pal_bm_pmu.c similarity index 82% rename from platform/pal_baremetal/FVP/src/pal_bm_pmu.c rename to platform/pal_baremetal/RDN2/src/pal_bm_pmu.c index 25373acd..fc42ca50 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_pmu.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_pmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,7 +15,7 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" +#include "pal_common_support.h" /** @@ -29,7 +29,11 @@ uint32_t pal_pmu_check_monitor_count_value(uint64_t interface_acpiid, uint32_t count_value, uint32_t eventid) { - return NOT_IMPLEMENTED; + (void) interface_acpiid; + (void) count_value; + (void) eventid; + + return NOT_IMPLEMENTED; } /** @@ -45,7 +49,12 @@ uint32_t pal_generate_traffic(uint64_t interface_acpiid, uint32_t pmu_node_index, uint32_t mon_index, uint32_t eventid) { - return NOT_IMPLEMENTED; + (void) interface_acpiid; + (void) pmu_node_index; + (void) mon_index; + (void) eventid; + + return NOT_IMPLEMENTED; } /** @@ -59,5 +68,8 @@ uint32_t pal_pmu_get_multi_traffic_support_interface(uint64_t *interface_acpiid, uint32_t *num_traffic_type_support) { - return NOT_IMPLEMENTED; + (void) interface_acpiid; + (void) num_traffic_type_support; + + return NOT_IMPLEMENTED; } diff --git a/platform/pal_baremetal/FVP/src/pal_bm_ras.c b/platform/pal_baremetal/RDN2/src/pal_bm_ras.c similarity index 90% rename from platform/pal_baremetal/FVP/src/pal_bm_ras.c rename to platform/pal_baremetal/RDN2/src/pal_bm_ras.c index efc4581c..7c15d34c 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_ras.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_ras.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,7 +15,7 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" +#include "pal_common_support.h" /** @brief API to check support for Poison @@ -43,6 +43,10 @@ uint32_t pal_ras_setup_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param) { /* Platform Defined way of setting up the Error Environment */ + + (void) in_param; + (void) out_param; + return NOT_IMPLEMENTED; } @@ -57,6 +61,9 @@ pal_ras_setup_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param) uint32_t pal_ras_inject_error(RAS_ERR_IN_t in_param, RAS_ERR_OUT_t *out_param) { + (void) in_param; + (void) out_param; + return NOT_IMPLEMENTED; } diff --git a/platform/pal_baremetal/FVP/src/pal_bm_smmu.c b/platform/pal_baremetal/RDN2/src/pal_bm_smmu.c similarity index 88% rename from platform/pal_baremetal/FVP/src/pal_bm_smmu.c rename to platform/pal_baremetal/RDN2/src/pal_bm_smmu.c index 7b4abdfc..cb65ef41 100644 --- a/platform/pal_baremetal/FVP/src/pal_bm_smmu.c +++ b/platform/pal_baremetal/RDN2/src/pal_bm_smmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" #define SMMU_V3_IDR1 0x4 #define SMMU_V3_IDR1_PASID_SHIFT 6 @@ -31,7 +31,10 @@ uint32_t pal_smmu_create_pasid_entry (uint64_t SmmuBase, uint32_t PasId) { - return 1; + (void) SmmuBase; + (void) PasId; + + return 1; } /** @@ -42,6 +45,8 @@ pal_smmu_create_pasid_entry (uint64_t SmmuBase, uint32_t PasId) uint32_t pal_smmu_disable (uint64_t SmmuBase) { + (void) SmmuBase; + return 0; } @@ -55,6 +60,9 @@ pal_smmu_disable (uint64_t SmmuBase) uint64_t pal_smmu_pa2iova (uint64_t SmmuBase, uint64_t Pa) { + (void) SmmuBase; + (void) Pa; + return 0; } @@ -67,6 +75,8 @@ pal_smmu_pa2iova (uint64_t SmmuBase, uint64_t Pa) **/ uint32_t pal_smmu_check_device_iova(void *port, uint64_t dma_addr) { + (void) port; + (void) dma_addr; return 0; } @@ -78,6 +88,8 @@ uint32_t pal_smmu_check_device_iova(void *port, uint64_t dma_addr) **/ void pal_smmu_device_start_monitor_iova(void *port) { + (void) port; + return; } @@ -88,5 +100,7 @@ void pal_smmu_device_start_monitor_iova(void *port) **/ void pal_smmu_device_stop_monitor_iova(void *port) { + (void) port; + return; } diff --git a/platform/pal_baremetal/FVP/RDN2/src/platform_cfg_fvp.c b/platform/pal_baremetal/RDN2/src/platform_cfg_fvp.c similarity index 99% rename from platform/pal_baremetal/FVP/RDN2/src/platform_cfg_fvp.c rename to platform/pal_baremetal/RDN2/src/platform_cfg_fvp.c index 5ceb3a6e..9093c6c6 100644 --- a/platform/pal_baremetal/FVP/RDN2/src/platform_cfg_fvp.c +++ b/platform/pal_baremetal/RDN2/src/platform_cfg_fvp.c @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" +#include "pal_common_support.h" +#include "platform_override_struct.h" /* To run a specific modules: diff --git a/platform/pal_baremetal/include/pal_common_support.h b/platform/pal_baremetal/common/include/pal_common_support.h similarity index 96% rename from platform/pal_baremetal/include/pal_common_support.h rename to platform/pal_baremetal/common/include/pal_common_support.h index 4ca6b973..7df0083a 100644 --- a/platform/pal_baremetal/include/pal_common_support.h +++ b/platform/pal_baremetal/common/include/pal_common_support.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -23,6 +23,9 @@ #include #include +typedef uintptr_t addr_t; +typedef char char8_t; + extern uint32_t g_print_level; extern uint32_t g_print_mmio; extern uint32_t g_curr_module; @@ -40,6 +43,9 @@ extern uint32_t g_enable_module; #define MEM_ALIGN_32K 0x8000 #define MEM_ALIGN_64K 0x10000 +void pal_mem_free_aligned(void *Buffer); +void *pal_aligned_alloc( uint32_t alignment, uint32_t size ); + #define PCIE_EXTRACT_BDF_SEG(bdf) ((bdf >> 24) & 0xFF) #define PCIE_EXTRACT_BDF_BUS(bdf) ((bdf >> 16) & 0xFF) #define PCIE_EXTRACT_BDF_DEV(bdf) ((bdf >> 8) & 0xFF) @@ -51,8 +57,15 @@ extern uint32_t g_enable_module; #define PCIE_MAX_DEV 32 #define PCIE_MAX_FUNC 8 +#ifdef TARGET_BM_BOOT +void pal_uart_print(int log, const char *fmt, ...); +void *mem_alloc(size_t alignment, size_t size); +#define print(verbose, string, ...) if(verbose >= g_print_level) \ + pal_uart_print(verbose, string, ##__VA_ARGS__) +#else #define print(verbose, string, ...) if(verbose >= g_print_level) \ printf(string, ##__VA_ARGS__) +#endif #define PCIE_CREATE_BDF(Seg, Bus, Dev, Func) ((Seg << 24) | (Bus << 16) | (Dev << 8) | Func) @@ -527,6 +540,7 @@ typedef struct { }IOVIRT_INFO_TABLE; #define IOVIRT_NEXT_BLOCK(b) (IOVIRT_BLOCK *)((uint8_t*)(&b->data_map[0]) + b->num_data_map * sizeof(NODE_DATA_MAP)) +#define ALIGN_MEMORY(b, bound) (IOVIRT_BLOCK *) (((uint64_t)b + bound - 1) & (~(bound - 1))) #define IOVIRT_CCA_MASK ~((uint32_t)0) /* Memory INFO table */ @@ -896,4 +910,12 @@ typedef struct { void pal_hmat_create_info_table(HMAT_INFO_TABLE *HmatTable); +/* LibC functions declaration */ + +int pal_mem_compare(void *Src, void *Dest, uint32_t Len); +void *pal_memcpy(void *DestinationBuffer, const void *SourceBuffer, uint32_t Length); +void *pal_strncpy(void *DestinationStr, const void *SourceStr, uint32_t Length); +uint32_t pal_strncmp(const char8_t *str1, const char8_t *str2, uint32_t len); +void pal_mem_set(void *buf, uint32_t size, uint8_t value); + #endif diff --git a/platform/pal_baremetal/include/pal_pcie_enum.h b/platform/pal_baremetal/common/include/pal_pcie_enum.h similarity index 97% rename from platform/pal_baremetal/include/pal_pcie_enum.h rename to platform/pal_baremetal/common/include/pal_pcie_enum.h index 899c9671..85437a89 100644 --- a/platform/pal_baremetal/include/pal_pcie_enum.h +++ b/platform/pal_baremetal/common/include/pal_pcie_enum.h @@ -41,7 +41,8 @@ /*BAR offset */ #define BAR0_OFFSET 0x10 -#define BAR_MAX_OFFSET 0x24 +#define TYPE1_BAR_MAX_OFF 0x14 +#define TYPE0_BAR_MAX_OFF 0x24 #define BAR_64_BIT 1 #define BAR_32_BIT 0 diff --git a/platform/pal_baremetal/common/include/pal_pl011_uart.h b/platform/pal_baremetal/common/include/pal_pl011_uart.h new file mode 100644 index 00000000..4794a7ed --- /dev/null +++ b/platform/pal_baremetal/common/include/pal_pl011_uart.h @@ -0,0 +1,73 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include +#include "platform_override_fvp.h" + +#ifndef _PAL_UART_PL011_H_ +#define _PAL_UART_PL011_H_ + +/* typedef's */ +typedef struct { + volatile uint32_t uartdr; /* Offset: 0x000 (R/W) Data Register */ + union { + volatile uint32_t uartrsr; /* Offset: 0x004 (R/ ) Receive status register */ + volatile uint32_t uartecr; /* Offset: 0x004 ( /W) Error clear register */ + }; + volatile uint32_t reserved_0[4]; /* Offset: 0x008-0x014 Reserved */ + volatile uint32_t uartfr; /* Offset: 0x018 (R/ ) Flag register */ + volatile uint32_t reserved_1; /* Offset: 0x01C Reserved */ + volatile uint32_t uartilpr; /* Offset: 0x020 (R/W) IrDA low-power counter register */ + volatile uint32_t uartibrd; /* Offset: 0x024 (R/W) Integer baud rate register */ + volatile uint32_t uartfbrd; /* Offset: 0x028 (R/W) Fractional baud rate register */ + volatile uint32_t uartlcr_h; /* Offset: 0x02C (R/W) Line control register */ + volatile uint32_t uartcr; /* Offset: 0x030 (R/W) Control register */ + volatile uint32_t uartifls; /* Offset: 0x034 (R/W) Interrupt FIFO level select reg */ + volatile uint32_t uartimsc; /* Offset: 0x038 (R/W) Interrupt mask set/clear register */ + volatile uint32_t uartris; /* Offset: 0x03C (R/ ) Raw interrupt status register */ + volatile uint32_t uartmis; /* Offset: 0x040 (R/ ) Masked interrupt status register */ + volatile uint32_t uarticr; /* Offset: 0x044 ( /W) Interrupt clear register */ + volatile uint32_t uartdmacr; /* Offset: 0x048 (R/W) DMA control register */ +} pal_uart_t; + +/* UART Enable */ +#define UART_PL011_UARTCR_UARTEN_OFF 0x0u +#define UART_PL011_UARTCR_EN_MASK (0x1u << UART_PL011_UARTCR_UARTEN_OFF) +/* Transmit enable */ +#define UART_PL011_UARTCR_TXE_OFF 0x8u +#define UART_PL011_UARTCR_TX_EN_MASK (0x1u << UART_PL011_UARTCR_TXE_OFF) +#define UART_PL011_UARTFR_TX_FIFO_FULL_OFF 0x5u +#define UART_PL011_UARTFR_TX_FIFO_FULL (0x1u << UART_PL011_UARTFR_TX_FIFO_FULL_OFF) + +#define UART_PL011_INTR_TX_OFF 0x5u +#define UART_PL011_TX_INTR_MASK (0x1u << UART_PL011_INTR_TX_OFF) +#define UART_PL011_UARTLCR_H_FEN_OFF 0x4u +#define UART_PL011_UARTLCR_H_FEN_MASK (0x1u << UART_PL011_UARTLCR_H_FEN_OFF) +#define UART_PL011_UARTLCR_H_WLEN_8 5 +#define UART_PL011_UARTLCR_H_WLEN_8_MASK (3 << UART_PL011_UARTLCR_H_WLEN_8) +#define UART_PL011_CLK_IN_HZ UART_CLK_RATE_HZ +#define UART_PL011_BAUDRATE UART_BAUD_RATE +#define UART_PL011_LINE_CONTROL (UART_PL011_UARTLCR_H_FEN_MASK | UART_PL011_UARTLCR_H_WLEN_8_MASK) + +#define PLATFORM_UART_BASE BASE_ADDRESS_ADDRESS + +/* function prototypes */ +extern void pal_driver_uart_pl011_putc(int c); + +#define pal_uart_putc(x) pal_driver_uart_pl011_putc(x) + +#endif /* _PAL_UART_PL011_H_ */ diff --git a/platform/pal_baremetal/include/pal_pmu.h b/platform/pal_baremetal/common/include/pal_pmu.h similarity index 100% rename from platform/pal_baremetal/include/pal_pmu.h rename to platform/pal_baremetal/common/include/pal_pmu.h diff --git a/platform/pal_baremetal/juno/src/AArch64/ArmSmc.S b/platform/pal_baremetal/common/src/AArch64/ArmSmc.S similarity index 90% rename from platform/pal_baremetal/juno/src/AArch64/ArmSmc.S rename to platform/pal_baremetal/common/src/AArch64/ArmSmc.S index 135aa25e..ada3d3d0 100644 --- a/platform/pal_baremetal/juno/src/AArch64/ArmSmc.S +++ b/platform/pal_baremetal/common/src/AArch64/ArmSmc.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,6 +16,8 @@ # #**/ +#include "gcc_types.h" + .text .align 3 diff --git a/platform/pal_baremetal/juno/src/AArch64/AvsTestInfra.S b/platform/pal_baremetal/common/src/AArch64/AvsTestInfra.S similarity index 90% rename from platform/pal_baremetal/juno/src/AArch64/AvsTestInfra.S rename to platform/pal_baremetal/common/src/AArch64/AvsTestInfra.S index 86ddf01f..244dcbb5 100644 --- a/platform/pal_baremetal/juno/src/AArch64/AvsTestInfra.S +++ b/platform/pal_baremetal/common/src/AArch64/AvsTestInfra.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,6 +16,8 @@ # #**/ +#include "gcc_types.h" + .text .align 3 diff --git a/platform/pal_baremetal/juno/src/AArch64/ModuleEntryPoint.S b/platform/pal_baremetal/common/src/AArch64/ModuleEntryPoint.S similarity index 91% rename from platform/pal_baremetal/juno/src/AArch64/ModuleEntryPoint.S rename to platform/pal_baremetal/common/src/AArch64/ModuleEntryPoint.S index c2de589f..8c3aaefc 100644 --- a/platform/pal_baremetal/juno/src/AArch64/ModuleEntryPoint.S +++ b/platform/pal_baremetal/common/src/AArch64/ModuleEntryPoint.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,6 +16,8 @@ # #**/ +#include "gcc_types.h" + .text .align 3 diff --git a/platform/pal_baremetal/common/src/AArch64/gcc_types.h b/platform/pal_baremetal/common/src/AArch64/gcc_types.h new file mode 100644 index 00000000..7eed68da --- /dev/null +++ b/platform/pal_baremetal/common/src/AArch64/gcc_types.h @@ -0,0 +1,37 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +// +// Private worker functions for ASM_PFX() +// +#define _CONCATENATE(a, b) __CONCATENATE(a, b) +#define __CONCATENATE(a, b) a ## b + +#define __USER_LABEL_PREFIX__ +// +// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix +// on symbols in assembly language. +// +#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) + +#define GCC_ASM_EXPORT(func__) \ + .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ + .type ASM_PFX(func__), %function + +#define GCC_ASM_IMPORT(func__) \ + .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) + diff --git a/platform/pal_baremetal/src/pal_dma.c b/platform/pal_baremetal/common/src/pal_dma.c similarity index 92% rename from platform/pal_baremetal/src/pal_dma.c rename to platform/pal_baremetal/common/src/pal_dma.c index c114108a..8b9ac8d0 100644 --- a/platform/pal_baremetal/src/pal_dma.c +++ b/platform/pal_baremetal/common/src/pal_dma.c @@ -16,9 +16,9 @@ **/ -#include "include/platform_override_struct.h" -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" +#include "platform_override_struct.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" extern DMA_INFO_TABLE platform_dma_cfg; diff --git a/platform/pal_baremetal/src/pal_exerciser.c b/platform/pal_baremetal/common/src/pal_exerciser.c similarity index 97% rename from platform/pal_baremetal/src/pal_exerciser.c rename to platform/pal_baremetal/common/src/pal_exerciser.c index de69e59c..96c7d19c 100644 --- a/platform/pal_baremetal/src/pal_exerciser.c +++ b/platform/pal_baremetal/common/src/pal_exerciser.c @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" extern PCIE_INFO_TABLE *g_pcie_info_table; diff --git a/platform/pal_baremetal/src/pal_gic.c b/platform/pal_baremetal/common/src/pal_gic.c similarity index 97% rename from platform/pal_baremetal/src/pal_gic.c rename to platform/pal_baremetal/common/src/pal_gic.c index fcf67edf..282d979b 100644 --- a/platform/pal_baremetal/src/pal_gic.c +++ b/platform/pal_baremetal/common/src/pal_gic.c @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" +#include "pal_common_support.h" +#include "platform_override_struct.h" extern PLATFORM_OVERRIDE_GIC_INFO_TABLE platform_gic_cfg; diff --git a/platform/pal_baremetal/src/pal_hmat.c b/platform/pal_baremetal/common/src/pal_hmat.c similarity index 95% rename from platform/pal_baremetal/src/pal_hmat.c rename to platform/pal_baremetal/common/src/pal_hmat.c index db47c000..3466f092 100644 --- a/platform/pal_baremetal/src/pal_hmat.c +++ b/platform/pal_baremetal/common/src/pal_hmat.c @@ -15,9 +15,9 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" -#include "include/platform_override_struct.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" +#include "platform_override_struct.h" extern PLATFORM_OVERRIDE_HMAT_INFO_TABLE platform_hmat_cfg; extern PLATFORM_OVERRIDE_HMAT_MEM_TABLE platform_hmat_mem_cfg; @@ -57,7 +57,8 @@ void pal_hmat_dump_info_table(HMAT_INFO_TABLE *HmatTable) **/ void pal_hmat_create_info_table(HMAT_INFO_TABLE *HmatTable) { - uint32_t prox_domain = 0, Index = 0; + int32_t prox_domain = 0; + uint32_t Index = 0; uint32_t data_type; uint64_t entry_base_unit; HMAT_BW_ENTRY *curr_info_entry; diff --git a/platform/pal_baremetal/src/pal_iovirt.c b/platform/pal_baremetal/common/src/pal_iovirt.c similarity index 93% rename from platform/pal_baremetal/src/pal_iovirt.c rename to platform/pal_baremetal/common/src/pal_iovirt.c index 6e0f6292..4e4f7a29 100644 --- a/platform/pal_baremetal/src/pal_iovirt.c +++ b/platform/pal_baremetal/common/src/pal_iovirt.c @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" +#include "pal_common_support.h" +#include "platform_override_struct.h" extern PLATFORM_OVERRIDE_IOVIRT_INFO_TABLE platform_iovirt_cfg; extern PLATFORM_OVERRIDE_NODE_DATA platform_node_type; @@ -25,6 +25,13 @@ extern PLATFORM_OVERRIDE_PMCG_NODE_DATA platform_pmcg_node_data; extern PLATFORM_OVERRIDE_NAMED_NODE_DATA platform_named_node_data; extern PLATFORM_OVERRIDE_CS_COMP_NODE_DATA platform_cs_comp_node_data; +#ifdef TARGET_BM_BOOT + // Align the memory access by 8 bytes in case of baremetal boot. + static uint64_t bound = 0x08; +#else + static uint64_t bound = 0x01; +#endif + uint64_t pal_iovirt_get_rc_smmu_base ( IOVIRT_INFO_TABLE *Iovirt, @@ -44,6 +51,7 @@ pal_iovirt_get_rc_smmu_base ( mapping_found = 0; for (i = 0; i < Iovirt->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) { + block = ALIGN_MEMORY(block, bound); if (block->type == IOVIRT_NODE_PCI_ROOT_COMPLEX && block->data.rc.segment == RcSegmentNum) { @@ -190,18 +198,23 @@ pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *IoVirtTable) block = &(IoVirtTable->blocks[0]); for (i = 0; i < platform_iovirt_cfg.node_count; i++, block=IOVIRT_NEXT_BLOCK(block)) { + block = ALIGN_MEMORY(block, bound); block->type = platform_iovirt_cfg.type[i]; block->flags = 0; switch(platform_iovirt_cfg.type[i]){ case IOVIRT_NODE_ITS_GROUP: +#ifdef TARGET_BM_BOOT + block->data.its_count = IOVIRT_ITS_COUNT; +#else block->data.its_count = platform_node_type.its_count; +#endif data_map = &block->data_map[0]; - memcpy(&((*data_map).id[0]), &identifier[i][0], sizeof(uint32_t) * block->data.its_count); + pal_memcpy(&((*data_map).id[0]), &identifier[i][0], sizeof(uint32_t) * block->data.its_count); block->num_data_map = (block->data.its_count +3)/4; IoVirtTable->num_its_groups++; break; case IOVIRT_NODE_NAMED_COMPONENT: - strncpy(block->data.named_comp.name, platform_named_node_data.named[n].name, + pal_strncpy(block->data.named_comp.name, platform_named_node_data.named[n].name, MAX_NAMED_COMP_LENGTH); block->data.named_comp.cca = (platform_named_node_data.named[n].memory_properties) & IOVIRT_CCA_MASK; @@ -288,7 +301,10 @@ pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *IoVirtTable) block = &(IoVirtTable->blocks[0]); print(AVS_PRINT_DEBUG, " Number of IOVIRT blocks = %d\n", IoVirtTable->num_blocks); for(i = 0; i < IoVirtTable->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) - dump_block(block); + { + block = ALIGN_MEMORY(block, bound); + dump_block(block); + } } @@ -332,16 +348,17 @@ pal_iovirt_unique_rid_strid_map(uint64_t rc_block) uint32_t pal_get_device_path(const char *hid, char hid_path[][MAX_NAMED_COMP_LENGTH]) { - uint32_t i, cmp; + uint32_t cmp; + int32_t i; uint32_t status = 1; /* Iterate through components and add device name of the component to the array if hid of the component is matched */ for (i = 0; i < CS_COMPONENT_COUNT; i++) { - cmp = strncmp(hid, platform_cs_comp_node_data.component[i].identifier, MAX_CS_COMP_LENGTH); + cmp = pal_strncmp(hid, platform_cs_comp_node_data.component[i].identifier, MAX_CS_COMP_LENGTH); if (!cmp) { status = 0; - strncpy(hid_path[i], + pal_strncpy(hid_path[i], platform_cs_comp_node_data.component[i].dev_name, MAX_CS_COMP_LENGTH); } } @@ -350,4 +367,4 @@ pal_get_device_path(const char *hid, char hid_path[][MAX_NAMED_COMP_LENGTH]) return 1; // return 1 if there's no entry in hid_path return 0; -} \ No newline at end of file +} diff --git a/platform/pal_baremetal/src/pal_misc.c b/platform/pal_baremetal/common/src/pal_misc.c similarity index 52% rename from platform/pal_baremetal/src/pal_misc.c rename to platform/pal_baremetal/common/src/pal_misc.c index 62a9547a..bf0e343a 100644 --- a/platform/pal_baremetal/src/pal_misc.c +++ b/platform/pal_baremetal/common/src/pal_misc.c @@ -15,13 +15,26 @@ * limitations under the License. **/ +#include +#include +#include "pal_pcie_enum.h" +#include "pal_common_support.h" +#include "pal_pl011_uart.h" -#include "include/pal_pcie_enum.h" -#include "include/pal_common_support.h" - +extern uint32_t g_print_level; extern void* g_sbsa_log_file_handle; - uint8_t *gSharedMemory; + +#define get_num_va_args(_args, _lcount) \ + (((_lcount) > 1) ? va_arg(_args, long long int) : \ + (((_lcount) == 1) ? va_arg(_args, long int) : \ + va_arg(_args, int))) + +#define get_unum_va_args(_args, _lcount) \ + (((_lcount) > 1) ? va_arg(_args, unsigned long long int) : \ + (((_lcount) == 1) ? va_arg(_args, unsigned long int) : \ + va_arg(_args, unsigned int))) + /** @brief Provides a single point of abstraction to read from all Memory Mapped IO address @@ -95,9 +108,10 @@ pal_mmio_read(uint64_t addr) { uint32_t data; + uint64_t mask = 0x3; if (addr & 0x3) { - addr = addr & ~(0x3); //make sure addr is aligned to 4 bytes + addr = addr & ~mask; //make sure addr is aligned to 4 bytes } data = (*(volatile uint32_t *)addr); @@ -219,7 +233,7 @@ pal_print_raw(uint64_t addr, char *string, uint64_t data) } } if(i>0) { - while(i>=0) + while(i!=0) *(volatile uint8_t *)addr = buffer[--i]; } else *(volatile uint8_t *)addr = 48; @@ -229,22 +243,6 @@ pal_print_raw(uint64_t addr, char *string, uint64_t data) } } -/** - @brief Compares two strings - - @param FirstString The pointer to a Null-terminated ASCII string. - @param SecondString The pointer to a Null-terminated ASCII string. - @param Length The maximum number of ASCII characters for compare. - - @return Zero if strings are identical, else non-zero value -**/ -uint32_t -pal_strncmp(char *FirstString, char *SecondString, uint32_t Length) -{ - - return strncmp(FirstString, SecondString, Length); -} - /** @brief Free the memory allocated by UEFI Framework APIs @param Buffer the base address of the memory range to be freed @@ -254,36 +252,11 @@ pal_strncmp(char *FirstString, char *SecondString, uint32_t Length) void pal_mem_free(void *Buffer) { +#ifndef TARGET_BM_BOOT free(Buffer); -} - -/** - @brief Compare the contents of the src and dest buffers - @param Src - source buffer to be compared - @param Dest - destination buffer to be compared - @param Len - Length of the comparison to be performed - - @return Zero if the buffer contecnts are same, else Nonzero -**/ -uint32_t -pal_mem_compare(void *Src, void *Dest, uint32_t Len) -{ - - return memcmp(Src, Dest, Len); -} - -/** - @brief a buffer with a known specified input value - @param Buf - Pointer to the buffer to fill - @param Size - Number of bytes in buffer to fill - @param Value - Value to fill buffer with - - @return None -**/ -void -pal_mem_set(void *Buf, uint32_t Size, uint8_t Value) -{ - memset(Buf, Value, Size); +#else + pal_mem_free_aligned(Buffer); +#endif } uint64_t @@ -302,7 +275,11 @@ pal_mem_get_shared_addr() void pal_mem_free_shared() { +#ifndef TARGET_BM_BOOT free ((void *)gSharedMemory); +#else + pal_mem_free_aligned((void *)gSharedMemory); +#endif } /** @@ -316,8 +293,13 @@ pal_mem_free_shared() void * pal_mem_alloc(uint32_t Size) { - +#ifndef TARGET_BM_BOOT return malloc(Size); +#else + uint32_t alignment = 0x08; + return (void *)mem_alloc(alignment, Size); +#endif + } /** @@ -331,10 +313,22 @@ pal_mem_alloc(uint32_t Size) void * pal_mem_calloc(uint32_t num, uint32_t Size) { - +#ifndef TARGET_BM_BOOT return calloc(num, Size); -} +#else + void* ptr; + uint32_t alignment = 0x08; + ptr = mem_alloc(alignment, num * Size); + + if (ptr != NULL) + { + pal_mem_set(ptr, num * Size, 0); + } + return ptr; +#endif + +} /** @brief Allocate memory which is to be used to share data across PEs @@ -352,6 +346,21 @@ pal_mem_allocate_shared(uint32_t num_pe, uint32_t sizeofentry) pal_pe_data_cache_ops_by_va((uint64_t)&gSharedMemory, CLEAN_AND_INVALIDATE); } +/** + @brief Checks if System information is passed using Baremetal (BM) + This api is also used to check if GIC/Interrupt Init ACS Code + is used or not. In case of BM, ACS Code is used for INIT + + @param None + + @return True/False +*/ +uint32_t +pal_target_is_bm() +{ + return 1; +} + /** Copies a source buffer to a destination buffer, and returns the destination buffer. @@ -363,24 +372,289 @@ pal_mem_allocate_shared(uint32_t num_pe, uint32_t sizeofentry) **/ void * -pal_memcpy(void *DestinationBuffer, void *SourceBuffer, uint32_t Length) +pal_memcpy(void *DestinationBuffer, const void *SourceBuffer, uint32_t Length) { - return memcpy(DestinationBuffer, SourceBuffer, Length); + uint32_t i; + const char *s = (char *)SourceBuffer; + char *d = (char *) DestinationBuffer; + + for(i = 0; i < Length; i++) + { + d[i] = s[i]; + } + + return d; } -/** - @brief Checks if System information is passed using Baremetal (BM) - This api is also used to check if GIC/Interrupt Init ACS Code - is used or not. In case of BM, ACS Code is used for INIT +uint32_t pal_strncmp(const char8_t *str1, const char8_t *str2, uint32_t len) +{ + while ( len && *str1 && ( *str1 == *str2 ) ) + { + ++str1; + ++str2; + --len; + } + if ( len == 0 ) + { + return 0; + } + else + { + return ( *(unsigned char *)str1 - *(unsigned char *)str2 ); + } +} - @param None +void *pal_strncpy(void *DestinationStr, const void *SourceStr, uint32_t Length) +{ + const char *s = SourceStr; + char *d = DestinationStr; - @return True/False -*/ -uint32_t -pal_target_is_bm() + if (d == NULL) { + return NULL; + } + + char* ptr = d; + + while (*s && Length--) + { + *d = *s; + d++; + s++; + } + *d = '\0'; + + return ptr; +} + +int +pal_mem_compare(void *Src, void *Dest, uint32_t Len) { - return 1; + if (Len != 0) { + register const unsigned char *p1 = Dest, *p2 = Src; + + do { + if (*p1++ != *p2++) + return (*--p1 - *--p2); + } while (--Len != 0); + } + return (0); +} + +void +pal_mem_set(void *buf, uint32_t size, uint8_t value) +{ + unsigned char *ptr = buf; + + while (size--) + { + *ptr++ = (unsigned char)value; + } + + return (void) buf; } +/* The functions implemented below are to enable console prints via UART driver */ + +static int string_print(const char *str) +{ + int count = 0; + + for ( ; *str != '\0'; str++) { + (void)pal_uart_putc(*str); + count++; + } + + return count; +} + +static int unsigned_num_print(unsigned long long int unum, unsigned int radix, + char padc, int padn) +{ + /* Just need enough space to store 64 bit decimal integer */ + char num_buf[20]; + int i = 0, count = 0; + unsigned int rem; + + /* num_buf is only large enough for radix >= 10 */ + if (radix < 10) { + return 0; + } + + do { + rem = unum % radix; + if (rem < 0xa) + num_buf[i] = '0' + rem; + else + num_buf[i] = 'a' + (rem - 0xa); + i++; + unum /= radix; + } while (unum > 0U); + + if (padn > 0) { + while (i < padn) { + (void)pal_uart_putc(padc); + count++; + padn--; + } + } + + while (--i >= 0) { + (void)pal_uart_putc(num_buf[i]); + count++; + } + + return count; +} + +int vprintf(const char *fmt, va_list args) +{ + int l_count; + long long int num; + unsigned long long int unum; + char *str; + char padc = '\0'; /* Padding character */ + int padn; /* Number of characters to pad */ + int count = 0; /* Number of printed characters */ + + while (*fmt != '\0') { + l_count = 0; + padn = 0; + + if (*fmt == '%') { + fmt++; + /* Check the format specifier */ +loop: + switch (*fmt) { + case '%': + (void)pal_uart_putc('%'); + break; + case 'i': /* Fall through to next one */ + case 'd': + num = get_num_va_args(args, l_count); + if (num < 0) { + (void)pal_uart_putc('-'); + unum = (unsigned long long int)-num; + padn--; + } else + unum = (unsigned long long int)num; + + count += unsigned_num_print(unum, 10, + padc, padn); + break; + case 's': + str = va_arg(args, char *); + count += string_print(str); + break; + case 'p': + unum = (uintptr_t)va_arg(args, void *); + if (unum > 0U) { + count += string_print("0x"); + padn -= 2; + } + + count += unsigned_num_print(unum, 16, + padc, padn); + break; + case 'x': + unum = get_unum_va_args(args, l_count); + count += unsigned_num_print(unum, 16, + padc, padn); + break; + case 'z': + if (sizeof(size_t) == 8U) + l_count = 2; + + fmt++; + goto loop; + case 'l': + l_count++; + fmt++; + goto loop; + case 'u': + unum = get_unum_va_args(args, l_count); + count += unsigned_num_print(unum, 10, + padc, padn); + break; + case '1': + case '2': + case '3': + case '4': + case '5': + case '6': + case '7': + case '8': + case '9': + case '0': + padc = '0'; + padn = 0; + fmt++; + + for (;;) { + char ch = *fmt; + if ((ch < '0') || (ch > '9')) { + goto loop; + } + padn = (padn * 10) + (ch - '0'); + fmt++; + } + + default: + /* Exit on any other format specifier */ + return -1; + } + + fmt++; + continue; + } + else + { + (void)pal_uart_putc(*fmt); + if (*fmt == '\n') + { + (void)pal_uart_putc('\r'); + } + } + + fmt++; + count++; + } + + return count; +} + +static const char *prefix_str[] = { + "", "", "", "", ""}; + +const char *log_get_prefix(int log_level) +{ + int level; + + if (log_level > AVS_PRINT_ERR) { + level = AVS_PRINT_ERR; + } else if (log_level < AVS_PRINT_INFO) { + level = AVS_PRINT_TEST; + } else { + level = log_level; + } + + return prefix_str[level - 1]; +} + +void pal_uart_print(int log, const char *fmt, ...) +{ + va_list args; + const char *prefix_str; + + prefix_str = log_get_prefix(log); + + while (*prefix_str != '\0') { + pal_uart_putc(*prefix_str); + prefix_str++; + } + + va_start(args, fmt); + (void)vprintf(fmt, args); + va_end(args); + (void) log; +} \ No newline at end of file diff --git a/platform/pal_baremetal/src/pal_mpam.c b/platform/pal_baremetal/common/src/pal_mpam.c similarity index 96% rename from platform/pal_baremetal/src/pal_mpam.c rename to platform/pal_baremetal/common/src/pal_mpam.c index 64526f10..e6892aba 100644 --- a/platform/pal_baremetal/src/pal_mpam.c +++ b/platform/pal_baremetal/common/src/pal_mpam.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,9 +15,9 @@ * limitations under the License. **/ -#include "include/platform_override_struct.h" -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" +#include "platform_override_struct.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" extern SRAT_INFO_TABLE platform_srat_cfg; extern PLATFORM_OVERRIDE_SRAT_NODE_INFO_TABLE platform_srat_node_type; @@ -104,7 +104,7 @@ pal_srat_dump_table(SRAT_INFO_TABLE *SratTable) /** @brief This API fills in the MPAM_INFO_TABLE with the platform information - This employs baremetal platform specific data. + This employs baremetal platform specific data. @param MpamTable - Address where the MPAM information needs to be filled. diff --git a/platform/pal_baremetal/src/pal_pcie.c b/platform/pal_baremetal/common/src/pal_pcie.c similarity index 99% rename from platform/pal_baremetal/src/pal_pcie.c rename to platform/pal_baremetal/common/src/pal_pcie.c index fe866bc4..40b6a7f5 100644 --- a/platform/pal_baremetal/src/pal_pcie.c +++ b/platform/pal_baremetal/common/src/pal_pcie.c @@ -15,17 +15,15 @@ * limitations under the License. **/ -#include "include/pal_pcie_enum.h" -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" +#include "pal_pcie_enum.h" +#include "pal_common_support.h" +#include "platform_override_struct.h" extern pcie_device_bdf_table *g_pcie_bdf_table; extern PCIE_INFO_TABLE platform_pcie_cfg; extern PCIE_READ_TABLE platform_pcie_device_hierarchy; extern PERIPHERAL_INFO_TABLE *g_peripheral_info_table; -void *pal_memcpy(void *dest_buffer, void *src_buffer, uint32_t len); - uint64_t pal_pcie_get_mcfg_ecam() { @@ -83,6 +81,9 @@ pal_pcie_ecam_base(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t func) uint8_t ecam_index; uint64_t ecam_base; + (void) dev; + (void) func; + ecam_index = 0; ecam_base = 0; @@ -682,6 +683,8 @@ pal_pcie_mem_get_offset(uint32_t type) uint32_t pal_pcie_bar_mem_read(uint32_t Bdf, uint64_t address, uint32_t *data) { + (void) Bdf; + *data = pal_mmio_read(address); return 0; } @@ -699,6 +702,8 @@ pal_pcie_bar_mem_read(uint32_t Bdf, uint64_t address, uint32_t *data) uint32_t pal_pcie_bar_mem_write(uint32_t Bdf, uint64_t address, uint32_t data) { + (void) Bdf; + pal_mmio_write(address, data); return 0; } diff --git a/platform/pal_baremetal/src/pal_pcie_enumeration.c b/platform/pal_baremetal/common/src/pal_pcie_enumeration.c similarity index 86% rename from platform/pal_baremetal/src/pal_pcie_enumeration.c rename to platform/pal_baremetal/common/src/pal_pcie_enumeration.c index 19532b0b..fc2e7db2 100644 --- a/platform/pal_baremetal/src/pal_pcie_enumeration.c +++ b/platform/pal_baremetal/common/src/pal_pcie_enumeration.c @@ -14,21 +14,23 @@ * limitations under the License. **/ -#include "include/pal_pcie_enum.h" -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" +#include "pal_pcie_enum.h" +#include "pal_common_support.h" +#include "platform_override_struct.h" extern PCIE_INFO_TABLE *g_pcie_info_table; -uint32_t index = 0, enumerate = 1; +uint32_t pcie_index = 0, enumerate = 1; /*64-bit address initialisation*/ -uint64_t g_bar64_p_start = PLATFORM_OVERRIDE_PCIE_BAR64_VAL; +uint64_t g_bar64_p_start = PLATFORM_OVERRIDE_PCIE_BAR64_VAL; +uint64_t g_rp_bar64_value = PLATFORM_OVERRIDE_RP_BAR64_VAL; uint64_t g_bar64_p_max; uint32_t g_64_bus, g_bar64_size; /*32-bit address initialisation*/ uint32_t g_bar32_np_start = PLATFORM_OVERRIDE_PCIE_BAR32NP_VAL; uint32_t g_bar32_p_start = PLATFORM_OVERRIDE_PCIE_BAR32P_VAL; +uint32_t g_rp_bar32_value = PLATOFRM_OVERRIDE_RP_BAR32_VAL; uint32_t g_bar32_np_max; uint32_t g_bar32_p_max; uint32_t g_np_bar_size = 0, g_p_bar_size = 0; @@ -54,14 +56,14 @@ uint32_t pal_pci_cfg_read(uint32_t bus, uint32_t dev, uint32_t func, uint32_t of if ((bus >= g_pcie_info_table->block[i].start_bus_num) && (bus <= g_pcie_info_table->block[i].end_bus_num)) { - index = i; + pcie_index = i; break; } i++; } } - uint64_t ecam_base = g_pcie_info_table->block[index].ecam_base; + uint64_t ecam_base = g_pcie_info_table->block[pcie_index].ecam_base; cfg_addr = (bus * PCIE_MAX_DEV * PCIE_MAX_FUNC * PCIE_CFG_SIZE) + (dev * PCIE_MAX_FUNC * PCIE_CFG_SIZE) + (func * PCIE_CFG_SIZE); *value = pal_mmio_read(ecam_base + cfg_addr + offset); @@ -80,7 +82,7 @@ uint32_t pal_pci_cfg_read(uint32_t bus, uint32_t dev, uint32_t func, uint32_t of void pal_pci_cfg_write(uint32_t bus, uint32_t dev, uint32_t func, uint32_t offset, uint32_t data) { - uint64_t ecam_base = g_pcie_info_table->block[index].ecam_base; + uint64_t ecam_base = g_pcie_info_table->block[pcie_index].ecam_base; uint32_t cfg_addr; @@ -119,11 +121,6 @@ get_resource_base_32(uint32_t bus, uint32_t dev, uint32_t func, uint32_t bar32_p pal_pci_cfg_write(bus, dev, func, NON_PRE_FET_OFFSET, mem_bar_np); } - if (bar32_np_base == g_bar32_np_start) - { - pal_pci_cfg_write(bus, dev, func, NON_PRE_FET_OFFSET, 0); - } - /*Update the 32 bit P-BAR start address for the next iteration*/ if (bar32_p_base != g_bar32_p_start) { @@ -135,10 +132,6 @@ get_resource_base_32(uint32_t bus, uint32_t dev, uint32_t func, uint32_t bar32_p mem_bar_p = ((bar32_p_limit & MEM_BASE32_LIM_MASK) | mem_bar_p); pal_pci_cfg_write(bus, dev, func, PRE_FET_OFFSET, mem_bar_p); } - if (bar32_p_base == g_bar32_p_start) - { - pal_pci_cfg_write(bus, dev, func, PRE_FET_OFFSET, 0); - } } @@ -168,7 +161,7 @@ get_resource_base_64(uint32_t bus, uint32_t dev, uint32_t func, uint64_t bar64_p uint32_t mem_bar_p = ((bar64_p_lower32_limit << 16) | bar64_p_lower32_base); /*Configure Memory base and Memory limit register*/ - if (bar64_p_base != g_bar64_p_max) + if ((bar64_p_base != g_bar64_p_max) && (g_bar64_p_start <= g_bar64_p_max)) { if ((g_bar64_p_start << 12) != 0) g_bar64_p_start = (g_bar64_p_start & MEM_BASE64_LIM_MASK) + BAR_INCREMENT; @@ -181,6 +174,72 @@ get_resource_base_64(uint32_t bus, uint32_t dev, uint32_t func, uint64_t bar64_p } } +void +pal_pcie_rp_program_bar(uint32_t bus, uint32_t dev, uint32_t func) +{ + uint64_t bar_size, bar_upper_bits; + uint32_t offset = BAR0_OFFSET; + uint32_t bar_reg_value, bar_lower_bits; + + while(offset <= TYPE1_BAR_MAX_OFF) + { + pal_pci_cfg_read(bus, dev, func, offset, &bar_reg_value); + if (BAR_REG(bar_reg_value) == BAR_64_BIT) + { + print(AVS_PRINT_INFO, "The BAR supports P_MEM 64-bit addr decoding capability\n", 0); + + /** BAR supports 64-bit address therefore, write all 1's + * to BARn and BARn+1 and identify the size requested + **/ + pal_pci_cfg_write(bus, dev, func, offset, 0xFFFFFFF0); + pal_pci_cfg_write(bus, dev, func, offset + 4, 0xFFFFFFFF); + pal_pci_cfg_read(bus, dev, func, offset, &bar_lower_bits); + bar_size = bar_lower_bits & BAR_MASK; + + pal_pci_cfg_read(bus, dev, func, offset + 4, &bar_reg_value); + bar_upper_bits = bar_reg_value; + bar_size = bar_size | (bar_upper_bits << 32 ); + + bar_size = ~bar_size + 1; + + /**If BAR size is 0, then BAR not implemented, move to next BAR**/ + if (bar_size == 0) + { + offset = offset + 8; + continue; + } + pal_pci_cfg_write(bus, dev, func, offset, g_rp_bar64_value); + pal_pci_cfg_write(bus, dev, func, offset + 4, g_rp_bar64_value >> 32); + offset = offset + 8; + } + + else + { + print(AVS_PRINT_INFO, "The BAR supports P_MEM 32-bit addr decoding capability\n", 0); + + /**BAR supports 32-bit address. Write all 1's + * to BARn and identify the size requested + **/ + pal_pci_cfg_write(bus, dev, func, offset, 0xFFFFFFF0); + pal_pci_cfg_read(bus, dev, func, offset, &bar_lower_bits); + bar_reg_value = bar_lower_bits & BAR_MASK; + bar_size = ~bar_reg_value + 1; + + /**If BAR size is 0, then BAR not implemented, move to next BAR**/ + if (bar_size == 0) + { + offset = offset + 4; + continue; + } + pal_pci_cfg_write(bus, dev, func, offset, g_rp_bar32_value); + print(AVS_PRINT_INFO, "Value written to BAR register is %x\n", g_rp_bar32_value); + g_rp_bar32_value = g_rp_bar32_value + bar_size; + offset = offset + 4; + } + } +} + + /** @brief This API programs all the BAR register in PCIe config space pointed by Bus, Device and Function for an End Point PCIe device @@ -196,7 +255,7 @@ void pal_pcie_program_bar_reg(uint32_t bus, uint32_t dev, uint32_t func) uint32_t np_bar_size = 0; uint32_t p_bar_size = 0, p_bar64_size = 0; - while(offset <= BAR_MAX_OFFSET) + while(offset <= TYPE0_BAR_MAX_OFF) { pal_pci_cfg_read(bus, dev, func, offset, &bar_reg_value); @@ -352,7 +411,10 @@ void pal_pcie_program_bar_reg(uint32_t bus, uint32_t dev, uint32_t func) pal_pci_cfg_read(bus, dev, func, offset, &bar_reg_value); if (BAR_REG(bar_reg_value) == BAR_64_BIT) + { + pal_pci_cfg_write(bus, dev, func, offset + 4, 0); offset = offset + 8; + } if (BAR_REG(bar_reg_value) == BAR_32_BIT) offset = offset + 4; } @@ -381,7 +443,7 @@ uint32_t pal_pcie_enumerate_device(uint32_t bus, uint32_t sec_bus) uint32_t bar32_p_limit; uint32_t bar32_np_limit; - if (bus == (g_pcie_info_table->block[index].end_bus_num)) + if (bus == ((g_pcie_info_table->block[pcie_index].end_bus_num) + 1)) return sub_bus; uint32_t bar32_p_base = g_bar32_p_start; @@ -407,7 +469,7 @@ uint32_t pal_pcie_enumerate_device(uint32_t bus, uint32_t sec_bus) pal_pci_cfg_read(bus, dev, func, HEADER_OFFSET, &header_value); if (PCIE_HEADER_TYPE(header_value) == TYPE1_HEADER) { - print(AVS_PRINT_INFO, "TYPE1 HEADER found\n", 0); + print(AVS_PRINT_INFO, "\n\nTYPE1 HEADER found", 0); /* Enable memory access, Bus master enable and I/O access*/ pal_pci_cfg_read(bus, dev, func, COMMAND_REG_OFFSET, &com_reg_value); @@ -428,6 +490,9 @@ uint32_t pal_pcie_enumerate_device(uint32_t bus, uint32_t sec_bus) /*Obtain the start memory base address and the final memory base address of 64 bit BAR*/ get_resource_base_64(bus, dev, func, bar64_p_base, g_bar64_p_max); + /* Update the BAR values of Type 1 Devices */ + pal_pcie_rp_program_bar(bus, dev, func); + /*Update the base and limit values*/ bar32_p_base = g_bar32_p_start; bar32_np_base = g_bar32_np_start; @@ -436,7 +501,7 @@ uint32_t pal_pcie_enumerate_device(uint32_t bus, uint32_t sec_bus) if (PCIE_HEADER_TYPE(header_value) == TYPE0_HEADER) { - print(AVS_PRINT_INFO, "END POINT found\n", 0); + print(AVS_PRINT_INFO, "\n\nEND POINT found", 0); pal_pcie_program_bar_reg(bus, dev, func); sub_bus = sec_bus - 1; } @@ -464,7 +529,7 @@ pal_clear_pri_bus() uint32_t header_value; uint32_t vendor_id; - for (bus = 0; bus <= g_pcie_info_table->block[index].end_bus_num; bus++) + for (bus = 0; bus <= g_pcie_info_table->block[pcie_index].end_bus_num; bus++) { for (dev = 0; dev < PCIE_MAX_DEV; dev++) { @@ -496,16 +561,16 @@ void pal_pcie_enumerate(void) } print(AVS_PRINT_INFO, "\nStarting Enumeration \n", 0); - while (index < g_pcie_info_table->num_entries) + while (pcie_index < g_pcie_info_table->num_entries) { - pri_bus = g_pcie_info_table->block[index].start_bus_num; + pri_bus = g_pcie_info_table->block[pcie_index].start_bus_num; sec_bus = pri_bus + 1; pal_pcie_enumerate_device(pri_bus, sec_bus); pal_clear_pri_bus(); - index++; + pcie_index++; } enumerate = 0; - index = 0; + pcie_index = 0; } /** diff --git a/platform/pal_baremetal/src/pal_pe.c b/platform/pal_baremetal/common/src/pal_pe.c similarity index 97% rename from platform/pal_baremetal/src/pal_pe.c rename to platform/pal_baremetal/common/src/pal_pe.c index 358ceb1b..5cf460a7 100644 --- a/platform/pal_baremetal/src/pal_pe.c +++ b/platform/pal_baremetal/common/src/pal_pe.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,9 +15,9 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" -#include "include/platform_override_struct.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" +#include "platform_override_struct.h" extern PE_INFO_TABLE platform_pe_cfg; extern PLATFORM_OVERRIDE_CACHE_INFO_TABLE platform_cache_cfg; @@ -86,7 +86,7 @@ PalAllocateSecondaryStack(uint64_t mpidr) if (gSecondaryPeStack == NULL) { - gSecondaryPeStack = pal_mem_alloc(NumPe * SIZE_STACK_SECONDARY_PE); + gSecondaryPeStack = pal_aligned_alloc(MEM_ALIGN_4K, NumPe * SIZE_STACK_SECONDARY_PE); if (gSecondaryPeStack == NULL){ print(AVS_PRINT_ERR, "FATAL - Allocation for Secondary stack failed \n", 0); } diff --git a/platform/pal_baremetal/src/pal_peripherals.c b/platform/pal_baremetal/common/src/pal_peripherals.c similarity index 97% rename from platform/pal_baremetal/src/pal_peripherals.c rename to platform/pal_baremetal/common/src/pal_peripherals.c index 47ed38c8..e9fa058a 100644 --- a/platform/pal_baremetal/src/pal_peripherals.c +++ b/platform/pal_baremetal/common/src/pal_peripherals.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020-2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,9 +15,9 @@ * limitations under the License. **/ -#include "include/pal_pcie_enum.h" -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" +#include "pal_pcie_enum.h" +#include "pal_common_support.h" +#include "platform_override_struct.h" extern PLATFORM_OVERRIDE_UART_INFO_TABLE platform_uart_cfg; extern PLATFORM_OVERRIDE_MEMORY_INFO_TABLE platform_mem_cfg; @@ -124,7 +124,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable) } per_info->type = 0xFF; //indicate end of table - + (void) StartBdf; } /** diff --git a/platform/pal_baremetal/common/src/pal_pl011_uart.c b/platform/pal_baremetal/common/src/pal_pl011_uart.c new file mode 100644 index 00000000..4391b35c --- /dev/null +++ b/platform/pal_baremetal/common/src/pal_pl011_uart.c @@ -0,0 +1,93 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include "pal_pl011_uart.h" + +static volatile uint64_t g_uart = PLATFORM_UART_BASE; +static uint8_t is_uart_init_done; + +/** + * @brief - This function initializes the UART + * @param - uart_base_addr: Base address of UART + * @return - none +**/ +static void pal_driver_uart_pl011_init(void) +{ + uint32_t bauddiv = (UART_PL011_CLK_IN_HZ * 4) / UART_PL011_BAUDRATE; + + /* Disable uart before programming */ + ((pal_uart_t *)g_uart)->uartcr &= ~UART_PL011_UARTCR_EN_MASK; + + /* Write the IBRD */ + ((pal_uart_t *)g_uart)->uartibrd = bauddiv >> 6; + + /* Write the FBRD */ + ((pal_uart_t *)g_uart)->uartfbrd = bauddiv & 0x3F; + + /* Set line of control */ + ((pal_uart_t *)g_uart)->uartlcr_h = UART_PL011_LINE_CONTROL; + + /* Clear any pending errors */ + ((pal_uart_t *)g_uart)->uartecr = 0; + + /* Enable tx, rx, and uart overall */ + ((pal_uart_t *)g_uart)->uartcr = UART_PL011_UARTCR_EN_MASK + | UART_PL011_UARTCR_TX_EN_MASK; +} + +/** + * @brief - This function checks for empty TX FIFO + * @param - none + * @return - status +**/ +static int pal_driver_uart_pl011_is_tx_empty(void) +{ + if ((((pal_uart_t *)g_uart)->uartcr & UART_PL011_UARTCR_EN_MASK) && + /* UART is enabled */ + (((pal_uart_t *)g_uart)->uartcr & UART_PL011_UARTCR_TX_EN_MASK) && + /* Transmit is enabled */ + ((((pal_uart_t *)g_uart)->uartfr & UART_PL011_UARTFR_TX_FIFO_FULL) == 0)) + { + return 1; + } else + { + return 0; + } +} + +/** + * @brief - This function checks for empty TX FIFO and writes to FIFO register + * @param - char to be written + * @return - none +**/ +void pal_driver_uart_pl011_putc(int c) +{ + const uint8_t pdata = (uint8_t)c; + + if (is_uart_init_done == 0) + { + pal_driver_uart_pl011_init(); + is_uart_init_done = 1; + } + + /* ensure TX buffer to be empty */ + while (!pal_driver_uart_pl011_is_tx_empty()) + ; + + /* write the data (upper 24 bits are reserved) */ + ((pal_uart_t *)g_uart)->uartdr = pdata; +} diff --git a/platform/pal_baremetal/src/pal_pmu.c b/platform/pal_baremetal/common/src/pal_pmu.c similarity index 96% rename from platform/pal_baremetal/src/pal_pmu.c rename to platform/pal_baremetal/common/src/pal_pmu.c index 957c2335..3e26aecb 100644 --- a/platform/pal_baremetal/src/pal_pmu.c +++ b/platform/pal_baremetal/common/src/pal_pmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,9 +15,9 @@ * limitations under the License. **/ -#include "include/platform_override_struct.h" -#include "include/pal_pmu.h" -#include "include/pal_common_support.h" +#include "platform_override_struct.h" +#include "pal_pmu.h" +#include "pal_common_support.h" extern PLATFORM_OVERRIDE_PMU_INFO_TABLE platform_pmu_cfg; @@ -55,7 +55,7 @@ pal_pmu_dump_info_table(PMU_INFO_TABLE *PmuTable) /** @brief This API fills in the PMU_INFO_TABLE with information about local and system - timers in the system. this employs baremetal platform specific data. + timers in the system. this employs baremetal platform specific data. @param PmuTable - Address where the PMU information needs to be filled. diff --git a/platform/pal_baremetal/src/pal_ras.c b/platform/pal_baremetal/common/src/pal_ras.c similarity index 98% rename from platform/pal_baremetal/src/pal_ras.c rename to platform/pal_baremetal/common/src/pal_ras.c index c39740aa..ce791db6 100644 --- a/platform/pal_baremetal/src/pal_ras.c +++ b/platform/pal_baremetal/common/src/pal_ras.c @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/platform_override_struct.h" +#include "pal_common_support.h" +#include "platform_override_struct.h" extern RAS_INFO_TABLE platform_ras_cfg; extern PLATFORM_OVERRIDE_RAS_NODE_DATA_INFO platform_ras_node_data; @@ -139,6 +139,8 @@ void fill_node_interface_data ( uint32_t node_index ) { + (void) RasInfoTable; + curr_node->intf_info.intf_type = platform_ras_node_interface.intf_info[node_index].intf_type; curr_node->intf_info.flags = platform_ras_node_interface.intf_info[node_index].flags; @@ -162,6 +164,7 @@ void fill_node_interrupt_data ( uint32_t node_index ) { + (void) RasInfoTable; uint32_t count = 0; for (count = 0; count < curr_node->num_intr_entries; count++) diff --git a/platform/pal_baremetal/src/pal_smmu.c b/platform/pal_baremetal/common/src/pal_smmu.c similarity index 93% rename from platform/pal_baremetal/src/pal_smmu.c rename to platform/pal_baremetal/common/src/pal_smmu.c index 036be2ce..fa104d8b 100644 --- a/platform/pal_baremetal/src/pal_smmu.c +++ b/platform/pal_baremetal/common/src/pal_smmu.c @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/pal_common_support.h" -#include "include/pal_pcie_enum.h" +#include "pal_common_support.h" +#include "pal_pcie_enum.h" #define SMMU_V3_IDR1 0x4 #define SMMU_V3_IDR1_PASID_SHIFT 6 diff --git a/platform/pal_baremetal/src/pal_timer_wd.c b/platform/pal_baremetal/common/src/pal_timer_wd.c similarity index 94% rename from platform/pal_baremetal/src/pal_timer_wd.c rename to platform/pal_baremetal/common/src/pal_timer_wd.c index c4352dea..970037bf 100644 --- a/platform/pal_baremetal/src/pal_timer_wd.c +++ b/platform/pal_baremetal/common/src/pal_timer_wd.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -15,8 +15,8 @@ * limitations under the License. **/ -#include "include/platform_override_struct.h" -#include "include/pal_common_support.h" +#include "platform_override_struct.h" +#include "pal_common_support.h" extern PLATFORM_OVERRIDE_TIMER_INFO_TABLE platform_timer_cfg; extern WD_INFO_TABLE platform_wd_cfg; @@ -36,7 +36,7 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable) uint32_t Index; - if (TimerTable == NULL || TimerTable->gt_info == NULL) + if (TimerTable == NULL ) return; TimerTable->header.num_platform_timer = 0; diff --git a/platform/pal_baremetal/juno/include/platform_override.h b/platform/pal_baremetal/juno/include/platform_override.h deleted file mode 100644 index 90d26469..00000000 --- a/platform/pal_baremetal/juno/include/platform_override.h +++ /dev/null @@ -1,201 +0,0 @@ -/** @file - * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - - -/* - *Secure EL1 timer Flags, Non-Secure EL1 timer Flags, EL2 timer Flags, - * and Virtual timer Flags all can have the same definition as follows. - */ -#define INTERRUPT_IS_LEVEL_TRIGGERED 0x0 -#define INTERRUPT_IS_EDGE_TRIGGERED 0x1 -#define INTERRUPT_IS_ACTIVE_HIGH 0x0 -#define INTERRUPT_IS_ACTIVE_LOW 0x1 - -#define TIMER_MODE INTERRUPT_IS_LEVEL_TRIGGERED -#define TIMER_POLARITY INTERRUPT_IS_ACTIVE_LOW - -#define TIMER_IS_NON_SECURE 0x0 -#define TIMER_IS_SECURE 0x1 - -#define TIMER_IS_ALWAYS_ON_INCAPABLE 0x0 -#define TIMER_IS_ALWAYS_ON_CAPABLE 0x1 - -/* Timer platform config parameters */ -#define PLATFORM_OVERRIDE_S_EL1_TIMER_FLAGS ((TIMER_POLARITY << 1) | (TIMER_MODE << 0)) -#define PLATFORM_OVERRIDE_NS_EL1_TIMER_FLAGS ((TIMER_POLARITY << 1) | (TIMER_MODE << 0)) -#define PLATFORM_OVERRIDE_NS_EL2_TIMER_FLAGS ((TIMER_POLARITY << 1) | (TIMER_MODE << 0)) -#define PLATFORM_OVERRIDE_VIRTUAL_TIMER_FLAGS ((TIMER_POLARITY << 1) | (TIMER_MODE << 0)) -#define PLATFORM_OVERRIDE_S_EL1_TIMER_GSIV 0x1D -#define PLATFORM_OVERRIDE_NS_EL1_TIMER_GSIV 0x1E -#define PLATFORM_OVERRIDE_NS_EL2_TIMER_GSIV 0x1A -#define PLATFORM_OVERRIDE_VIRTUAL_TIMER_GSIV 0x1B -#define PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV 28 -#define PLATFORM_OVERRIDE_PLATFORM_TIMER_COUNT 0x2 - -#define PLATFORM_OVERRIDE_SYS_TIMER_TYPE 0x2001 -#define PLATFORM_OVERRIDE_TIMER_TYPE PLATFORM_OVERRIDE_SYS_TIMER_TYPE -#define PLATFORM_OVERRIDE_TIMER_COUNT 0x2 -#define PLATFORM_OVERRIDE_TIMER_CNTCTL_BASE 0x2a810000 - -#define PLATFORM_OVERRIDE_TIMER_CNTBASE_0 0x2a830000 -#define PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_0 0xFFFFFFFFFFFFFFFF -#define PLATFORM_OVERRIDE_TIMER_GSIV_0 0x5c -#define PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_0 0x0 -#define PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_0 0x0 -#define PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_0 0x0 -#define PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_0 ((TIMER_IS_ALWAYS_ON_CAPABLE << 1) | (TIMER_IS_NON_SECURE << 0)) -#define PLATFORM_OVERRIDE_TIMER_FLAGS_0 ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_0 << 16) | \ - (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_0 << 8) | \ - (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_0)) - -#define PLATFORM_OVERRIDE_TIMER_CNTBASE_1 0x2a820000 -#define PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_1 0xFFFFFFFFFFFFFFFF -#define PLATFORM_OVERRIDE_TIMER_GSIV_1 0x5B -#define PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_1 0x0 -#define PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1 0x0 -#define PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1 0x0 -#define PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1 ((TIMER_IS_ALWAYS_ON_CAPABLE << 1) | (TIMER_IS_SECURE << 0)) -#define PLATFORM_OVERRIDE_TIMER_FLAGS_1 ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1 << 16) | \ - (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1 << 8) | \ - (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1)) - -/* Watchdog platform config parameters */ -#define WD_MODE INTERRUPT_IS_LEVEL_TRIGGERED -#define WD_POLARITY INTERRUPT_IS_ACTIVE_HIGH - -#define WD_IS_NON_SECURE 0x0 -#define WD_IS_SECURE 0x1 - -#define PLATFORM_OVERRIDE_WD_TIMER_COUNT 0x1 -#define PLATFORM_OVERRIDE_WD_REFRESH_BASE 0x2A450000 -#define PLATFORM_OVERRIDE_WD_CTRL_BASE 0x2A440000 -#define PLATFORM_OVERRIDE_WD_GSIV 0x5D -#define PLATFORM_OVERRIDE_WD_FLAGS ((WD_IS_NON_SECURE << 2) | (WD_POLARITY << 1) | (WD_MODE << 0)) - - -/* GIC platform config parameters */ -#define PLATFORM_OVERRIDE_GIC_VERSION 0x00 -#define PLATFORM_OVERRIDE_CORE_COUNT 0x4 -#define PLATFORM_OVERRIDE_CLUSTER_COUNT 0x2 -#define PLATFORM_OVERRIDE_GICC_COUNT (PLATFORM_OVERRIDE_CORE_COUNT * PLATFORM_OVERRIDE_CLUSTER_COUNT) -#define PLATFORM_OVERRIDE_GICD_COUNT 0x1 -#define PLATFORM_OVERRIDE_GICRD_COUNT (PLATFORM_OVERRIDE_CORE_COUNT * PLATFORM_OVERRIDE_CLUSTER_COUNT) -#define PLATFORM_OVERRIDE_GICITS_COUNT 0x1 -#define PLATFORM_OVERRIDE_GICC_TYPE 0x1000 -#define PLATFORM_OVERRIDE_GICD_TYPE 0x1001 -#define PLATFORM_OVERRIDE_GICRD_TYPE 0x1002 -#define PLATFORM_OVERRIDE_GICITS_TYPE 0x1003 -#define PLATFORM_OVERRIDE_GICC_BASE 0x30000000 -#define PLATFORM_OVERRIDE_GICD_BASE 0x30000000 -#define PLATFORM_OVERRIDE_GICRD_BASE 0x300C0000 -#define PLATFORM_OVERRIDE_GICITS_BASE 0x30040000 - - -/* PE platform config paramaters */ -#define PLATFORM_OVERRIDE_PE_CNT 0x8 -#define PLATFORM_OVERRIDE_PE0_INDEX 0x0 -#define PLATFORM_OVERRIDE_PE0_MPIDR 0x0 -#define PLATFORM_OVERRIDE_PE0_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE1_INDEX 0x1 -#define PLATFORM_OVERRIDE_PE1_MPIDR 0x100 -#define PLATFORM_OVERRIDE_PE1_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE2_INDEX 0x2 -#define PLATFORM_OVERRIDE_PE2_MPIDR 0x200 -#define PLATFORM_OVERRIDE_PE2_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE3_INDEX 0x3 -#define PLATFORM_OVERRIDE_PE3_MPIDR 0x300 -#define PLATFORM_OVERRIDE_PE3_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE4_INDEX 0x4 -#define PLATFORM_OVERRIDE_PE4_MPIDR 0x10000 -#define PLATFORM_OVERRIDE_PE4_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE5_INDEX 0x5 -#define PLATFORM_OVERRIDE_PE5_MPIDR 0x10100 -#define PLATFORM_OVERRIDE_PE5_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE6_INDEX 0x6 -#define PLATFORM_OVERRIDE_PE6_MPIDR 0x10200 -#define PLATFORM_OVERRIDE_PE6_PMU_GSIV 0x17 -#define PLATFORM_OVERRIDE_PE7_INDEX 0x7 -#define PLATFORM_OVERRIDE_PE7_MPIDR 0x10300 -#define PLATFORM_OVERRIDE_PE7_PMU_GSIV 0x17 - -typedef struct { - UINT32 pe_num; - UINT64 mpidr; - UINT32 pmu_gsiv; -} PLATFORM_OVERRIDE_PE_INFO_ENTRY; - -typedef struct { - UINT32 num_of_pe; - PLATFORM_OVERRIDE_PE_INFO_ENTRY pe_info[PLATFORM_OVERRIDE_PE_CNT]; -} PLATFORM_OVERRIDE_PE_INFO_TABLE; - -typedef struct { - UINT32 gic_version; - UINT32 num_gicc; - UINT32 num_gicd; - UINT32 num_gicrd; - UINT32 num_gicits; - UINT32 gicc_type; - UINT32 gicd_type; - UINT32 gicrd_type; - UINT32 gicits_type; - UINT64 gicc_base[PLATFORM_OVERRIDE_GICC_COUNT]; - UINT64 gicd_base[PLATFORM_OVERRIDE_GICD_COUNT]; - UINT64 gicrd_base[PLATFORM_OVERRIDE_GICRD_COUNT]; - UINT64 gicits_base[PLATFORM_OVERRIDE_GICITS_COUNT]; -} PLATFORM_OVERRIDE_GIC_INFO_TABLE; - -typedef struct { - UINT32 s_el1_timer_flags; - UINT32 ns_el1_timer_flags; - UINT32 el2_timer_flags; - UINT32 s_el1_timer_gsiv; - UINT32 ns_el1_timer_gsiv; - UINT32 el2_timer_gsiv; - UINT32 virtual_timer_flags; - UINT32 virtual_timer_gsiv; - UINT32 el2_virt_timer_gsiv; - UINT32 num_platform_timer; -} PLATFORM_OVERRIDE_TIMER_INFO_HDR; - -typedef struct { - UINT32 type; - UINT32 timer_count; - UINT64 block_cntl_base; - UINT64 GtCntBase[PLATFORM_OVERRIDE_TIMER_COUNT]; - UINT64 GtCntEl0Base[PLATFORM_OVERRIDE_TIMER_COUNT]; - UINT32 gsiv[PLATFORM_OVERRIDE_TIMER_COUNT]; - UINT32 virt_gsiv[PLATFORM_OVERRIDE_TIMER_COUNT]; - UINT32 flags[PLATFORM_OVERRIDE_TIMER_COUNT]; -} PLATFORM_OVERRIDE_TIMER_INFO_GTBLOCK; - -typedef struct { - PLATFORM_OVERRIDE_TIMER_INFO_HDR header; - PLATFORM_OVERRIDE_TIMER_INFO_GTBLOCK gt_info; -} PLATFORM_OVERRIDE_TIMER_INFO_TABLE; - -typedef struct { - UINT64 wd_ctrl_base; - UINT64 wd_refresh_base; - UINT32 wd_gsiv; - UINT32 wd_flags; -} PLATFORM_OVERRIDE_WD_INFO_BLOCK; - -typedef struct { - UINT32 num_wd; - PLATFORM_OVERRIDE_WD_INFO_BLOCK wd_info[PLATFORM_OVERRIDE_WD_TIMER_COUNT]; -} PLATFORM_OVERRIDE_WD_INFO_TABLE; diff --git a/platform/pal_baremetal/juno/src/pal_gic.c b/platform/pal_baremetal/juno/src/pal_gic.c deleted file mode 100644 index fc7d3eb0..00000000 --- a/platform/pal_baremetal/juno/src/pal_gic.c +++ /dev/null @@ -1,133 +0,0 @@ -/** @file - * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - - -#include "include/platform_override.h" - -extern PLATFORM_OVERRIDE_GIC_INFO_TABLE platform_gic_cfg; - - -/** - @brief Populate information about the GIC sub-system at the input address. - - @param GicTable Address of the memory region where this information is to be filled in - - @return None -**/ -VOID -pal_gic_create_info_table(GIC_INFO_TABLE *GicTable) -{ - UINT32 Index; - UINT32 InfoIndex = 0; - - if (GicTable == NULL) { - return; - } - - GicTable->header.gic_version = platform_gic_cfg.gic_version; - GicTable->header.num_gicrd = platform_gic_cfg.num_gicrd; - GicTable->header.num_gicd = platform_gic_cfg.num_gicd; - GicTable->header.num_its = platform_gic_cfg.num_gicits; - - for (Index = 0; Index < platform_gic_cfg.num_gicc; Index++) { - GicTable->gic_info[InfoIndex].type = PLATFORM_OVERRIDE_GICC_TYPE; - GicTable->gic_info[InfoIndex++].base = platform_gic_cfg.gicc_base[Index]; - } - - for (Index = 0; Index < platform_gic_cfg.num_gicrd; Index++) { - GicTable->gic_info[InfoIndex].type = PLATFORM_OVERRIDE_GICRD_TYPE; - GicTable->gic_info[InfoIndex++].base = platform_gic_cfg.gicrd_base[Index]; - } - - for (Index = 0; Index < platform_gic_cfg.num_gicd; Index++) { - GicTable->gic_info[InfoIndex].type = PLATFORM_OVERRIDE_GICD_TYPE; - GicTable->gic_info[InfoIndex++].base = platform_gic_cfg.gicd_base[Index]; - } - - for (Index = 0; Index < platform_gic_cfg.num_gicits; Index++) { - GicTable->gic_info[InfoIndex].type = PLATFORM_OVERRIDE_GICITS_TYPE; - GicTable->gic_info[InfoIndex++].base = platform_gic_cfg.gicits_base[Index]; - } - - GicTable->gic_info[InfoIndex].type = 0xFF; //Indicate end of data - - -} - -/** - @brief Enable the interrupt in the GIC Distributor and GIC CPU Interface and hook - the interrupt service routine for the IRQ to the Baremetal Framework - - @param int_id Interrupt ID which needs to be enabled and service routine installed for - @param isr Function pointer of the Interrupt service routine - - @return Status of the operation -**/ -UINT32 -pal_gic_install_isr(UINT32 int_id, VOID (*isr)()) -{ - - UINT32 Status; - - /* TO DO - Baremetal - * Place holder to register the interrupt - */ - - return Status; -} - -/** - @brief Indicate that processing of interrupt is complete by writing to - End of interrupt register in the GIC CPU Interface - - @param int_id Interrupt ID which needs to be acknowledged that it is complete - - @return Status of the operation -**/ -UINT32 -pal_gic_end_of_interrupt(UINT32 int_id) -{ - - UINT32 Status; - - /* TO DO - Baremetal - * Place holder to set EOI in GICC - */ - - return Status; -} - -/** - @brief Set Trigger type Edge/Level - - @param int_id Interrupt ID which needs to be enabled and service routine installed for - @param trigger_type Interrupt Trigger Type Edge/Trigger - - @return Status of the operation -**/ -UINT32 -pal_gic_set_intr_trigger(UINT32 int_id, INTR_TRIGGER_INFO_TYPE_e trigger_type) -{ - - UINT32 Status; - - /* TO Do - Baremetal - * Place holder to set interrupt trigger type - */ - - return Status; -} diff --git a/platform/pal_baremetal/juno/src/pal_pe.c b/platform/pal_baremetal/juno/src/pal_pe.c deleted file mode 100644 index ce631e66..00000000 --- a/platform/pal_baremetal/juno/src/pal_pe.c +++ /dev/null @@ -1,282 +0,0 @@ -/** @file - * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - - -#include "include/platform_override.h" - -extern PLATFORM_OVERRIDE_PE_INFO_TABLE platform_pe_cfg; -UINT8 *gSecondaryPeStack; -UINT64 gMpidrMax; - -#define SIZE_STACK_SECONDARY_PE 0x100 //256 bytes per core -#define UPDATE_AFF_MAX(src,dest,mask) ((dest & mask) > (src & mask) ? (dest & mask) : (src & mask)) - -UINT64 -pal_get_madt_ptr(); - -VOID -ArmCallSmc ( - IN OUT ARM_SMC_ARGS *Args - ); - - -/** - @brief Return the base address of the region allocated for Stack use for the Secondary - PEs. - @param None - @return base address of the Stack -**/ -UINT64 -PalGetSecondaryStackBase() -{ - - return (UINT64)gSecondaryPeStack; -} - -/** - @brief Returns the Max of each 8-bit Affinity fields in MPIDR. - @param None - @return Max MPIDR -**/ -UINT64 -PalGetMaxMpidr() -{ - - return gMpidrMax; -} - -/** - @brief Allocate memory region for secondary PE stack use. SIZE of stack for each PE - is a #define - - @param Number of PEs - - @return None -**/ -VOID -PalAllocateSecondaryStack(UINT64 mpidr) -{ - UINT32 Status; - UINT32 NumPe, Aff0, Aff1, Aff2, Aff3; - - Aff0 = ((mpidr & 0x00000000ff) >> 0); - Aff1 = ((mpidr & 0x000000ff00) >> 8); - Aff2 = ((mpidr & 0x0000ff0000) >> 16); - Aff3 = ((mpidr & 0xff00000000) >> 32); - - NumPe = ((Aff3+1) * (Aff2+1) * (Aff1+1) * (Aff0+1)); - - if (gSecondaryPeStack == NULL) { - - /* TO DO - Baremetal - * Place holder to allocate memory to gSecondaryPeStack - */ - - } - pal_pe_data_cache_ops_by_va((UINT64)&gSecondaryPeStack, CLEAN_AND_INVALIDATE); - } - -} - -/** - @brief This API fills in the PE_INFO Table with information about the PEs in the - system. This is achieved by parsing the ACPI - MADT table. - - @param PeTable - Address where the PE information needs to be filled. - - @return None -**/ -VOID -pal_pe_create_info_table(PE_INFO_TABLE *PeTable) -{ - UINT64 MpidrAff0Max = 0; - UINT64 MpidrAff1Max = 0; - UINT64 MpidrAff2Max = 0; - UINT64 MpidrAff3Max = 0; - UINT32 PeIndex = 0; - - if (PeTable == NULL) { - return; - } - - PeTable->header.num_of_pe = platform_pe_cfg.num_of_pe; - if (PeTable->header.num_of_pe == 0) { - return; - } - - while (PeIndex < PeTable->header.num_of_pe) { - - PeTable->pe_info[PeIndex].mpidr = platform_pe_cfg.pe_info[PeIndex].mpidr; - PeTable->pe_info[PeIndex].pe_num = PeIndex; - PeTable->pe_info[PeIndex].pmu_gsiv = platform_pe_cfg.pe_info[PeIndex].pmu_gsiv; - pal_pe_data_cache_ops_by_va((UINT64)(&PeTable->pe_info[PeIndex]), CLEAN_AND_INVALIDATE); - - MpidrAff0Max = UPDATE_AFF_MAX(MpidrAff0Max, PeTable->pe_info[PeIndex].mpidr, 0x000000ff); - MpidrAff1Max = UPDATE_AFF_MAX(MpidrAff1Max, PeTable->pe_info[PeIndex].mpidr, 0x0000ff00); - MpidrAff2Max = UPDATE_AFF_MAX(MpidrAff2Max, PeTable->pe_info[PeIndex].mpidr, 0x00ff0000); - MpidrAff3Max = UPDATE_AFF_MAX(MpidrAff3Max, PeTable->pe_info[PeIndex].mpidr, 0xff00000000); - - PeIndex++; - }; - - gMpidrMax = MpidrAff0Max | MpidrAff1Max | MpidrAff2Max | MpidrAff3Max; - pal_pe_data_cache_ops_by_va((UINT64)PeTable, CLEAN_AND_INVALIDATE); - pal_pe_data_cache_ops_by_va((UINT64)&gMpidrMax, CLEAN_AND_INVALIDATE); - PalAllocateSecondaryStack(gMpidrMax); - -} - -/** - @brief Install Exception Handler through BAREMETAL Interrupt registration - - @param ExceptionType - AARCH64 Exception type - @param esr - Function pointer of the exception handler - - @return status of the API -**/ -UINT32 -pal_pe_install_esr(UINT32 ExceptionType, VOID (*esr)(UINT64, VOID *)) -{ - - UINT32 Status; - - /* TO DO - Baremetal - * Place holder to: - * 1. Unregister the default exception handler - * 2. Register the handler to receive interrupts - */ - - return Status; -} - -/** - @brief Make the SMC call using AARCH64 Assembly code - SMC calls can take up to 7 arguments and return up to 4 return values. - Therefore, the 4 first fields in the ARM_SMC_ARGS structure are used - for both input and output values. - - @param Argumets to pass to the EL3 firmware - - @return None -**/ -VOID -pal_pe_call_smc(ARM_SMC_ARGS *ArmSmcArgs) -{ - /* TO DO - Baremetal - * Place holder to call baremetal SMC API - */ -} - -VOID -ModuleEntryPoint(); - -/** - @brief Make a PSCI CPU_ON call using SMC instruction. - Pass PAL Assembly code entry as the start vector for the PSCI ON call - - @param Argumets to pass to the EL3 firmware - - @return None -**/ -VOID -pal_pe_execute_payload(ARM_SMC_ARGS *ArmSmcArgs) -{ - ArmSmcArgs->Arg2 = (UINT64)ModuleEntryPoint; - pal_pe_call_smc(ArmSmcArgs); -} - -/** - @brief Update the ELR to return from exception handler to a desired address - - @param context - exception context structure - @param offset - address with which ELR should be updated - - @return None -**/ -VOID -pal_pe_update_elr(VOID *context, UINT64 offset) -{ - /* TO DO - Baremetal - * Place holder to save offset into context saving structure ELR - */ -} - -/** - @brief Get the Exception syndrome from Baremetal exception handler - - @param context - exception context structure - - @return ESR -**/ -UINT64 -pal_pe_get_esr(VOID *context) -{ - /*TO DO - Baremetal - * Place holder to return ESR from context saving structure - */ -} - -/** - @brief Get the FAR from Baremetal exception handler - - @param context - exception context structure - - @return FAR -**/ -UINT64 -pal_pe_get_far(VOID *context) -{ - /* TO DO - Baremetal - * Place holder to return FAR from context saving structure - */ -} - -VOID -DataCacheCleanInvalidateVA(UINT64 addr); - -VOID -DataCacheCleanVA(UINT64 addr); - -VOID -DataCacheInvalidateVA(UINT64 addr); - -/** - @brief Perform cache maintenance operation on an address - - @param addr - address on which cache ops to be performed - @param type - type of cache ops - - @return None -**/ -VOID -pal_pe_data_cache_ops_by_va(UINT64 addr, UINT32 type) -{ - switch(type){ - case CLEAN_AND_INVALIDATE: - DataCacheCleanInvalidateVA(addr); - break; - case CLEAN: - DataCacheCleanVA(addr); - break; - case INVALIDATE: - DataCacheInvalidateVA(addr); - break; - default: - DataCacheCleanInvalidateVA(addr); - } - -} diff --git a/platform/pal_baremetal/juno/src/pal_timer_wd.c b/platform/pal_baremetal/juno/src/pal_timer_wd.c deleted file mode 100644 index a524cf56..00000000 --- a/platform/pal_baremetal/juno/src/pal_timer_wd.c +++ /dev/null @@ -1,99 +0,0 @@ -/** @file - * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - -#include "include/platform_override.h" - -extern PLATFORM_OVERRIDE_TIMER_INFO_TABLE platform_timer_cfg; -extern PLATFORM_OVERRIDE_WD_INFO_TABLE platform_wd_cfg; - - -/** - @brief This API fills in the TIMER_INFO_TABLE with information about local and - system timers in the system from baremetal platform timer configuration - - @param TimerTable - Address where the Timer information needs to be filled - - @return None -**/ -VOID -pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable) -{ - UINT32 Index; - - if (TimerTable == NULL) - return; - - TimerTable->header.num_platform_timer = 0; - - TimerTable->header.s_el1_timer_flag = platform_timer_cfg.header.s_el1_timer_flags; - TimerTable->header.ns_el1_timer_flag = platform_timer_cfg.header.ns_el1_timer_flags; - TimerTable->header.el2_timer_flag = platform_timer_cfg.header.el2_timer_flags; - TimerTable->header.s_el1_timer_gsiv = platform_timer_cfg.header.s_el1_timer_gsiv; - TimerTable->header.ns_el1_timer_gsiv = platform_timer_cfg.header.ns_el1_timer_gsiv; - TimerTable->header.el2_timer_gsiv = platform_timer_cfg.header.el2_timer_gsiv; - TimerTable->header.virtual_timer_flag = platform_timer_cfg.header.virtual_timer_flags; - TimerTable->header.virtual_timer_gsiv = platform_timer_cfg.header.virtual_timer_gsiv; - TimerTable->header.el2_virt_timer_gsiv = platform_timer_cfg.header.el2_virt_timer_gsiv; - - TimerTable->gt_info->type = platform_timer_cfg.gt_info.type; - TimerTable->gt_info->block_cntl_base = platform_timer_cfg.gt_info.block_cntl_base; - TimerTable->gt_info->timer_count = platform_timer_cfg.gt_info.timer_count; - - for (Index = 0; Index < TimerTable->gt_info->timer_count; Index++) { - - TimerTable->gt_info->GtCntBase[Index] = platform_timer_cfg.gt_info.GtCntBase[Index]; - TimerTable->gt_info->GtCntEl0Base[Index] = platform_timer_cfg.gt_info.GtCntEl0Base[Index]; - TimerTable->gt_info->gsiv[Index] = platform_timer_cfg.gt_info.gsiv[Index]; - TimerTable->gt_info->virt_gsiv[Index] = platform_timer_cfg.gt_info.virt_gsiv[Index]; - TimerTable->gt_info->flags[Index] = platform_timer_cfg.gt_info.flags[Index]; - - TimerTable->header.num_platform_timer++; - - } - -} - -/** - @brief This API fills in the WD_INFO_TABLE with information about Watchdogs - in the system from baremetal platform watchdog configuration - - @param WdTable - Address where the Timer information needs to be filled. - - @return None -**/ - -VOID -pal_wd_create_info_table(WD_INFO_TABLE *WdTable) -{ - UINT32 Index; - - if (WdTable == NULL) { - return; - } - - WdTable->header.num_wd = platform_wd_cfg.num_wd; - - for (Index = 0; Index < WdTable->header.num_wd; Index++) { - - WdTable->wd_info[Index].wd_refresh_base = platform_wd_cfg.wd_info[Index].wd_refresh_base; - WdTable->wd_info[Index].wd_ctrl_base = platform_wd_cfg.wd_info[Index].wd_ctrl_base; - WdTable->wd_info[Index].wd_gsiv = platform_wd_cfg.wd_info[Index].wd_gsiv; - WdTable->wd_info[Index].wd_flags = platform_wd_cfg.wd_info[Index].wd_flags; - - } - -} diff --git a/platform/pal_baremetal/juno/src/platform_cfg.c b/platform/pal_baremetal/juno/src/platform_cfg.c deleted file mode 100644 index 0d7c2d56..00000000 --- a/platform/pal_baremetal/juno/src/platform_cfg.c +++ /dev/null @@ -1,126 +0,0 @@ -/** @file - * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - -#include "include/platform_override.h" - -PLATFORM_OVERRIDE_PE_INFO_TABLE platform_pe_cfg = { - - .num_of_pe = PLATFORM_OVERRIDE_PE_CNT, - - .pe_info[0].pe_num = PLATFORM_OVERRIDE_PE0_INDEX, - .pe_info[0].mpidr = PLATFORM_OVERRIDE_PE0_MPIDR, - .pe_info[0].pmu_gsiv = PLATFORM_OVERRIDE_PE0_PMU_GSIV, - - .pe_info[1].pe_num = PLATFORM_OVERRIDE_PE1_INDEX, - .pe_info[1].mpidr = PLATFORM_OVERRIDE_PE1_MPIDR, - .pe_info[1].pmu_gsiv = PLATFORM_OVERRIDE_PE1_PMU_GSIV, - - .pe_info[2].pe_num = PLATFORM_OVERRIDE_PE2_INDEX, - .pe_info[2].mpidr = PLATFORM_OVERRIDE_PE2_MPIDR, - .pe_info[2].pmu_gsiv = PLATFORM_OVERRIDE_PE2_PMU_GSIV, - - .pe_info[3].pe_num = PLATFORM_OVERRIDE_PE3_INDEX, - .pe_info[3].mpidr = PLATFORM_OVERRIDE_PE3_MPIDR, - .pe_info[3].pmu_gsiv = PLATFORM_OVERRIDE_PE3_PMU_GSIV, - - .pe_info[4].pe_num = PLATFORM_OVERRIDE_PE4_INDEX, - .pe_info[4].mpidr = PLATFORM_OVERRIDE_PE4_MPIDR, - .pe_info[4].pmu_gsiv = PLATFORM_OVERRIDE_PE4_PMU_GSIV, - - .pe_info[5].pe_num = PLATFORM_OVERRIDE_PE5_INDEX, - .pe_info[5].mpidr = PLATFORM_OVERRIDE_PE5_MPIDR, - .pe_info[5].pmu_gsiv = PLATFORM_OVERRIDE_PE5_PMU_GSIV, - - .pe_info[6].pe_num = PLATFORM_OVERRIDE_PE6_INDEX, - .pe_info[6].mpidr = PLATFORM_OVERRIDE_PE6_MPIDR, - .pe_info[6].pmu_gsiv = PLATFORM_OVERRIDE_PE6_PMU_GSIV, - - .pe_info[7].pe_num = PLATFORM_OVERRIDE_PE7_INDEX, - .pe_info[7].mpidr = PLATFORM_OVERRIDE_PE7_MPIDR, - .pe_info[7].pmu_gsiv = PLATFORM_OVERRIDE_PE7_PMU_GSIV, - -}; - -PLATFORM_OVERRIDE_GIC_INFO_TABLE platform_gic_cfg = { - - .gic_version = PLATFORM_OVERRIDE_GIC_VERSION, - .num_gicc = PLATFORM_OVERRIDE_GICC_COUNT, - .num_gicd = PLATFORM_OVERRIDE_GICD_COUNT, - .num_gicrd = PLATFORM_OVERRIDE_GICRD_COUNT, - .num_gicits = PLATFORM_OVERRIDE_GICITS_COUNT, - - .gicc_base[0] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[1] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[2] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[3] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[4] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[5] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[6] = PLATFORM_OVERRIDE_GICC_BASE, - .gicc_base[7] = PLATFORM_OVERRIDE_GICC_BASE, - - .gicd_base[0] = PLATFORM_OVERRIDE_GICD_BASE, - - .gicrd_base[0] = PLATFORM_OVERRIDE_GICRD_BASE, - .gicrd_base[1] = PLATFORM_OVERRIDE_GICRD_BASE, - .gicrd_base[2] = PLATFORM_OVERRIDE_GICRD_BASE, - .gicrd_base[3] = PLATFORM_OVERRIDE_GICRD_BASE, - .gicrd_base[4] = PLATFORM_OVERRIDE_GICRD_BASE, - .gicrd_base[5] = PLATFORM_OVERRIDE_GICRD_BASE, - .gicrd_base[6] = PLATFORM_OVERRIDE_GICRD_BASE, - .gicrd_base[7] = PLATFORM_OVERRIDE_GICRD_BASE, - - .gicits_base[0] = PLATFORM_OVERRIDE_GICITS_BASE - -}; - - -PLATFORM_OVERRIDE_TIMER_INFO_TABLE platform_timer_cfg = { - - .header.s_el1_timer_flags = PLATFORM_OVERRIDE_S_EL1_TIMER_FLAGS, - .header.ns_el1_timer_flags = PLATFORM_OVERRIDE_NS_EL1_TIMER_FLAGS, - .header.el2_timer_flags = PLATFORM_OVERRIDE_NS_EL2_TIMER_FLAGS, - .header.s_el1_timer_gsiv = PLATFORM_OVERRIDE_S_EL1_TIMER_GSIV, - .header.ns_el1_timer_gsiv = PLATFORM_OVERRIDE_NS_EL1_TIMER_GSIV, - .header.el2_timer_gsiv = PLATFORM_OVERRIDE_NS_EL2_TIMER_GSIV, - .header.virtual_timer_flags = PLATFORM_OVERRIDE_VIRTUAL_TIMER_FLAGS, - .header.virtual_timer_gsiv = PLATFORM_OVERRIDE_VIRTUAL_TIMER_GSIV, - .header.el2_virt_timer_gsiv = PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV, - .header.num_platform_timer = PLATFORM_OVERRIDE_PLATFORM_TIMER_COUNT, - - .gt_info.type = PLATFORM_OVERRIDE_TIMER_TYPE, - .gt_info.timer_count = PLATFORM_OVERRIDE_TIMER_COUNT, - .gt_info.block_cntl_base = PLATFORM_OVERRIDE_TIMER_CNTCTL_BASE, - .gt_info.GtCntBase[0] = PLATFORM_OVERRIDE_TIMER_CNTBASE_0, - .gt_info.GtCntBase[1] = PLATFORM_OVERRIDE_TIMER_CNTBASE_1, - .gt_info.GtCntEl0Base[0] = PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_0, - .gt_info.GtCntEl0Base[1] = PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_1, - .gt_info.gsiv[0] = PLATFORM_OVERRIDE_TIMER_GSIV_0, - .gt_info.gsiv[1] = PLATFORM_OVERRIDE_TIMER_GSIV_1, - .gt_info.virt_gsiv[0] = PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_0, - .gt_info.virt_gsiv[1] = PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_1, - .gt_info.flags[0] = PLATFORM_OVERRIDE_TIMER_FLAGS_0, - .gt_info.flags[1] = PLATFORM_OVERRIDE_TIMER_FLAGS_1 - -}; - -PLATFORM_OVERRIDE_WD_INFO_TABLE platform_wd_cfg = { - .num_wd = PLATFORM_OVERRIDE_WD_TIMER_COUNT, - .wd_info[0].wd_ctrl_base = PLATFORM_OVERRIDE_WD_CTRL_BASE, - .wd_info[0].wd_refresh_base = PLATFORM_OVERRIDE_WD_REFRESH_BASE, - .wd_info[0].wd_gsiv = PLATFORM_OVERRIDE_WD_GSIV, - .wd_info[0].wd_flags = PLATFORM_OVERRIDE_WD_FLAGS -}; diff --git a/platform/pal_baremetal/pal.cmake b/platform/pal_baremetal/pal.cmake new file mode 100644 index 00000000..c560b8fc --- /dev/null +++ b/platform/pal_baremetal/pal.cmake @@ -0,0 +1,69 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +set(PAL_SRC + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_dma.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_exerciser.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_gic.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_iovirt.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_misc.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_pcie.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_pe.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_peripherals.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_pmu.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_ras.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/pal_bm_smmu.c + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/platform_cfg_fvp.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_dma.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_exerciser.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_gic.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_hmat.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_iovirt.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_misc.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_mpam.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_pcie_enumeration.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_pcie.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_pe.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_peripherals.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_pl011_uart.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_pmu.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_ras.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_smmu.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/pal_timer_wd.c + ${ROOT_DIR}/platform/pal_baremetal/common/src/AArch64/AvsTestInfra.S + ${ROOT_DIR}/platform/pal_baremetal/common/src/AArch64/ModuleEntryPoint.S + ${ROOT_DIR}/platform/pal_baremetal/common/src/AArch64/ArmSmc.S +) + +#Create compile list files +list(APPEND COMPILE_LIST ${PAL_SRC}) +set(COMPILE_LIST ${COMPILE_LIST} PARENT_SCOPE) + +# Create PAL library +add_library(${PAL_LIB} STATIC ${PAL_SRC}) + +target_include_directories(${PAL_LIB} PRIVATE + ${CMAKE_CURRENT_BINARY_DIR} + ${ROOT_DIR}/ + ${ROOT_DIR}/baremetal_app/ + ${ROOT_DIR}/platform/pal_baremetal/ + ${ROOT_DIR}/platform/pal_baremetal/common/include/ + ${ROOT_DIR}/platform/pal_baremetal/common/src/AArch64/ + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/include/ +) + +unset(PAL_SRC) diff --git a/platform/pal_baremetal/src/AArch64/ArmSmc.S b/platform/pal_baremetal/src/AArch64/ArmSmc.S deleted file mode 100644 index f1df2f52..00000000 --- a/platform/pal_baremetal/src/AArch64/ArmSmc.S +++ /dev/null @@ -1,63 +0,0 @@ -#/** @file -# Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -/* Private worker functions for ASM_PFX() */ -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -/* The __USER_LABEL_PREFIX__ macro predefined by GNUC represents - the prefix on symbols in assembly language.*/ -#define __USER_LABEL_PREFIX__ - -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - -#define GCC_ASM_IMPORT(func__) \ - .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - -.text -.align 3 - -GCC_ASM_EXPORT(ArmCallSmc) - -ASM_PFX(ArmCallSmc): - // Push x0 on the stack - The stack must always be quad-word aligned - str x0, [sp, #-16]! - - // Load the SMC arguments values into the appropriate registers - ldp x6, x7, [x0, #48] - ldp x4, x5, [x0, #32] - ldp x2, x3, [x0, #16] - ldp x0, x1, [x0, #0] - - smc #0 - - // Pop the ARM_SMC_ARGS structure address from the stack into x9 - ldr x9, [sp], #16 - - // Store the SMC returned values into the ARM_SMC_ARGS structure. - // A SMC call can return up to 4 values - we do not need to store back x4-x7. - stp x2, x3, [x9, #16] - stp x0, x1, [x9, #0] - - mov x0, x9 - - ret diff --git a/platform/pal_baremetal/src/AArch64/AvsTestInfra.S b/platform/pal_baremetal/src/AArch64/AvsTestInfra.S deleted file mode 100644 index 784cf115..00000000 --- a/platform/pal_baremetal/src/AArch64/AvsTestInfra.S +++ /dev/null @@ -1,59 +0,0 @@ -#/** @file -# Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -/* Private worker functions for ASM_PFX() */ -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -/* The __USER_LABEL_PREFIX__ macro predefined by GNUC represents - the prefix on symbols in assembly language.*/ -#define __USER_LABEL_PREFIX__ - -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - -#define GCC_ASM_IMPORT(func__) \ - .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - -.text -.align 3 - -GCC_ASM_EXPORT(DataCacheCleanInvalidateVA) -GCC_ASM_EXPORT(DataCacheInvalidateVA) -GCC_ASM_EXPORT(DataCacheCleanVA) - -ASM_PFX(DataCacheCleanInvalidateVA): - dc civac, x0 - dsb sy - isb - ret - -ASM_PFX(DataCacheCleanVA): - dc cvac, x0 - dsb ish - isb - ret - -ASM_PFX(DataCacheInvalidateVA): - dc ivac, x0 - dsb ish - isb - ret diff --git a/platform/pal_baremetal/src/AArch64/ModuleEntryPoint.S b/platform/pal_baremetal/src/AArch64/ModuleEntryPoint.S deleted file mode 100644 index 9df9a347..00000000 --- a/platform/pal_baremetal/src/AArch64/ModuleEntryPoint.S +++ /dev/null @@ -1,99 +0,0 @@ -#/** @file -# Copyright (c) 2020, 2022 Arm Limited or its affiliates. All rights reserved. -# SPDX-License-Identifier : Apache-2.0 -# -# Licensed under the Apache License, Version 2.0 (the "License"); -# you may not use this file except in compliance with the License. -# You may obtain a copy of the License at -# -# http://www.apache.org/licenses/LICENSE-2.0 -# -# Unless required by applicable law or agreed to in writing, software -# distributed under the License is distributed on an "AS IS" BASIS, -# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -# See the License for the specific language governing permissions and -# limitations under the License. -# -#**/ - -/* Private worker functions for ASM_PFX() */ -#define _CONCATENATE(a, b) __CONCATENATE(a, b) -#define __CONCATENATE(a, b) a ## b - -/* The __USER_LABEL_PREFIX__ macro predefined by GNUC represents - the prefix on symbols in assembly language.*/ -#define __USER_LABEL_PREFIX__ - -#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) - -#define GCC_ASM_EXPORT(func__) \ - .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ - .type ASM_PFX(func__), %function - -#define GCC_ASM_IMPORT(func__) \ - .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) - -.text -.align 3 - -GCC_ASM_IMPORT(ArmReadMpidr) -GCC_ASM_IMPORT(PalGetSecondaryStackBase) -GCC_ASM_IMPORT(PalGetMaxMpidr) -GCC_ASM_EXPORT(ModuleEntryPoint) - -StartupAddr: .8byte ASM_PFX(val_test_entry) -ASM_PFX(StackSize): .8byte 0x100 - -ASM_PFX(ModuleEntryPoint): - // Get ID of this CPU in Multicore system - bl ASM_PFX(ArmReadMpidr) - // Keep a copy of the MpId register value - mov x10, x0 - - // With this function: CorePos = (Aff3 x maxAff2 x maxAff1 x maxAff0) + - // (Aff2 x maxAff1 x maxAff0) + (Aff1 x maxAff0) + Aff0 - and x1, x0, 0xFF - and x2, x0, 0xFF00 - lsr x2, x2, 8 - and x3, x0, 0xFF0000 - lsr x3, x3, 16 - and x4, x0, 0xFF00000000 - lsr x4, x4, 32 - - bl ASM_PFX(PalGetMaxMpidr) - and x5, x0, 0xFF - add x5, x5, 1 - and x6, x0, 0xFF00 - lsr x6, x6, 8 - add x6, x6, 1 - and x7, x0, 0xFF0000 - lsr x7, x7, 16 - add x7, x7, 1 - and x8, x0, 0xFF00000000 - lsr x8, x8, 32 - add x8, x8, 1 // x8 has maxAff3, which is reserved for future use - - madd x0, x2, x5, x1 - mul x5, x5, x6 - madd x0, x3, x5, x0 - mul x5, x5, x7 - madd x0, x4, x5, x0 - - ldr x3, StackSize - mul x3, x3, x0 -_GetStackBase: - mov x0, 0 - //ldr x4, GetStackMem - //blr x4 - //ASM_PFX(pal_allocate_stack) - bl ASM_PFX(PalGetSecondaryStackBase) - add x0, x0, x3 - mov sp, x0 -_PrepareArguments: - - ldr x4, StartupAddr - - blr x4 - -_NeverReturn: - b _NeverReturn diff --git a/test_pool/exerciser/operating_system/test_e001.c b/test_pool/exerciser/operating_system/test_e001.c index d160ac73..04c93a76 100644 --- a/test_pool/exerciser/operating_system/test_e001.c +++ b/test_pool/exerciser/operating_system/test_e001.c @@ -39,7 +39,7 @@ payload(void) exerciser_data_t e_data; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS); while (instance-- != 0) { diff --git a/test_pool/exerciser/operating_system/test_e002.c b/test_pool/exerciser/operating_system/test_e002.c index 13dcdf5d..139df44b 100644 --- a/test_pool/exerciser/operating_system/test_e002.c +++ b/test_pool/exerciser/operating_system/test_e002.c @@ -94,7 +94,7 @@ payload(void) mem_desc = &mem_desc_array[0]; dram_buf_in_phys = 0; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS); /* Allocate an array to store base addresses of page tables allocated for * all exercisers diff --git a/test_pool/exerciser/operating_system/test_e003.c b/test_pool/exerciser/operating_system/test_e003.c index feb18a5c..941dd2a5 100644 --- a/test_pool/exerciser/operating_system/test_e003.c +++ b/test_pool/exerciser/operating_system/test_e003.c @@ -100,7 +100,7 @@ payload(void) dram_buf_in_phys = 0; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS); num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); /* Allocate an array to store base addresses of page tables allocated for diff --git a/test_pool/exerciser/operating_system/test_e004.c b/test_pool/exerciser/operating_system/test_e004.c index 01b77c6c..54424a9e 100644 --- a/test_pool/exerciser/operating_system/test_e004.c +++ b/test_pool/exerciser/operating_system/test_e004.c @@ -279,7 +279,7 @@ cfgspace_transactions_order_check(void) uint64_t bdf_addr; /* Read the number of excerciser cards */ - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS); while (instance-- != 0) { @@ -335,7 +335,7 @@ barspace_transactions_order_check(void) uint32_t status; /* Read the number of excerciser cards */ - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS); while (instance-- != 0) { diff --git a/test_pool/exerciser/operating_system/test_e005.c b/test_pool/exerciser/operating_system/test_e005.c index 0190b022..e0eb8a12 100644 --- a/test_pool/exerciser/operating_system/test_e005.c +++ b/test_pool/exerciser/operating_system/test_e005.c @@ -152,7 +152,7 @@ barspace_transactions_order_check(void) uint32_t status; /* Read the number of excerciser cards */ - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS); while (instance-- != 0) { diff --git a/test_pool/exerciser/operating_system/test_e006.c b/test_pool/exerciser/operating_system/test_e006.c index 09789289..1c92674c 100644 --- a/test_pool/exerciser/operating_system/test_e006.c +++ b/test_pool/exerciser/operating_system/test_e006.c @@ -288,7 +288,7 @@ payload(void) uint32_t dpc_cap_base = 0; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS); while (instance-- != 0) { diff --git a/test_pool/exerciser/operating_system/test_e007.c b/test_pool/exerciser/operating_system/test_e007.c index 9a00363b..bce86372 100644 --- a/test_pool/exerciser/operating_system/test_e007.c +++ b/test_pool/exerciser/operating_system/test_e007.c @@ -123,7 +123,7 @@ save_config_space(uint32_t rp_bdf) performed, all the devices connected below the RP is reset. This needs to be restored after SBR*/ cfg_space_buf[tbl_index] = val_aligned_alloc(MEM_ALIGN_4K, PCIE_CFG_SIZE); - if (cfg_space_buf == NULL) + if (cfg_space_buf[tbl_index] == NULL) { val_print(AVS_PRINT_ERR, "\n Memory allocation failed.", 0); val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); @@ -169,7 +169,7 @@ payload(void) fail_cnt = 0; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS); while (instance-- != 0) { diff --git a/test_pool/exerciser/operating_system/test_e008.c b/test_pool/exerciser/operating_system/test_e008.c index 05a17b4c..e41552b6 100644 --- a/test_pool/exerciser/operating_system/test_e008.c +++ b/test_pool/exerciser/operating_system/test_e008.c @@ -44,7 +44,7 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, uint32_t erp_ecam_index; uint32_t status; - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS); while (instance-- != 0) { @@ -172,7 +172,7 @@ payload(void) fail_cnt = 0; test_skip = 1; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - req_instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + req_instance = val_exerciser_get_info(EXERCISER_NUM_CARDS); status = val_pcie_p2p_support(); /* Check If PCIe Hierarchy supports P2P. */ diff --git a/test_pool/mpam/operating_system/test_mpam002.c b/test_pool/mpam/operating_system/test_mpam002.c index 159959e7..952a059f 100644 --- a/test_pool/mpam/operating_system/test_mpam002.c +++ b/test_pool/mpam/operating_system/test_mpam002.c @@ -28,7 +28,7 @@ static void payload(void) { uint32_t llc_index; - uint32_t cache_identifier; + uint64_t cache_identifier; uint32_t msc_node_cnt; uint32_t rsrc_node_cnt; uint32_t msc_index, rsrc_index; diff --git a/test_pool/mpam/operating_system/test_mpam006.c b/test_pool/mpam/operating_system/test_mpam006.c index 981292d1..1c9128f6 100644 --- a/test_pool/mpam/operating_system/test_mpam006.c +++ b/test_pool/mpam/operating_system/test_mpam006.c @@ -37,7 +37,7 @@ static void payload(void) uint32_t msc_index; uint32_t rsrc_index; uint32_t llc_index; - uint32_t cache_identifier; + uint64_t cache_identifier; uint32_t cache_size; uint32_t max_pmg; uint32_t max_partid; diff --git a/test_pool/pcie/operating_system/test_p033.c b/test_pool/pcie/operating_system/test_p033.c index b17f780c..0678baaf 100644 --- a/test_pool/pcie/operating_system/test_p033.c +++ b/test_pool/pcie/operating_system/test_p033.c @@ -34,7 +34,7 @@ payload(void) uint32_t pe_index; uint32_t tbl_index; uint32_t reg_value; - uint32_t max_payload_value; + int32_t max_payload_value; uint32_t dp_type; uint32_t test_fails; uint32_t test_skip = 1; diff --git a/test_pool/smmu/operating_system/test_i012.c b/test_pool/smmu/operating_system/test_i012.c index eccb2d8a..082c0256 100644 --- a/test_pool/smmu/operating_system/test_i012.c +++ b/test_pool/smmu/operating_system/test_i012.c @@ -32,7 +32,7 @@ payload() { uint64_t data; - uint64_t data_pe_endian; + uint64_t data_pe_endian = 0; uint32_t num_smmu; uint32_t index; diff --git a/test_pool/test.cmake b/test_pool/test.cmake new file mode 100644 index 00000000..c63019cb --- /dev/null +++ b/test_pool/test.cmake @@ -0,0 +1,68 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + + # get testsuite directory list +set(TEST_DIR_PATH ${ROOT_DIR}/test) +if(SUITE STREQUAL "all") + # Get all the test pool components + _get_sub_dir_list(TEST_SUITE_LIST ${TEST_DIR_PATH}) +else() + set(TEST_SUITE_LIST ${SUITE}) +endif() + +set(TEST_INCLUDE ${CMAKE_CURRENT_BINARY_DIR}) +list(APPEND TEST_INCLUDE + ${ROOT_DIR}/ + ${ROOT_DIR}/val/include/ + ${ROOT_DIR}/val/src/ + ${ROOT_DIR}/platform/pal_baremetal/common/include/ + ${ROOT_DIR}/platform/pal_baremetal/common/src/ + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/include/ + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/src/ +) + +set(TEST_LIB ${EXE_NAME}_test_lib) + +# Compile all .c/.S files from test directory +file(GLOB TEST_SRC + "${ROOT_DIR}/test_pool/*/*/test*.c" +) + +# Create TEST library +add_library(${TEST_LIB} STATIC ${TEST_SRC}) + +#Create compile list files +list(APPEND COMPILE_LIST ${TEST_SRC}) +set(COMPILE_LIST ${COMPILE_LIST} PARENT_SCOPE) + +target_include_directories(${TEST_LIB} PRIVATE ${TEST_INCLUDE} + +) + +create_executable(${EXE_NAME} ${BUILD}/output/ "") +unset(TEST_SRC) + +# target_include_directories(${VAL_LIB} PRIVATE +# ${CMAKE_CURRENT_BINARY_DIR} +# ${ROOT_DIR}/val/ +# ) + + +# test source directory +set(TEST_SOURCE_DIR ${ROOT_DIR}/test_pool) +# Get all the test pool components +_get_sub_dir_list(SUITE_LIST ${TEST_SOURCE_DIR}) \ No newline at end of file diff --git a/test_pool/test_pool.mk b/test_pool/test_pool.mk deleted file mode 100644 index 1ab87443..00000000 --- a/test_pool/test_pool.mk +++ /dev/null @@ -1,92 +0,0 @@ -## @file - # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. - # SPDX-License-Identifier : Apache-2.0 - # - # Licensed under the Apache License, Version 2.0 (the "License"); - # you may not use this file except in compliance with the License. - # You may obtain a copy of the License at - # - # http://www.apache.org/licenses/LICENSE-2.0 - # - # Unless required by applicable law or agreed to in writing, software - # distributed under the License is distributed on an "AS IS" BASIS, - # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - # See the License for the specific language governing permissions and - # limitations under the License. - ## - -SBSA_ROOT:= $(SBSA_PATH) -SBSA_DIR := $(SBSA_ROOT)/test_pool -SBSA_TEST_DIR := $(SBSA_ROOT)/test_pool/exerciser -SBSA_TEST_DIR += $(SBSA_ROOT)/test_pool/pcie -SBSA_TEST_DIR += $(SBSA_ROOT)/test_pool/pe -SBSA_TEST_DIR += $(SBSA_ROOT)/test_pool/gic -SBSA_TEST_DIR += $(SBSA_ROOT)/test_pool/peripherals -SBSA_TEST_DIR += $(SBSA_ROOT)/test_pool/timer_wd -SBSA_TEST_DIR += $(SBSA_ROOT)/test_pool/io_virt -SBSA_TEST_DIR += $(SBSA_ROOT)/test_pool/power_wakeup - -CFLAGS += -I$(SBSA_ROOT)/val/include -CFLAGS += -I$(SBSA_ROOT)/ - -CC = $(GCC49_AARCH64_PREFIX)gcc -march=armv8.2-a -DTARGET_EMULATION -AR = $(GCC49_AARCH64_PREFIX)ar -CC_FLAGS = -g -O0 -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wextra -Wmissing-declarations -Wstrict-prototypes -Wno-error=conversion -Wno-error=sign-conversion -Wno-error=strict-overflow -Wno-type-limits - -DEPS = $(SBSA_ROOT)/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h - -OBJ_DIR := $(SBSA_ROOT)/build/obj -LIB_DIR := $(SBSA_ROOT)/build/lib -OUT_DIR = $(SBSA_ROOT)/build - -FILES := $(foreach files,$(SBSA_TEST_DIR),$(wildcard $(files)/*.c)) -FILE = `find $(FILES) -type f -exec sh -c 'echo {} $$(basename {})' \; | sort -u --stable -k2,2 | awk '{print $$1}'` -FILE_1 := $(shell echo $(FILE)) -XYZ := $(foreach a,$(FILE_1),$(info $(a))) -PAL_OBJS :=$(addprefix $(OBJ_DIR)/,$(addsuffix .o, $(basename $(notdir $(foreach dirz,$(FILE_1),$(dirz)))))) - -all: PAL_LIB - -create_dirs: - rm -rf ${OBJ_DIR} - rm -rf ${LIB_DIR} - rm -rf ${OUT_DIR} - @mkdir ${OUT_DIR} - @mkdir ${OBJ_DIR} - @mkdir ${LIB_DIR} - - -$(OBJ_DIR)/%.o: $(DEPS) - $(CC) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 -$(OBJ_DIR)/%.o: $(SBSA_DIR)/exerciser/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 -$(OBJ_DIR)/%.o: $(SBSA_DIR)/io_virt/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 -$(OBJ_DIR)/%.o: $(SBSA_DIR)/pe/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 -$(OBJ_DIR)/%.o: $(SBSA_DIR)/pcie/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 -$(OBJ_DIR)/%.o: $(SBSA_DIR)/gic/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 -$(OBJ_DIR)/%.o: $(SBSA_DIR)/peripherals/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 -$(OBJ_DIR)/%.o: $(SBSA_DIR)/timer_wd/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 -$(OBJ_DIR)/%.o: $(SBSA_DIR)/power_wakeup/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: %.S$(SBSA_DIR) - $(CC) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(LIB_DIR)/lib_testpool.a: $(PAL_OBJS) - $(AR) $(ARFLAGS) $@ $^ >> $(OUT_DIR)/link.log 2>&1 - -PAL_LIB: $(LIB_DIR)/lib_testpool.a - -clean: - rm -rf $(OBJ_DIR) - rm -rf $(LIB_DIR) - rm -rf ${OUT_DIR} - -.PHONY: all PAL_LIB - diff --git a/tools/cmake/acs_host/CMakeLists.txt b/tools/cmake/acs_host/CMakeLists.txt new file mode 100644 index 00000000..98e47d5e --- /dev/null +++ b/tools/cmake/acs_host/CMakeLists.txt @@ -0,0 +1,28 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +project(acs_host LANGUAGES C ASM) + +set(EXE_NAME "${PROJECT_NAME}") + +set(VAL_LIB ${EXE_NAME}_val_lib) +set(PAL_LIB ${EXE_NAME}_pal_lib) + + +include(${ROOT_DIR}/platform/pal_baremetal/pal.cmake) +include(${ROOT_DIR}/val/val_host.cmake) +include(${ROOT_DIR}/test_pool/test.cmake) \ No newline at end of file diff --git a/tools/cmake/acs_host/image.ld.S b/tools/cmake/acs_host/image.ld.S new file mode 100644 index 00000000..77a5ee42 --- /dev/null +++ b/tools/cmake/acs_host/image.ld.S @@ -0,0 +1,75 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include "SbsaAvs.h" + +IMAGE_BASE = PLATFORM_HOST_IMAGE_BASE; +OUTPUT_FORMAT(elf64-littleaarch64) +OUTPUT_ARCH(aarch64) +ENTRY(acs_host_entry) + +MEMORY { + RAM (rwx): ORIGIN = IMAGE_BASE, LENGTH = PLATFORM_HOST_IMAGE_SIZE +} + +SECTIONS +{ + . = IMAGE_BASE; + + ASSERT(. == ALIGN(PAGE_SIZE), + "TEXT_START address is not aligned to PAGE_SIZE.") + .text : { + __TEXT_START__ = .; + *AvsBootEntry.S.o(.text*) + *(.text*) + . = NEXT(PAGE_SIZE); + __TEXT_END__ = .; + } + + .rodata : { + . = ALIGN(PAGE_SIZE); + __RODATA_START__ = .; + *(.rodata*) + + . = NEXT(PAGE_SIZE); + __RODATA_END__ = .; + + } + + .data : { + . = ALIGN(PAGE_SIZE); + __DATA_START__ = .; + *(.data*) + + . = ALIGN(8); + __GOT_START__ = .; + *(.got) + __GOT_END__ = .; + + . = NEXT(PAGE_SIZE); + __DATA_END__ = .; + } + + .bss (NOLOAD) : { + . = ALIGN(PAGE_SIZE); + __BSS_START__ = .; + *(SORT_BY_ALIGNMENT(.bss*)) + *(COMMON) + . = NEXT(PAGE_SIZE); + __BSS_END__ = .; + } +} diff --git a/tools/cmake/toolchain/common.cmake b/tools/cmake/toolchain/common.cmake new file mode 100644 index 00000000..61463e7f --- /dev/null +++ b/tools/cmake/toolchain/common.cmake @@ -0,0 +1,58 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +#Stop built in CMakeDetermine.cmake scripts to run. +set (CMAKE_C_COMPILER_ID_RUN 1) +#Stop cmake run compiler tests. +set (CMAKE_C_COMPILER_FORCED true) + +set(CMAKE_STATIC_LIBRARY_PREFIX "") +set(CMAKE_STATIC_LIBRARY_SUFFIX ".a") +set(CMAKE_SHARED_LIBRARY_SUFFIX "") +set(CMAKE_EXECUTABLE_SUFFIX ".elf") + + +if(NOT DEFINED CROSS_COMPILE) + message(FATAL_ERROR "CROSS_COMPILE is undefined.") +else() + set(CMAKE_C_COMPILER "${CROSS_COMPILE}gcc") + set(CMAKE_C_COMPILER_ID "gnuarm" CACHE INTERNAL "CROSS_COMPILE ID" FORCE) + set(COMPILER_FILE "${ROOT_DIR}/tools/cmake/toolchain/gnuarm.cmake") +endif () + +# Overwrite COMPILER_FILE and CMAKE_C_COMPILER if CC is passed as command-line argument +if(DEFINED CC) + set(CMAKE_C_COMPILER ${CC}) + if (CC MATCHES "^.*armclang(\\.exe)?$") + set(CMAKE_C_COMPILER_ID "ARMCLANG" CACHE INTERNAL "C compiler ID" FORCE) + set(COMPILER_FILE "${ROOT_DIR}/tools/cmake/toolchain/armclang.cmake") + elseif (CC MATCHES "^.*clang(\\.exe)?$") + set(CMAKE_C_COMPILER_ID "CLANG" CACHE INTERNAL "C compiler ID" FORCE) + set(COMPILER_FILE "${ROOT_DIR}/tools/cmake/toolchain/clang.cmake") + else() + message(FATAL_ERROR "CC is unknown.") + endif() +endif() + +## Always use ld for linking +set(LINKER_FILE "${ROOT_DIR}/tools/cmake/toolchain/linker.cmake") + +set(CROSS_COMPILE ${CROSS_COMPILE} CACHE INTERNAL "CROSS_COMPILE is set to ${CROSS_COMPILE}" FORCE) +set(CMAKE_C_COMPILER ${CMAKE_C_COMPILER} CACHE INTERNAL "CMAKE_C_COMPILER is set to ${CMAKE_C_COMPILER}" FORCE) + +include(${COMPILER_FILE}) +include(${LINKER_FILE}) diff --git a/tools/cmake/toolchain/default.cmake b/tools/cmake/toolchain/default.cmake new file mode 100644 index 00000000..c35969db --- /dev/null +++ b/tools/cmake/toolchain/default.cmake @@ -0,0 +1,20 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +set(ARM_ARCH_MAJOR_DFLT 9) +set(ARM_ARCH_MINOR_DFLT 0) +set(TARGET_DFLT RDN2) diff --git a/tools/cmake/toolchain/gnuarm.cmake b/tools/cmake/toolchain/gnuarm.cmake new file mode 100644 index 00000000..29f376ec --- /dev/null +++ b/tools/cmake/toolchain/gnuarm.cmake @@ -0,0 +1,49 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +if(_TOOLCHAIN_CMAKE_LOADED) + return() +endif() +set(_TOOLCHAIN_CMAKE_LOADED TRUE) + +get_filename_component(_CMAKE_C_TOOLCHAIN_LOCATION "${CMAKE_C_COMPILER}" PATH) + +set(CMAKE_ASM_COMPILER "${CMAKE_C_COMPILER}" CACHE FILEPATH "The GNUARM asm" FORCE) +set(CMAKE_AR "${CROSS_COMPILE}ar" CACHE FILEPATH "The GNUARM archiver" FORCE) + +# Set the compiler's target architecture profile based on ARM_ARCH_MINOR option +if(${ARM_ARCH_MINOR} STREQUAL 0) + set(TARGET_SWITCH "-march=armv${ARM_ARCH_MAJOR}-a+profile+sve") +else() + set(TARGET_SWITCH "-march=armv${ARM_ARCH_MAJOR}.${ARM_ARCH_MINOR}-a+profile+sve") +endif() + +if(${ENABLE_PIE}) + set(COMPILE_PIE_SWITCH "-fpie") + add_definitions(-DENABLE_PIE) +else() + set(COMPILE_PIE_SWITCH "") +endif() + +set(C_COMPILE_DEBUG_OPTIONS "-g -Wa,-gdwarf-4") +set(ASM_COMPILE_DEBUG_OPTIONS "-g -Wa,--gdwarf-4") + +add_definitions(-DTARGET_EMULATION) +add_definitions(-DTARGET_BM_BOOT) + +set(CMAKE_C_FLAGS "${TARGET_SWITCH} ${COMPILE_PIE_SWITCH} ${C_COMPILE_DEBUG_OPTIONS} -ffunction-sections -fdata-sections -mstrict-align -O0 -ffreestanding -Wall -Werror -std=gnu99 -Wextra -Wstrict-overflow -DCMAKE_GNUARM_COMPILE -Wno-packed-bitfield-compat -Wno-missing-field-initializers -mcmodel=small") # -Wcast-align -Wmissing-prototypes -Wmissing-declarations +set(CMAKE_ASM_FLAGS "${TARGET_SWITCH} ${ASM_COMPILE_DEBUG_OPTIONS} -c -x assembler-with-cpp -Wall -Werror -ffunction-sections -fdata-sections -Wstrict-prototypes -Wextra -Wconversion -Wsign-conversion -Wcast-align -Wstrict-overflow -DCMAKE_GNUARM_COMPILE") diff --git a/tools/cmake/toolchain/linker.cmake b/tools/cmake/toolchain/linker.cmake new file mode 100644 index 00000000..3a0bdd79 --- /dev/null +++ b/tools/cmake/toolchain/linker.cmake @@ -0,0 +1,72 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +if(_LINKER_CMAKE_LOADED) + return() +endif() +set(_LINKER_CMAKE_LOADED TRUE) + +set(GNUARM_LINKER "${CROSS_COMPILE}ld" CACHE FILEPATH "The GNUARM linker" FORCE) +set(GNUARM_OBJCOPY "${CROSS_COMPILE}objcopy" CACHE FILEPATH "The GNUARM objcopy" FORCE) +set(GNUARM_OBJDUMP "${CROSS_COMPILE}objdump" CACHE FILEPATH "The GNUARM objdump" FORCE) + +if(${ENABLE_PIE}) + set(LINKER_PIE_SWITCH "-pie --no-dynamic-linker") +else() + set(LINKER_PIE_SWITCH "") +endif() + +set(LINKER_DEBUG_OPTIONS "-g") +set(GNUARM_LINKER_FLAGS "--fatal-warnings ${LINKER_PIE_SWITCH} ${LINKER_DEBUG_OPTIONS} -O1 --gc-sections --build-id=none") +set(GNUARM_OBJDUMP_FLAGS "-dSx") +set(GNUARM_OBJCOPY_FLAGS "-Obinary") + +function (create_executable EXE_NAME OUTPUT_DIR TEST) + set(SCATTER_INPUT_FILE "${ROOT_DIR}/tools/cmake/${EXE_NAME}/image.ld.S") + set(SCATTER_OUTPUT_FILE "${OUTPUT_DIR}/${EXE_NAME}_image.ld") + + # Preprocess the scatter file for image layout symbols + add_custom_command(OUTPUT CPP-LD--${EXE_NAME}${TEST} + COMMAND ${CROSS_COMPILE}gcc -E -P -I${ROOT_DIR}/platform/pal_baremetal/${TARGET}/include -I${ROOT_DIR}/baremetal_app/ -I${ROOT_DIR} ${SCATTER_INPUT_FILE} -o ${SCATTER_OUTPUT_FILE} -DCMAKE_BUILD={CMAKE_BUILD} + DEPENDS ${VAL_LIB} ${PAL_LIB} ${TEST_LIB}) + add_custom_target(CPP-LD-${EXE_NAME}${TEST} ALL DEPENDS CPP-LD--${EXE_NAME}${TEST}) + + # Link the objects + add_custom_command(OUTPUT ${EXE_NAME}${TEST}.elf + COMMAND ${GNUARM_LINKER} ${CMAKE_LINKER_FLAGS} -T ${SCATTER_OUTPUT_FILE} -o ${OUTPUT_DIR}/${EXE_NAME}.elf ${VAL_LIB}.a ${PAL_LIB}.a ${TEST_LIB}.a ${VAL_LIB}.a ${PAL_LIB}.a ${PAL_OBJ_LIST} -Map=${OUTPUT_DIR}/${EXE_NAME}.map + DEPENDS CPP-LD-${EXE_NAME}${TEST}) + add_custom_target(${EXE_NAME}${TEST}_elf ALL DEPENDS ${EXE_NAME}${TEST}.elf) + + # Create the dump info + add_custom_command(OUTPUT ${EXE_NAME}${TEST}.dump + COMMAND ${GNUARM_OBJDUMP} ${GNUARM_OBJDUMP_FLAGS} ${OUTPUT_DIR}/${EXE_NAME}.elf > ${OUTPUT_DIR}/${EXE_NAME}.dump + DEPENDS ${EXE_NAME}${TEST}_elf) + add_custom_target(${EXE_NAME}${TEST}_dump ALL DEPENDS ${EXE_NAME}${TEST}.dump) + + # Create the binary + add_custom_command(OUTPUT ${EXE_NAME}${TEST}.bin + COMMAND ${GNUARM_OBJCOPY} ${GNUARM_OBJCOPY_FLAGS} ${OUTPUT_DIR}/${EXE_NAME}.elf ${OUTPUT_DIR}/${EXE_NAME}.bin + DEPENDS ${EXE_NAME}${TEST}_dump) + add_custom_target(${EXE_NAME}${TEST}_bin ALL DEPENDS ${EXE_NAME}${TEST}.bin) + + # Create the image + add_custom_command(OUTPUT ${EXE_NAME}${TEST}.img + COMMAND ${GNUARM_OBJCOPY} ${GNUARM_OBJCOPY_FLAGS} ${OUTPUT_DIR}/${EXE_NAME}.elf ${OUTPUT_DIR}/${EXE_NAME}.img + DEPENDS ${EXE_NAME}${TEST}_dump) + add_custom_target(${EXE_NAME}${TEST}_img ALL DEPENDS ${EXE_NAME}${TEST}.img) + +endfunction() diff --git a/tools/cmake/toolchain/utils.cmake b/tools/cmake/toolchain/utils.cmake new file mode 100644 index 00000000..a5cb1569 --- /dev/null +++ b/tools/cmake/toolchain/utils.cmake @@ -0,0 +1,28 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +# Function to get all the folders inside given parent directory +function(_get_sub_dir_list result parent_dir) + file(GLOB parent_dir_items RELATIVE ${parent_dir} ${parent_dir}/*) + set(dir_list "") + foreach(item ${parent_dir_items}) + if(IS_DIRECTORY ${parent_dir}/${item} AND NOT(${item} STREQUAL "database") AND NOT(${item} STREQUAL "common")) + list(APPEND dir_list ${item}) + endif() + endforeach() + set(${result} ${dir_list} PARENT_SCOPE) +endfunction(_get_sub_dir_list) diff --git a/tools/scripts/compile_check.py b/tools/scripts/compile_check.py new file mode 100644 index 00000000..0dfab6a8 --- /dev/null +++ b/tools/scripts/compile_check.py @@ -0,0 +1,73 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +import sys +import os +from os import walk +import warnings + +IGNORE_FILE_TYPES = ['', '.inf', '.mk', '.md', '.cmake', 'json', '.dts', '.h'] + +def compile_check(COMPILED_FILE, ROOT_DIR, TARGET): + + VAL_PATH = os.path.join(ROOT_DIR,'val') + PLAT_COMMON = os.path.join(ROOT_DIR,'platform', 'pal_baremetal', "common") + PLAT_PATH = os.path.join(ROOT_DIR,'platform', 'pal_baremetal', TARGET) + TEST_PATH = os.path.join(ROOT_DIR,'test_pool') + + global_filelist = [] + + for val, val_dir, val_files in os.walk(VAL_PATH): + for file in val_files: + if (os.path.splitext(file)[1] in IGNORE_FILE_TYPES): + continue + else: + global_filelist.append(os.path.join(val,file)) + + for plat, plat_dir, plat_files in os.walk(PLAT_COMMON): + for file in plat_files: + if (os.path.splitext(file)[1] in IGNORE_FILE_TYPES): + continue + else: + global_filelist.append(os.path.join(plat,file)) + + for plat, plat_dir, plat_files in os.walk(PLAT_PATH): + for file in plat_files: + if (os.path.splitext(file)[1] in IGNORE_FILE_TYPES): + continue + else: + global_filelist.append(os.path.join(plat,file)) + + for test, test_dir, test_files in os.walk(TEST_PATH): + for file in test_files: + if (os.path.splitext(file)[1] in IGNORE_FILE_TYPES): + continue + else: + global_filelist.append(os.path.join(test,file)) + + not_compiled_files = [not_compiled for not_compiled in global_filelist + if not_compiled not in COMPILED_FILE] + for i in not_compiled_files: + print(i) + + +if __name__ == "__main__": + COMPILED_FILE = sys.argv[1] + ROOT_DIR = sys.argv[2] + TARGET = sys.argv[3] + + compile_check(COMPILED_FILE, ROOT_DIR, TARGET) diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index d518058d..99121857 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -23,6 +23,32 @@ #include #endif +#ifdef TARGET_BM_BOOT + +#include "platform_image_def.h" +#include "platform_override_fvp.h" + + #define IMAGE_BASE PLATFORM_NORMAL_WORLD_IMAGE_BASE + #define IMAGE_SIZE PLATFORM_NORMAL_WORLD_IMAGE_SIZE + + #define UART_BASE BASE_ADDRESS_ADDRESS + #define GICC_BASE PLATFORM_OVERRIDE_GICC_BASE + #define GICD_BASE PLATFORM_OVERRIDE_GICD_BASE + #define GICRD_BASE PLATFORM_OVERRIDE_GICRD_BASE + #define GICH_BASE PLATFORM_OVERRIDE_GICH_BASE + #define MEM_POOL_SIZE PLATFORM_MEMORY_POOL_SIZE + + #define PCIE_BAR64 PLATFORM_OVERRIDE_PCIE_BAR64_VAL + #define PCIE_BAR64_RP PLATFORM_OVERRIDE_RP_BAR64_VAL + #define PCIE_BAR32_NP PLATFORM_OVERRIDE_PCIE_BAR32NP_VAL + #define PCIE_BAR32_P PLATFORM_OVERRIDE_PCIE_BAR32P_VAL + #define PCIE_BAR32_RP PLATOFRM_OVERRIDE_RP_BAR32_VAL + + #define MMU_PGT_IAS PLATFORM_OVERRIDE_MMU_PGT_IAS + #define MMU_PGT_OAS PLATFORM_OVERRIDE_MMU_PGT_OAS + +#endif + #ifdef TARGET_LINUX typedef char char8_t; typedef long long int addr_t; @@ -35,6 +61,8 @@ #define PCIE_MAX_FUNC 8 #define MAX_SID 32 +#define MMU_PGT_IAS 48 +#define MMU_PGT_OAS 48 #elif TARGET_EMULATION #include @@ -173,6 +201,10 @@ typedef struct { void pal_pe_call_smc(ARM_SMC_ARGS *args, int32_t conduit); void pal_pe_execute_payload(ARM_SMC_ARGS *args); uint32_t pal_pe_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void *)); +#ifdef TARGET_BM_BOOT + uint32_t pal_get_pe_count(void); + uint64_t *pal_get_phy_mpidr_list_base(void); +#endif /* ********** PE INFO END **********/ @@ -447,6 +479,7 @@ typedef struct { }IOVIRT_BLOCK; #define IOVIRT_NEXT_BLOCK(b) (IOVIRT_BLOCK *)((uint8_t*)(&b->data_map[0]) + b->num_data_map * sizeof(NODE_DATA_MAP)) +#define ALIGN_MEMORY(b, bound) (IOVIRT_BLOCK *) (((uint64_t)b + bound - 1) & (~(bound - 1))) #define IOVIRT_CCA_MASK ~((uint32_t)0) typedef struct { @@ -671,6 +704,7 @@ uint64_t pal_memory_get_unpopulated_addr(uint64_t *addr, uint32_t instance); /* Common Definitions */ void pal_print(char8_t *string, uint64_t data); void pal_print_raw(uint64_t addr, char8_t *string, uint64_t data); +void pal_uart_print(int log, const char *fmt, ...); uint32_t pal_strncmp(char8_t *str1, char8_t *str2, uint32_t len); void *pal_memcpy(void *dest_buffer, void *src_buffer, uint32_t len); void *pal_mem_alloc(uint32_t size); @@ -704,8 +738,6 @@ void pal_mmio_write16(uint64_t addr, uint16_t data); void pal_mmio_write(uint64_t addr, uint32_t data); void pal_mmio_write64(uint64_t addr, uint64_t data); -void pal_mem_set(void *Buf, uint32_t Size, uint8_t Value); - void pal_pe_update_elr(void *context, uint64_t offset); uint64_t pal_pe_get_esr(void *context); uint64_t pal_pe_get_far(void *context); diff --git a/val/include/sbsa_avs_exerciser.h b/val/include/sbsa_avs_exerciser.h index 7c0e3d0f..f91d50d8 100644 --- a/val/include/sbsa_avs_exerciser.h +++ b/val/include/sbsa_avs_exerciser.h @@ -109,7 +109,7 @@ typedef struct { void val_exerciser_create_info_table(void); uint32_t val_exerciser_init(uint32_t instance); -uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance); +uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type); uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance); uint32_t val_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, uint32_t instance); uint32_t val_exerciser_set_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance); diff --git a/val/include/sbsa_avs_mmu.h b/val/include/sbsa_avs_mmu.h index ae66d45c..b0a543db 100644 --- a/val/include/sbsa_avs_mmu.h +++ b/val/include/sbsa_avs_mmu.h @@ -24,6 +24,64 @@ #define MEM_ATTR_SH_SHIFT 8 #define MEM_ATTR_AF_SHIFT 10 +#define MAX_MMAP_REGION_COUNT 15 +#define TCR_TG0 0 + +#define PGT_IPS 0x2ull + +#define ATTR_NORMAL_NONCACHEABLE (0x0ull << 2) +#define ATTR_NORMAL_WB_WA_RA (0x1ull << 2) +#define ATTR_DEVICE (0x2ull << 2) +#define ATTR_NORMAL_WB (0x1ull << 3) + +/* Stage 1 Inner and Outer Cacheability attribute encoding without TEX remap */ +#define ATTR_S1_NONCACHEABLE (0x0ull << 2) +#define ATTR_S1_WB_WA_RA (0x1ull << 2) +#define ATTR_S1_WT_RA (0x2ull << 2) +#define ATTR_S1_WB_RA (0x3ull << 2) + +/* Stage 2 MemAttr[1:0] encoding for Normal memory */ +#define ATTR_S2_INNER_NONCACHEABLE (0x1ull << 2) +#define ATTR_S2_INNER_WT_CACHEABLE (0x2ull << 2) +#define ATTR_S2_INNER_WB_CACHEABLE (0x3ull << 2) + +#define ATTR_NS (0x1ull << 5) +#define ATTR_S (0x0ull << 5) + +#define ATTR_STAGE1_AP_RW (0x1ull << 6) +#define ATTR_STAGE2_AP_RW (0x3ull << 6) +#define ATTR_STAGE2_MASK (0x3ull << 6 | 0x1ull << 4) +#define ATTR_STAGE2_MASK_RO (0x1ull << 6 | 0x1ull << 4) + +#define ATTR_NON_SHARED (0x0ull << 8) +#define ATTR_OUTER_SHARED (0x2ull << 8) +#define ATTR_INNER_SHARED (0x3ull << 8) + +#define ATTR_AF (0x1ull << 10) +#define ATTR_nG (0x1ull << 11) + +#define ATTR_UXN (0x1ull << 54) +#define ATTR_PXN (0x1ull << 53) + +#define ATTR_PRIV_RW (0x0ull << 6) +#define ATTR_PRIV_RO (0x2ull << 6) +#define ATTR_USER_RW (0x1ull << 6) +#define ATTR_USER_RO (0x3ull << 6) + +#define ATTR_CODE (ATTR_S1_WB_WA_RA | ATTR_USER_RO | \ + ATTR_AF | ATTR_INNER_SHARED) +#define ATTR_RO_DATA (ATTR_S1_WB_WA_RA | ATTR_USER_RO | \ + ATTR_UXN | ATTR_PXN | ATTR_AF | \ + ATTR_INNER_SHARED) +#define ATTR_RW_DATA (ATTR_S1_WB_WA_RA | \ + ATTR_USER_RW | ATTR_UXN | ATTR_PXN | ATTR_AF \ + | ATTR_INNER_SHARED) +#define ATTR_DEVICE_RW (ATTR_DEVICE | ATTR_USER_RW | ATTR_UXN | \ + ATTR_PXN | ATTR_AF | ATTR_INNER_SHARED) + +#define ATTR_RW_DATA_NC (ATTR_S1_NONCACHEABLE | \ + ATTR_USER_RW | ATTR_UXN | ATTR_PXN | ATTR_AF \ + | ATTR_INNER_SHARED) /* memory type MAIR register index definitions*/ #define ATTR_DEVICE_nGnRnE (0x0ULL << MEM_ATTR_INDX_SHIFT) @@ -31,4 +89,31 @@ uint32_t val_mmu_check_for_entry(uint64_t base_addr); uint32_t val_mmu_add_entry(uint64_t base_addr, uint64_t size); uint32_t val_mmu_update_entry(uint64_t address, uint32_t size); +extern void val_mair_write(uint64_t value, uint64_t el_num); +extern void val_tcr_write(uint64_t value, uint64_t el_num); +extern void val_ttbr0_write(uint64_t value, uint64_t el_num); +extern void val_sctlr_write(uint64_t value, uint64_t el_num); +extern uint64_t val_sctlr_read(uint64_t el_num); +extern uint64_t val_read_current_el(void); +extern void EnableMMU(void); + +extern uint64_t tt_l0_base[]; +extern uint64_t tt_l1_base[]; +extern uint64_t tt_l2_base_1[]; +extern uint64_t tt_l2_base_2[]; +extern uint64_t tt_l2_base_3[]; +extern uint64_t tt_l2_base_4[]; +extern uint64_t tt_l2_base_5[]; +extern uint64_t tt_l2_base_6[]; +extern uint64_t tt_l3_base_1[]; +extern uint64_t tt_l3_base_2[]; +extern uint64_t tt_l3_base_3[]; +extern uint64_t tt_l3_base_4[]; +extern uint64_t tt_l3_base_5[]; +extern uint64_t tt_l3_base_6[]; +extern uint64_t tt_l3_base_7[]; +extern uint64_t tt_l3_base_8[]; +extern uint64_t tt_l3_base_9[]; +extern uint64_t tt_l3_base_10[]; + #endif /* __SBSA_AVS_MMU_H__ */ diff --git a/val/include/sbsa_avs_pe.h b/val/include/sbsa_avs_pe.h index 1be123d6..d7e535f8 100644 --- a/val/include/sbsa_avs_pe.h +++ b/val/include/sbsa_avs_pe.h @@ -75,6 +75,25 @@ #define SBSA_TCR_PS_SHIFT 16 #define SBSA_TCR_PS_MASK (0x7ull << SBSA_TCR_PS_SHIFT) +/* MPIDR macros */ +#define PAL_MPIDR_AFFLVL_MASK 0xffull +#define PAL_MPIDR_AFFINITY_BITS 8 +#define PAL_MPIDR_AFF0_SHIFT 0 +#define PAL_MPIDR_AFF1_SHIFT 8u +#define PAL_MPIDR_AFF2_SHIFT 16u +#define PAL_MPIDR_AFF3_SHIFT 32u +#define PAL_MPIDR_AFFLVL0 0x0ull +#define PAL_MPIDR_AFFLVL1 0x1ull +#define PAL_MPIDR_AFFLVL2 0x2ull +#define PAL_MPIDR_AFFLVL3 0x3ull + +#define PAL_MPIDR_AFFINITY_MASK ((PAL_MPIDR_AFFLVL_MASK << PAL_MPIDR_AFF3_SHIFT) | \ + (PAL_MPIDR_AFFLVL_MASK << PAL_MPIDR_AFF2_SHIFT) | \ + (PAL_MPIDR_AFFLVL_MASK << PAL_MPIDR_AFF1_SHIFT) | \ + (PAL_MPIDR_AFFLVL_MASK << PAL_MPIDR_AFF0_SHIFT)) + +#define PAL_INVALID_MPID 0xFFFFFFFFu + typedef enum { MPIDR_EL1 = 1, ID_AA64PFR0_EL1, diff --git a/val/include/sbsa_avs_smmu.h b/val/include/sbsa_avs_smmu.h index 7b0b9c4d..b69d4c78 100644 --- a/val/include/sbsa_avs_smmu.h +++ b/val/include/sbsa_avs_smmu.h @@ -44,7 +44,7 @@ uint32_t val_smmu_read_cfg(uint32_t offset, uint32_t index); uint64_t -val_smmu_ops(SMMU_OPS_e ops, uint32_t index, void *param1, void *param2); +val_smmu_ops(SMMU_OPS_e ops, void *param1, void *param2); uint32_t val_smmu_max_pasids(uint32_t smmu_index); diff --git a/val/include/val_interface.h b/val/include/val_interface.h index e68b2af6..e88305e0 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -54,6 +54,7 @@ #define SINGLE_TEST_SENTINEL 10000 #define SINGLE_MODULE_SENTINEL 10001 +typedef char char8_t; /* GENERIC VAL APIs */ void val_allocate_shared_mem(void); void val_free_shared_mem(void); @@ -385,6 +386,13 @@ typedef enum { /* MMU entries APIs*/ uint32_t val_mmu_update_entry(uint64_t address, uint32_t size); +/* Mem Map APIs */ +void val_mmu_add_mmap(void); +void val_mmap_add_region(uint64_t va_base, uint64_t pa_base, + uint64_t length, uint64_t attributes); +uint32_t val_setup_mmu(void); +uint32_t val_enable_mmu(void); + /* Identify memory type using MAIR attribute, refer to ARM ARM VMSA for details */ #define MEM_NORMAL_WB_IN_OUT(attr) (((attr & 0xcc) == 0xcc) || (((attr & 0x7) >= 5) && (((attr >> 4) & 0x7) >= 5))) @@ -427,6 +435,7 @@ void val_cache_free_info_table(void); uint64_t val_cache_get_info(CACHE_INFO_e type, uint32_t cache_index); uint32_t val_cache_get_llc_index(void); uint32_t val_cache_get_pe_l1_cache_res(uint32_t res_index); +uint64_t val_get_primary_mpidr(void); /* MPAM tests APIs */ #define MPAM_INVALID_INFO 0xFFFFFFFF diff --git a/val/src/AArch64/AvsBootEntry.S b/val/src/AArch64/AvsBootEntry.S new file mode 100644 index 00000000..3c1b4081 --- /dev/null +++ b/val/src/AArch64/AvsBootEntry.S @@ -0,0 +1,201 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include "SbsaAvs.h" + + .extern val_main + .extern vector_table + .extern val_fixup_symbol_table + .extern val_inv_dcache_range + .extern val_inv_icache_range + .extern g_primary_mpidr + + .cfi_sections .debug_frame + .globl acs_host_entry + .section .text.acs_host_entry, "ax" + +.macro dcache_line_size reg, tmp + mrs \tmp, ctr_el0 + ubfx \tmp, \tmp, #16, #4 + mov \reg, #4 + lsl \reg, \reg, \tmp +.endm + +.macro icache_line_size reg, tmp + mrs \tmp, ctr_el0 + and \tmp, \tmp, #0xf + mov \reg, #4 + lsl \reg, \reg, \tmp +.endm + +.macro do_icache_maintenance_by_mva op + /* Exit early if size is zero */ + cbz x1, exit_loop_\op + icache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +loop_\op: + ic \op, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo loop_\op + dsb sy +exit_loop_\op: + ret +.endm + +/* + * This macro can be used for implementing various data cache operations `op` + */ +.macro do_dcache_maintenance_by_mva op + /* Exit early if size is zero */ + cbz x1, exit_loop_\op + dcache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +loop_\op: + dc \op, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo loop_\op + dsb sy +exit_loop_\op: + ret +.endm + +acs_host_entry: + /* Install vector table */ + adr x0, vector_table + msr vbar_el2, x0 + + /* Set x19 = 1 for primary cpu + * Set x19 = 0 for secondary cpu + */ + adr x18, g_primary_mpidr + ldr x0, [x18] + mov x2, #INVALID_MPIDR + cmp x2, x0 + b.eq primary_cpu_entry + + mrs x2, mpidr_el1 + cmp x2, x0 + b.ne secondary_cpu_entry + + +primary_cpu_entry: + mov x19, #1 + + /* + * Invalidate the instr cache for the code region. + * This prevents re-use of stale data cache entries from + * prior bootloader stages. + */ + adr x0, __TEXT_START__ + adr x1, __TEXT_END__ + sub x1, x1, x0 + bl val_inv_icache_range + + /* + * Invalidate the data cache for the data regions. + * This prevents re-use of stale data cache entries from + * prior bootloader stages. + */ + adrp x0, __RODATA_START__ + add x0, x0, :lo12:__RODATA_START__ + adrp x1, __RODATA_END__ + add x1, x1, :lo12:__RODATA_END__ + sub x1, x1, x0 + bl val_inv_dcache_range + + + /* Enable I-Cache */ + mrs x0, sctlr_el2 + orr x0, x0, #SCTLR_I_BIT + msr sctlr_el2, x0 + isb + + /* Save the primary cpu mpidr */ + adr x18, g_primary_mpidr + mrs x0, mpidr_el1 + str x0, [x18] + + /* Clear BSS */ + adrp x0, __BSS_START__ + add x0,x0,:lo12:__BSS_START__ + adrp x1, __BSS_END__ + add x1,x1,:lo12:__BSS_END__ + sub x1, x1, x0 + //bl val_inv_dcache_range + +1: + stp xzr, xzr, [x0] + add x0, x0, #16 + sub x1, x1, #16 + cmp xzr, x1 + b.ne 1b + + b 0f + +secondary_cpu_entry: + mov x19, #0 + + /* Enable I-Cache */ + mrs x0, sctlr_el2 + orr x0, x0, #SCTLR_I_BIT + msr sctlr_el2, x0 + isb + +0: + /* Setup the dummy stack to call val_get_pe_id C fn */ + adrp x1, dummy_stack_end + add x1,x1,#:lo12:dummy_stack_end + mov sp, x1 + + mrs x0, mpidr_el1 + bl val_get_pe_id + + /* Now setup the stack pointer with actual stack addr + * for the logic PE id return by val_get_pe_id + */ + adrp x1, stacks_end + add x1,x1,#:lo12:stacks_end + mov x2, #STACK_SIZE + mul x2, x0, x2 + sub sp, x1, x2 + + /* And jump to the C entrypoint. */ + mov x0, x19 + b ShellAppMainsbsa + +val_inv_icache_range: + do_icache_maintenance_by_mva ivau + +val_inv_dcache_range: + do_dcache_maintenance_by_mva ivac + + +.section .bss.stacks + .global stacks_start + .global stacks_end + .balign CACHE_WRITEBACK_GRANULE +stacks_start: + .fill STACK_SIZE * PLATFORM_CPU_COUNT +stacks_end: + .fill STACK_SIZE +dummy_stack_end: diff --git a/val/src/AArch64/MmuSupport.S b/val/src/AArch64/MmuSupport.S new file mode 100644 index 00000000..3f90934d --- /dev/null +++ b/val/src/AArch64/MmuSupport.S @@ -0,0 +1,61 @@ +#/** @file +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. +# SPDX-License-Identifier : Apache-2.0 +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +#**/ + +// +// Private worker functions for ASM_PFX() +// +#define _CONCATENATE(a, b) __CONCATENATE(a, b) +#define __CONCATENATE(a, b) a ## b + +#define __USER_LABEL_PREFIX__ +// +// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix +// on symbols in assembly language. +// +#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) + +#define GCC_ASM_EXPORT(func__) \ + .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ + .type ASM_PFX(func__), %function + +#define GCC_ASM_IMPORT(func__) \ + .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) + +#include "SbsaAvs.h" + +GCC_ASM_EXPORT(EnableMMU) +GCC_ASM_EXPORT(DisableMMU) + +ASM_PFX(DisableMMU): + MRS X0, SCTLR_EL1 // Read System Control Register configuration data + AND X0, X0, #DISABLE_MMU_BIT // Set [M] bit and enable the MMU. + MSR SCTLR_EL1, X0 // Write System Control Register configuration data + ISB // The ISB forces these changes to be seen by the next instruction + + RET + +ASM_PFX(EnableMMU): + + // Enable MMU. + + MRS X0, SCTLR_EL1 // Read System Control Register configuration data + ORR X0, X0, #1 // Set [M] bit and enable the MMU. + MSR SCTLR_EL1, X0 // Write System Control Register configuration data + ISB // The ISB forces these changes to be seen by the next instruction + + RET \ No newline at end of file diff --git a/val/src/AArch64/MpamSupport.s b/val/src/AArch64/MpamSupport.s index cef982aa..463ff74b 100644 --- a/val/src/AArch64/MpamSupport.s +++ b/val/src/AArch64/MpamSupport.s @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,6 +16,26 @@ # #**/ +// +// Private worker functions for ASM_PFX() +// +#define _CONCATENATE(a, b) __CONCATENATE(a, b) +#define __CONCATENATE(a, b) a ## b + +#define __USER_LABEL_PREFIX__ +// +// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix +// on symbols in assembly language. +// +#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) + +#define GCC_ASM_EXPORT(func__) \ + .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ + .type ASM_PFX(func__), %function + +#define GCC_ASM_IMPORT(func__) \ + .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) + .text .align 2 @@ -51,4 +71,6 @@ ASM_PFX(AA64IssueDSB): dsb sy ret +#ifndef TARGET_EMULATION ASM_FUNCTION_REMOVE_IF_UNREFERENCED +#endif // TARGET_EMULATION diff --git a/val/src/AArch64/RasSupport.S b/val/src/AArch64/RasSupport.S index d144fa15..3253aa5f 100644 --- a/val/src/AArch64/RasSupport.S +++ b/val/src/AArch64/RasSupport.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2023 Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -16,6 +16,26 @@ # #**/ +// +// Private worker functions for ASM_PFX() +// +#define _CONCATENATE(a, b) __CONCATENATE(a, b) +#define __CONCATENATE(a, b) a ## b + +#define __USER_LABEL_PREFIX__ +// +// The __USER_LABEL_PREFIX__ macro predefined by GNUC represents the prefix +// on symbols in assembly language. +// +#define ASM_PFX(name) _CONCATENATE (__USER_LABEL_PREFIX__, name) + +#define GCC_ASM_EXPORT(func__) \ + .global _CONCATENATE (__USER_LABEL_PREFIX__, func__) ;\ + .type ASM_PFX(func__), %function + +#define GCC_ASM_IMPORT(func__) \ + .extern _CONCATENATE (__USER_LABEL_PREFIX__, func__) + .text .align 2 @@ -106,4 +126,6 @@ ASM_PFX(AA64WriteErrPfgcdn1): msr erxpfgcdn_el1, x0 ret +#ifndef TARGET_EMULATION ASM_FUNCTION_REMOVE_IF_UNREFERENCED +#endif // TARGET_EMULATION diff --git a/val/src/AArch64/SystemRegisters.S b/val/src/AArch64/SystemRegisters.S new file mode 100644 index 00000000..11df58fb --- /dev/null +++ b/val/src/AArch64/SystemRegisters.S @@ -0,0 +1,183 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + + .section .text.sysreg, "ax" + + .global val_mair_write +val_mair_write: + cmp x1, #2 + b.ne mair_el1_write + msr mair_el2, x0 + ret + +mair_el1_write: + msr mair_el1, x0 + ret + + .global val_tcr_write +val_tcr_write: + cmp x1, #2 + b.ne tcr_el1_write + msr tcr_el2, x0 + tlbi alle2 + dsb sy + isb + ret +tcr_el1_write: + msr tcr_el1, x0 + tlbi vmalle1 + dsb sy + isb + ret + + .global val_ttbr0_write +val_ttbr0_write: + cmp x1, #2 + b.ne ttbr0_el1_write + msr ttbr0_el2, x0 + ret + +ttbr0_el1_write: + msr ttbr0_el1, x0 + ret + + .global val_ttbr0_read +val_ttbr0_read: + cmp x0, #2 + b.ne ttbr0_el1_read + mrs x0, ttbr0_el2 + ret +ttbr0_el1_read: + mrs x0, ttbr0_el1 + ret + + .global val_sctlr_read +val_sctlr_read: + cmp x0, #2 + b.ne sctlr_el1_read + mrs x0, sctlr_el2 + isb + ret +sctlr_el1_read: + mrs x0, sctlr_el1 + isb + ret + + .global val_sctlr_write +val_sctlr_write: + cmp x1, #2 + b.ne sctlr_el1_write + msr sctlr_el2, x0 + isb + ret +sctlr_el1_write: + msr sctlr_el1, x0 + isb + ret + + .global val_read_current_el +val_read_current_el: + mrs x0, CurrentEL + ret + + .global val_dataCacheCleanInvalidateVA +val_dataCacheCleanInvalidateVA: + dc civac, x0 + dsb sy + isb + ret + + .global val_dataCacheCleanVA +val_dataCacheCleanVA: + dc cvac, x0 + dsb ish + isb + ret + + .global val_dataCacheInvalidateVA +val_dataCacheInvalidateVA: + dc ivac, x0 + dsb ish + isb + ret + +.macro dcache_line_size reg, tmp + mrs \tmp, ctr_el0 + ubfx \tmp, \tmp, #16, #4 + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + +.macro icache_line_size reg, tmp + mrs \tmp, ctr_el0 + and \tmp, \tmp, #0xf + mov \reg, #4 + lsl \reg, \reg, \tmp + .endm + +.macro do_dcache_maintenance_by_mva op + /* Exit early if size is zero */ + cbz x1, exit_loop_\op + dcache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +loop_\op: + dc \op, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo loop_\op + dsb sy +exit_loop_\op: + ret +.endm + +.macro do_icache_maintenance_by_mva op + /* Exit early if size is zero */ + cbz x1, exit_loop_\op + icache_line_size x2, x3 + add x1, x0, x1 + sub x3, x2, #1 + bic x0, x0, x3 +loop_\op: + ic \op, x0 + add x0, x0, x2 + cmp x0, x1 + b.lo loop_\op + dsb sy +exit_loop_\op: + ret +.endm + + /* ------------------------------------------ + * Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ + .global val_inv_dcache_range +val_inv_dcache_range: + do_dcache_maintenance_by_mva ivac + + /* ------------------------------------------ + * Invalidate from base address till + * size. 'x0' = addr, 'x1' = size + * ------------------------------------------ + */ + .global val_inv_icache_range +val_inv_icache_range: + do_icache_maintenance_by_mva ivau + diff --git a/val/src/AArch64/Vec_table.S b/val/src/AArch64/Vec_table.S new file mode 100644 index 00000000..2f79bcb7 --- /dev/null +++ b/val/src/AArch64/Vec_table.S @@ -0,0 +1,123 @@ +/** @file + * Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + + .section .bss.tt, "aw" + .align 12 + .global tt_l0_base +tt_l0_base: + .fill 4096 + + .align 12 + .global tt_l1_base +tt_l1_base: + .fill 4096 + + .align 12 + // Allocate space for 4 contiguous L2 tables + .global tt_l2_base_1 +tt_l2_base_1: + .fill 16384 + + .align 12 + // Allocate space for 4 contiguous L2 tables + .global tt_l2_base_2 +tt_l2_base_2: + .fill 16384 + + .align 12 + // Allocate space for 4 contiguous L2 tables + .global tt_l2_base_3 +tt_l2_base_3: + .fill 16384 + + .align 12 + // Allocate space for 4 contiguous L2 tables + .global tt_l2_base_4 +tt_l2_base_4: + .fill 16384 + + .align 12 + // Allocate space for 4 contiguous L2 tables + .global tt_l2_base_5 +tt_l2_base_5: + .fill 16384 + + .align 12 + // Allocate space for 4 contiguous L2 tables + .global tt_l2_base_6 +tt_l2_base_6: + .fill 16384 + + .align 12 + // Allocate space for 6 contiguous L3 tables + .global tt_l3_base_1 +tt_l3_base_1: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_2 +tt_l3_base_2: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_3 +tt_l3_base_3: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_4 +tt_l3_base_4: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_5 +tt_l3_base_5: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_6 +tt_l3_base_6: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_7 +tt_l3_base_7: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_8 +tt_l3_base_8: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_9 +tt_l3_base_9: + .fill 16384 + + .align 12 +// Allocate space for 6 contiguous L3 tables + .global tt_l3_base_10 +tt_l3_base_10: + .fill 16384 diff --git a/val/src/avs_exerciser.c b/val/src/avs_exerciser.c index 2093f968..70220cf6 100644 --- a/val/src/avs_exerciser.c +++ b/val/src/avs_exerciser.c @@ -138,8 +138,9 @@ uint32_t val_get_exerciser_err_info(EXERCISER_ERROR_CODE type) @param instance - Stimulus hadrware instance number @return value - Information value for input type **/ -uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance) +uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type) { + switch (type) { case EXERCISER_NUM_CARDS: return g_exerciser_info_table.num_exerciser; @@ -312,7 +313,7 @@ val_exerciser_execute_tests(uint32_t level) val_print(AVS_PRINT_INFO, "\n Starting Exerciser Setup\n", 0); val_exerciser_create_info_table(); - num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS); if (num_instances == 0) { val_print(AVS_PRINT_WARN, "\n No Exerciser Devices Found, Skipping Exerciser tests...\n", 0); diff --git a/val/src/avs_gic.c b/val/src/avs_gic.c index 7f063440..68fa4e64 100644 --- a/val/src/avs_gic.c +++ b/val/src/avs_gic.c @@ -37,6 +37,7 @@ val_gic_execute_tests(uint32_t level, uint32_t num_pe) uint32_t status, i; uint32_t module_skip; + status = 0; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_GIC_TEST_NUM_BASE) { diff --git a/val/src/avs_iovirt.c b/val/src/avs_iovirt.c index 6c0cbf81..c6c553e6 100644 --- a/val/src/avs_iovirt.c +++ b/val/src/avs_iovirt.c @@ -23,6 +23,13 @@ IOVIRT_INFO_TABLE *g_iovirt_info_table; uint32_t g_num_smmus; +#ifdef TARGET_BM_BOOT + // Align the memory access by 8 bytes in case of baremetal boot. + static uint64_t bound = 0x08; +#else + static uint64_t bound = 0x01; +#endif + /** @brief This API is a single point of entry to retrieve SMMU information stored in the IoVirt Info table @@ -51,6 +58,7 @@ val_iovirt_get_smmu_info(SMMU_INFO_e type, uint32_t index) block = &g_iovirt_info_table->blocks[0]; for(i = 0; i < g_iovirt_info_table->num_blocks; i++, block=IOVIRT_NEXT_BLOCK(block)) { + block = ALIGN_MEMORY(block, bound); if(block->type == IOVIRT_NODE_SMMU || block->type == IOVIRT_NODE_SMMU_V3) { if(j == index) @@ -108,6 +116,7 @@ val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index) block = &g_iovirt_info_table->blocks[0]; for(i = 0; i < g_iovirt_info_table->num_blocks; i++, block=IOVIRT_NEXT_BLOCK(block)) { + block = ALIGN_MEMORY(block, bound); if(block->type == IOVIRT_NODE_PCI_ROOT_COMPLEX) { if(j == index) @@ -157,6 +166,7 @@ val_iovirt_get_rc_index(uint32_t rc_seg_num) block = &g_iovirt_info_table->blocks[0]; for (i = 0; i < g_iovirt_info_table->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) { + block = ALIGN_MEMORY(block, bound); if (block->type == IOVIRT_NODE_PCI_ROOT_COMPLEX) { if (block->data.rc.segment == rc_seg_num) @@ -212,6 +222,7 @@ val_iovirt_get_named_comp_info(NAMED_COMP_INFO_e type, uint32_t index) block = &g_iovirt_info_table->blocks[0]; for (i = 0; i < g_iovirt_info_table->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) { + block = ALIGN_MEMORY(block, bound); if (block->type == IOVIRT_NODE_NAMED_COMPONENT) { if (j == index) @@ -268,6 +279,7 @@ val_iovirt_get_pmcg_info(PMCG_INFO_e type, uint32_t index) block = &g_iovirt_info_table->blocks[0]; for (i = 0; i < g_iovirt_info_table->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) { + block = ALIGN_MEMORY(block, bound); if (block->type == IOVIRT_NODE_PMCG) { if (j == index) @@ -343,6 +355,7 @@ val_iovirt_get_device_info(uint32_t rid, uint32_t segment, uint32_t *device_id, mapping_found = 0; for (i = 0; i < g_iovirt_info_table->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) { + block = ALIGN_MEMORY(block, bound); if (block->type == IOVIRT_NODE_PCI_ROOT_COMPLEX && block->data.rc.segment == segment) { diff --git a/val/src/avs_memory.c b/val/src/avs_memory.c index e336bb16..5f7552a3 100644 --- a/val/src/avs_memory.c +++ b/val/src/avs_memory.c @@ -18,10 +18,79 @@ #include "include/sbsa_avs_val.h" #include "include/sbsa_avs_peripherals.h" #include "include/sbsa_avs_common.h" +#include "include/sbsa_avs_mmu.h" +#include "include/val_interface.h" MEMORY_INFO_TABLE *g_memory_info_table; +#define SIZE_4KB 0x00001000 + +#ifdef TARGET_BM_BOOT + +/* Linker symbols used to figure out the memory layout of secure partition. */ +extern addr_t __TEXT_START__, __TEXT_END__; +#define TEXT_START ((addr_t)&__TEXT_START__) +#define TEXT_END ((addr_t)&__TEXT_END__) + +extern addr_t __RODATA_START__, __RODATA_END__; +#define RODATA_START ((addr_t)&__RODATA_START__) +#define RODATA_END ((addr_t)&__RODATA_END__) + +extern addr_t __DATA_START__, __DATA_END__; +#define DATA_START ((addr_t)&__DATA_START__) +#define DATA_END ((addr_t)&__DATA_END__) + +extern addr_t __BSS_START__, __BSS_END__; +#define BSS_START ((addr_t)&__BSS_START__) +#define BSS_END ((addr_t)&__BSS_END__) + +/** + * @brief Add regions assigned to host into its translation table data structure. + * @param void + * @return void +**/ +void val_mmu_add_mmap(void) +{ + /* Host Image region */ + val_mmap_add_region(TEXT_START, TEXT_START, + (TEXT_END - TEXT_START), + ATTR_CODE | ATTR_NS); + val_mmap_add_region(RODATA_START, RODATA_START, + (RODATA_END - RODATA_START), + ATTR_RO_DATA | ATTR_NS); + val_mmap_add_region(DATA_START, DATA_START, + (DATA_END - DATA_START), + ATTR_RW_DATA | ATTR_NS); + val_mmap_add_region(BSS_START, BSS_START, + (BSS_END - BSS_START), + ATTR_RW_DATA | ATTR_NS); + + /* Memory Pool region */ + val_mmap_add_region(IMAGE_BASE + IMAGE_SIZE, + IMAGE_BASE + IMAGE_SIZE, + MEM_POOL_SIZE, + ATTR_RW_DATA | ATTR_NS); + + /* Device region */ + val_mmap_add_region(UART_BASE, UART_BASE, 0x10000, ATTR_DEVICE_RW | ATTR_NS); + val_mmap_add_region(GICD_BASE, GICD_BASE, 0x10000, ATTR_DEVICE_RW | ATTR_NS); + val_mmap_add_region(GICC_BASE, GICC_BASE, 0x10000, ATTR_DEVICE_RW | ATTR_NS); + val_mmap_add_region(GICH_BASE, GICH_BASE, 0x10000, ATTR_DEVICE_RW | ATTR_NS); + val_mmap_add_region(GICRD_BASE, GICRD_BASE, 0x10000, ATTR_DEVICE_RW | ATTR_NS); + + /* PCIe BAR region */ + val_mmap_add_region(PCIE_BAR64, PCIE_BAR64, 0x100000, ATTR_RW_DATA | ATTR_NS); + val_mmap_add_region(PCIE_BAR64_RP, PCIE_BAR64_RP, 0x100000, ATTR_RW_DATA | ATTR_NS); + + val_mmap_add_region(PCIE_BAR32_P, PCIE_BAR32_P, 0x100000, ATTR_RW_DATA | ATTR_NS); + val_mmap_add_region(PCIE_BAR32_NP, PCIE_BAR32_NP, 0x100000, ATTR_RW_DATA | ATTR_NS); + val_mmap_add_region(PCIE_BAR32_RP, PCIE_BAR32_RP, 0x100000, ATTR_RW_DATA | ATTR_NS); + + +} +#endif // TARGET_BM_BOOT + #ifndef TARGET_LINUX /** @brief This API will execute all Memory tests designated for a given compliance level @@ -37,6 +106,7 @@ val_memory_execute_tests(uint32_t level, uint32_t num_pe) uint32_t status = 0; uint32_t i; + (void) level; for (i = 0 ; i < g_num_skip ; i++) { if (g_skip_test_num[i] == AVS_MEM_MAP_TEST_NUM_BASE) { diff --git a/val/src/avs_mmu.c b/val/src/avs_mmu.c index 7f4dc87c..03c05b9f 100644 --- a/val/src/avs_mmu.c +++ b/val/src/avs_mmu.c @@ -21,8 +21,11 @@ #include "include/sbsa_avs_pgt.h" #include "include/sbsa_avs_pe.h" #include "include/sbsa_avs_memory.h" +#include "include/val_interface.h" static uint32_t log2_func(uint64_t size); +static uint8_t mmap_list_curr_index; +memory_region_descriptor_t mmap_region_list[MAX_MMAP_REGION_COUNT]; /** @brief This API will check whether inputted base address is already @@ -225,7 +228,7 @@ uint32_t val_mmu_update_entry(uint64_t address, uint32_t size) **/ static uint32_t log2_func(uint64_t value) { - int bit = 0; + uint32_t bit = 0; while (value != 0) { @@ -236,3 +239,117 @@ static uint32_t log2_func(uint64_t value) } return 0; } + +/** + * @brief Populate mmap_region_list with given map info + * @param va_base - VA address + * @param pa_base - PA address + * @param length - Size of the region + * @param attributes - Map attributes + * @return Void +**/ +void val_mmap_add_region(uint64_t va_base, uint64_t pa_base, + uint64_t length, uint64_t attributes) +{ + mmap_region_list[mmap_list_curr_index].virtual_address = va_base; + mmap_region_list[mmap_list_curr_index].physical_address = pa_base; + mmap_region_list[mmap_list_curr_index].length = length; + mmap_region_list[mmap_list_curr_index].attributes = attributes; + mmap_list_curr_index++; +} + +#ifdef TARGET_BM_BOOT +/** + * @brief Setup page table for image regions and device regions + * @param void + * @return status +**/ +uint32_t val_setup_mmu(void) +{ + memory_region_descriptor_t mem_desc_array[2], *mem_desc; + pgt_descriptor_t pgt_desc; + uint8_t i = 0; + + // Memory map the image regions + val_mmu_add_mmap(); + + pgt_desc.ias = MMU_PGT_IAS; + pgt_desc.oas = MMU_PGT_OAS; + + pgt_desc.pgt_base = (uint64_t) tt_l0_base; + pgt_desc.stage = PGT_STAGE1; + + val_print(AVS_PRINT_DEBUG, " mmu: ias=%d\n", pgt_desc.ias); + val_print(AVS_PRINT_DEBUG, " mmu: oas=%d\n", pgt_desc.oas); + + /* Map regions */ + + val_memory_set(mem_desc_array, sizeof(mem_desc_array), 0); + mem_desc = &mem_desc_array[0]; + + while (i < mmap_list_curr_index) + { + mem_desc->virtual_address = mmap_region_list[i].virtual_address; + mem_desc->physical_address = mmap_region_list[i].physical_address; + mem_desc->length = mmap_region_list[i].length; + mem_desc->attributes = mmap_region_list[i].attributes; + + val_print(AVS_PRINT_DEBUG, "\n Creating page table for region : 0x%lx", + mem_desc->virtual_address); + val_print(AVS_PRINT_DEBUG, "- 0x%lx\n", (mem_desc->virtual_address + mem_desc->length) - 1); + + if (val_pgt_create(mem_desc, &pgt_desc)) + { + return AVS_STATUS_ERR; + } + i++; + } + + return AVS_STATUS_PASS; +} + +/** + * @brief Enable mmu through configuring mmu registers + * @param void + * @return status +**/ +uint32_t val_enable_mmu(void) +{ + uint64_t tcr; + uint32_t currentEL; + currentEL = (val_read_current_el() & 0xc) >> 2; + + /* + * Setup Memory Attribute Indirection Register + * Attr0 = b01000100 = Normal, Inner/Outer Non-Cacheable + * Attr1 = b11111111 = Normal, Inner/Outer WB/WA/RA + * Attr2 = b00000000 = Device-nGnRnE + */ + val_mair_write(0xFF00, currentEL); + + /* Setup ttbr0 */ + val_ttbr0_write((uint64_t)tt_l0_base, currentEL); + + if (AA64ReadCurrentEL() == AARCH64_EL2) + { + tcr = ((1ull << 20) | /* TBI, top byte ignored. */ + (TCR_TG0 << 14) | /* TG0, granule size */ + (3ull << 12) | /* SH0, inner shareable. */ + (1ull << 10) | /* ORGN0, normal mem, WB RA WA Cacheable */ + (1ull << 8) | /* IRGN0, normal mem, WB RA WA Cacheable */ + (64 - MMU_PGT_IAS)); /* T0SZ, input address is 2^40 bytes. */ + } + + val_tcr_write(tcr, currentEL); + + val_print(AVS_PRINT_DEBUG, " val_setup_mmu: TG0=0x%x\n", TCR_TG0); + val_print(AVS_PRINT_DEBUG, " val_setup_mmu: tcr=0x%lx\n", tcr); + + // Enable the MMU + EnableMMU(); + + val_print(AVS_PRINT_DEBUG, " val_enable_mmu: successful\n", 0); + + return AVS_STATUS_PASS; +} +#endif // TARGET_BM_BOOT diff --git a/val/src/avs_mpam.c b/val/src/avs_mpam.c index 91de082f..dab87b4b 100644 --- a/val/src/avs_mpam.c +++ b/val/src/avs_mpam.c @@ -38,6 +38,7 @@ val_mpam_execute_tests(uint32_t level, uint32_t num_pe) uint32_t status = AVS_STATUS_FAIL, i; uint32_t skip_module; uint32_t msc_node_cnt; + (void) level; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_MPAM_TEST_NUM_BASE) { diff --git a/val/src/avs_nist.c b/val/src/avs_nist.c index c9ce9778..7d8ada05 100644 --- a/val/src/avs_nist.c +++ b/val/src/avs_nist.c @@ -31,6 +31,7 @@ uint32_t val_nist_execute_tests(uint32_t level, uint32_t num_pe) { uint32_t status, i; + (void) level; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_NIST_TEST_NUM_BASE) { diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c index 64efb7b5..4caef4d7 100644 --- a/val/src/avs_pcie.c +++ b/val/src/avs_pcie.c @@ -1242,6 +1242,8 @@ val_pcie_get_atomicop_requester_capable(uint32_t bdf) { /* TO DO */ //return pal_pcie_get_atomicop_requester_capable(bdf); + (void) bdf; + return 0; } diff --git a/val/src/avs_pe.c b/val/src/avs_pe.c index a1a8069f..3995f8ce 100644 --- a/val/src/avs_pe.c +++ b/val/src/avs_pe.c @@ -42,6 +42,7 @@ extern ARM_SMC_ARGS g_smc_args; uint32_t val_pe_execute_tests(uint32_t level, uint32_t num_pe) { + uint32_t status = AVS_STATUS_PASS, i; for (i = 0; i < g_num_skip; i++) { @@ -242,11 +243,13 @@ val_pe_reg_read(uint32_t reg_id) return AA64ReadMair1(); if (AA64ReadCurrentEL() == AARCH64_EL2) return AA64ReadMair2(); + break; case TCR_ELx: if (AA64ReadCurrentEL() == AARCH64_EL1) return AA64ReadTcr1(); if (AA64ReadCurrentEL() == AARCH64_EL2) return AA64ReadTcr2(); + break; case ID_AA64ZFR0_EL1: return AA64ReadZfr0(); default: diff --git a/val/src/avs_pe_infra.c b/val/src/avs_pe_infra.c index 96c09647..009f227a 100644 --- a/val/src/avs_pe_infra.c +++ b/val/src/avs_pe_infra.c @@ -21,8 +21,14 @@ #include "include/sbsa_std_smc.h" #include "sys_arch_src/gic/sbsa_exception.h" +#include "include/val_interface.h" +#include "include/pal_interface.h" + int32_t gPsciConduit; +/* Global variable to store mpidr of primary PE */ +uint64_t g_primary_mpidr = PAL_INVALID_MPID; + /** @brief Pointer to the memory location of the PE Information table **/ @@ -112,7 +118,6 @@ val_pe_get_num() return g_pe_info_table->header.num_of_pe; } - /** @brief This API reads MPIDR system regiser and return the Affinity bits 1. Caller - Test Suite, VAL @@ -373,6 +378,7 @@ val_pe_context_save(uint64_t sp, uint64_t elr) void val_pe_context_restore(uint64_t sp) { + (void) sp; sp = 0; *(uint64_t *)(g_stack_pointer+8) = g_ret_addr; } @@ -403,7 +409,7 @@ void val_pe_default_esr(uint64_t interrupt_type, void *context) { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(AVS_PRINT_WARN, "\n Unexpected exception occured", 0); + val_print(AVS_PRINT_WARN, "\n Unexpected exception occured of type %d", interrupt_type); #ifndef TARGET_LINUX if (pal_target_is_bm()) { @@ -587,3 +593,45 @@ val_cache_get_pe_l1_cache_res(uint32_t res_index) return DEFAULT_CACHE_IDX; } } + +#ifdef TARGET_BM_BOOT +/** + * @brief Returns mpidr of primary cpu set during boot. + * @param void + * @return primary mpidr +**/ +uint64_t val_get_primary_mpidr(void) +{ + return g_primary_mpidr; +} + +/** + * @brief Convert mpidr to logical cpu number + * @param mpidr - mpidr value + * @return Logical cpu number +**/ +// This API is only used for baremetal boot at which point PE info table is not yet created. +uint32_t val_get_pe_id(uint64_t mpidr) +{ + uint32_t pe_index = 0; + uint32_t total_pe_num = pal_get_pe_count(); + uint64_t *phy_mpidr_list = pal_get_phy_mpidr_list_base(); + + mpidr = mpidr & PAL_MPIDR_AFFINITY_MASK; + + for (pe_index = 0; pe_index < total_pe_num; pe_index++) + { + if (mpidr == phy_mpidr_list[pe_index]) + return pe_index; + } + + /* In case virtual mpidr returned for realm */ + for (pe_index = 0; pe_index < total_pe_num; pe_index++) + { + if (mpidr == pe_index) + return pe_index; + } + + return PAL_INVALID_MPID; +} +#endif //TARGET_BM_BOOT diff --git a/val/src/avs_peripherals.c b/val/src/avs_peripherals.c index ece5b5d5..9ee84291 100644 --- a/val/src/avs_peripherals.c +++ b/val/src/avs_peripherals.c @@ -38,6 +38,8 @@ val_peripheral_execute_tests(uint32_t level, uint32_t num_pe) uint32_t status = AVS_STATUS_SKIP, i; uint32_t skip_module; + (void) level; + (void) num_pe; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_PER_TEST_NUM_BASE) { @@ -54,7 +56,6 @@ val_peripheral_execute_tests(uint32_t level, uint32_t num_pe) } val_print_test_start("Peripheral"); - return status; } #endif diff --git a/val/src/avs_pgt.c b/val/src/avs_pgt.c index 9f3fc0cb..871895df 100644 --- a/val/src/avs_pgt.c +++ b/val/src/avs_pgt.c @@ -20,6 +20,7 @@ #include "include/sbsa_avs_pgt.h" #include "include/sbsa_avs_memory.h" +#include "include/sbsa_avs_mmu.h" #define get_min(a, b) ((a) < (b))?(a):(b) @@ -200,12 +201,6 @@ uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t * mem_desc->virtual_address &= ((0x1ull << pgt_desc->ias) - 1); } - if ((pgt_desc->tcr.tg_size_log2) != page_size_log2) - { - val_print(AVS_PRINT_ERR, "\n val_pgt_create: input page_size 0x%x not supported ", (0x1 << pgt_desc->tcr.tg_size_log2)); - return AVS_STATUS_ERR; - } - tt_desc.input_base = mem_desc->virtual_address & ((0x1ull << pgt_desc->ias) - 1); tt_desc.input_top = tt_desc.input_base + mem_desc->length - 1; tt_desc.output_base = mem_desc->physical_address & ((0x1ull << pgt_desc->oas) - 1); diff --git a/val/src/avs_pmu.c b/val/src/avs_pmu.c index dff8ba4b..0e4af0f7 100644 --- a/val/src/avs_pmu.c +++ b/val/src/avs_pmu.c @@ -37,6 +37,7 @@ val_pmu_execute_tests(uint32_t level, uint32_t num_pe) uint32_t status = AVS_STATUS_FAIL; uint32_t skip_module; uint32_t i, pmu_node_count; + (void) level; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_PMU_TEST_NUM_BASE) { diff --git a/val/src/avs_ras.c b/val/src/avs_ras.c index 37c0009d..f01fff5e 100644 --- a/val/src/avs_ras.c +++ b/val/src/avs_ras.c @@ -34,9 +34,11 @@ static RAS2_INFO_TABLE *g_ras2_info_table; uint32_t val_ras_execute_tests(uint32_t level, uint32_t num_pe) { + uint32_t status, i; uint32_t skip_module; uint64_t num_ras_nodes = 0; + (void) level; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_RAS_TEST_NUM_BASE) { @@ -417,7 +419,7 @@ uint64_t val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx) { uint64_t base, value = INVALID_RAS_REG_VAL; - uint32_t start_rec_index, offset; + uint32_t start_rec_index, offset = 0; uint64_t num_err_recs, err_rec_impl_bitmap; start_rec_index = g_ras_info_table->node[node_index].intf_info.start_rec_index; @@ -568,7 +570,7 @@ void val_ras_reg_write(uint32_t node_index, uint32_t reg, uint64_t write_data) { uint64_t base; - uint32_t rec_index, offset; + uint32_t rec_index, offset = 0; rec_index = g_ras_info_table->node[node_index].intf_info.start_rec_index; @@ -768,7 +770,7 @@ uint32_t val_ras_check_err_record(uint32_t node_index, uint32_t error_type) { uint32_t status = AVS_STATUS_PASS; uint64_t err_status; - uint32_t err_type_mask; + uint32_t err_type_mask = 0; /* Loop for Wait */ val_ras_wait_timeout(1); diff --git a/val/src/avs_smmu.c b/val/src/avs_smmu.c index 7413fad6..2280a246 100644 --- a/val/src/avs_smmu.c +++ b/val/src/avs_smmu.c @@ -176,7 +176,7 @@ val_smmu_check_device_iova(uint32_t ctrl_index, addr_t dma_addr) uint64_t -val_smmu_ops(SMMU_OPS_e ops, uint32_t smmu_index, void *param1, void *param2) +val_smmu_ops(SMMU_OPS_e ops, void *param1, void *param2) { switch(ops) diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c index 3fdd69b6..f4a6efc7 100644 --- a/val/src/avs_test_infra.c +++ b/val/src/avs_test_infra.c @@ -20,6 +20,7 @@ #include "include/sbsa_avs_common.h" uint32_t g_override_skip; +#include "include/val_interface.h" /** @brief This API calls PAL layer to print a formatted string @@ -36,10 +37,14 @@ uint32_t g_override_skip; void val_print(uint32_t level, char8_t *string, uint64_t data) { - +#ifndef TARGET_BM_BOOT if (level >= g_print_level) pal_print(string, data); - +#else + if (level >= g_print_level) { + pal_uart_print(level, string, data); + } +#endif } /** @@ -54,28 +59,28 @@ val_print(uint32_t level, char8_t *string, uint64_t data) void val_print_test_start(char8_t *string) { - pal_print("\n *** Starting ", 0); - pal_print(string, 0); - pal_print(" tests *** \n", 0); + val_print(AVS_PRINT_TEST, "\n *** Starting ", 0); + val_print(AVS_PRINT_TEST, string, 0); + val_print(AVS_PRINT_TEST, " tests *** \n", 0); } void val_print_test_end(uint32_t status, char8_t *string) { - pal_print("\n ", 0); + val_print(AVS_PRINT_TEST, "\n ", 0); if (status != AVS_STATUS_PASS) { - pal_print("One or more ", 0); - pal_print(string, 0); - pal_print(" tests failed or were skipped.", 0); + val_print(AVS_PRINT_TEST, "One or more ", 0); + val_print(AVS_PRINT_TEST, string, 0); + val_print(AVS_PRINT_TEST, " tests failed or were skipped.", 0); } else { - pal_print("All ", 0); - pal_print(string, 0); - pal_print(" tests passed.", 0); + val_print(AVS_PRINT_TEST, "All ", 0); + val_print(AVS_PRINT_TEST, string, 0); + val_print(AVS_PRINT_TEST, " tests passed.", 0); } - pal_print("\n", 0); + val_print(AVS_PRINT_TEST, "\n", 0); } @@ -533,6 +538,7 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid) uint32_t status = 0; uint32_t error_flag = 0; uint32_t my_index = val_pe_get_index_mpid(val_pe_get_mpid()); + (void) test_num; /* this special case is needed when the Main PE is not the first entry of pe_info_table but num_pe is 1 for SOC tests */ diff --git a/val/src/avs_timer.c b/val/src/avs_timer.c index f7fd5faa..84bda436 100644 --- a/val/src/avs_timer.c +++ b/val/src/avs_timer.c @@ -37,6 +37,8 @@ val_timer_execute_tests(uint32_t level, uint32_t num_pe) { uint32_t status = AVS_STATUS_SKIP, i; uint32_t skip_module; + (void) level; + (void) num_pe; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_TIMER_TEST_NUM_BASE) { @@ -53,7 +55,6 @@ val_timer_execute_tests(uint32_t level, uint32_t num_pe) } val_print_test_start("Timer"); - return status; } @@ -92,22 +93,27 @@ val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance) val_platform_timer_get_entry_index (instance, &block_num, &block_index); if (block_num != 0xFFFF) return ((g_timer_info_table->gt_info[block_num].flags[block_index] >> 16) & 1); + break; case TIMER_INFO_SYS_CNTL_BASE: val_platform_timer_get_entry_index (instance, &block_num, &block_index); if (block_num != 0xFFFF) return g_timer_info_table->gt_info[block_num].block_cntl_base; + break; case TIMER_INFO_SYS_CNT_BASE_N: val_platform_timer_get_entry_index (instance, &block_num, &block_index); if (block_num != 0xFFFF) return g_timer_info_table->gt_info[block_num].GtCntBase[block_index]; + break; case TIMER_INFO_FRAME_NUM: val_platform_timer_get_entry_index (instance, &block_num, &block_index); if (block_num != 0xFFFF) return g_timer_info_table->gt_info[block_num].frame_num[block_index]; + break; case TIMER_INFO_SYS_INTID: val_platform_timer_get_entry_index (instance, &block_num, &block_index); if (block_num != 0xFFFF) return g_timer_info_table->gt_info[block_num].gsiv[block_index]; + break; case TIMER_INFO_PHY_EL1_FLAGS: return g_timer_info_table->header.ns_el1_timer_flag; case TIMER_INFO_VIR_EL1_FLAGS: @@ -119,6 +125,7 @@ val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance) default: return 0; } + return 0; } void diff --git a/val/src/avs_timer_support.c b/val/src/avs_timer_support.c index af253ee0..3290d542 100644 --- a/val/src/avs_timer_support.c +++ b/val/src/avs_timer_support.c @@ -71,12 +71,12 @@ ArmArchTimerReadReg ( case CnthCtl: case CnthpCval: - pal_print ("The register is related to Hypervisor Mode." - " Can't perform requested operation\n ", 0); + val_print (AVS_PRINT_TEST, "The register is related to Hypervisor Mode.", 0); + val_print(AVS_PRINT_TEST, " Can't perform requested operation\n ", 0); break; default: - pal_print ("Unknown ARM Generic Timer register %x. \n ", Reg); + val_print (AVS_PRINT_TEST, "Unknown ARM Generic Timer register %x. \n", Reg); } return 0xFFFFFFFF; @@ -92,7 +92,7 @@ ArmArchTimerWriteReg ( switch (Reg) { case CntPct: - pal_print("Can't write to Read Only Register: CNTPCT \n", 0); + val_print(AVS_PRINT_TEST, "Can't write to Read Only Register: CNTPCT \n", 0); break; case CntkCtl: @@ -116,7 +116,7 @@ ArmArchTimerWriteReg ( break; case CntvCt: - pal_print("Can't write to Read Only Register: CNTVCT \n", 0); + val_print(AVS_PRINT_TEST, "Can't write to Read Only Register: CNTVCT \n", 0); break; case CntpCval: @@ -145,11 +145,11 @@ ArmArchTimerWriteReg ( break; case CnthCtl: case CnthpCval: - pal_print("The register is related to Hypervisor Mode." - " Can't perform requested operation\n ", 0); + val_print(AVS_PRINT_TEST, "The register is related to Hypervisor Mode.", 0); + val_print(AVS_PRINT_TEST, " Can't perform requested operation\n ", 0); break; default: - pal_print("Unknown ARM Generic Timer register %x. \n ", Reg); + val_print(AVS_PRINT_TEST, "Unknown ARM Generic Timer register %x. \n", Reg); } } diff --git a/val/src/avs_wakeup.c b/val/src/avs_wakeup.c index 9e957c7d..7e4abe7e 100644 --- a/val/src/avs_wakeup.c +++ b/val/src/avs_wakeup.c @@ -35,9 +35,11 @@ extern int32_t gPsciConduit; uint32_t val_wakeup_execute_tests(uint32_t level, uint32_t num_pe) { + uint32_t status = AVS_STATUS_SKIP, i; uint32_t skip_module; - + (void) level; + (void) num_pe; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_WAKEUP_TEST_NUM_BASE) { diff --git a/val/src/avs_wd.c b/val/src/avs_wd.c index 497f135c..5f2d9565 100644 --- a/val/src/avs_wd.c +++ b/val/src/avs_wd.c @@ -35,6 +35,7 @@ uint32_t val_wd_execute_tests(uint32_t level, uint32_t num_pe) { uint32_t status = AVS_STATUS_PASS, i; + (void) level; for (i = 0; i < g_num_skip; i++) { if (g_skip_test_num[i] == AVS_WD_TEST_NUM_BASE) { diff --git a/val/sys_arch_src/gic/its/sbsa_gic_its.c b/val/sys_arch_src/gic/its/sbsa_gic_its.c index 00bc6d79..e3e6fa17 100644 --- a/val/sys_arch_src/gic/its/sbsa_gic_its.c +++ b/val/sys_arch_src/gic/its/sbsa_gic_its.c @@ -128,13 +128,13 @@ uint32_t ArmGicSetItsTables(uint32_t its_index) uint32_t DevBits, CIDBits; uint64_t Address; uint64_t ItsBase; - + uint64_t offset; ItsBase = g_gic_its_info->GicIts[its_index].Base; /* Allocate Memory for Table Depending on the Type of the table in GITS_BASER. */ for (it = 0; it < ARM_NUM_GITS_BASER; it++) { - - its_baser = val_mmio_read64(ItsBase + ARM_GITS_BASER(it)); + offset = (uint64_t) ARM_GITS_BASER(it); + its_baser = val_mmio_read64(ItsBase + offset); table_type = ARM_GITS_BASER_GET_TYPE(its_baser); entry_size = ARM_GITS_BASER_GET_ENTRY_SIZE(its_baser); @@ -162,13 +162,12 @@ uint32_t ArmGicSetItsTables(uint32_t its_index) } val_memory_set((void *)Address, PAGES_TO_SIZE(Pages), 0); - - write_value = val_mmio_read64(ItsBase + ARM_GITS_BASER(it)); + write_value = val_mmio_read64(ItsBase + offset); write_value = write_value & (~ARM_GITS_BASER_PA_MASK); write_value = write_value | (Address & ARM_GITS_BASER_PA_MASK); write_value = write_value | ARM_GITS_BASER_VALID; write_value = write_value | (Pages-1); - val_mmio_write64(ItsBase + ARM_GITS_BASER(it), write_value); + val_mmio_write64(ItsBase + offset, write_value); } @@ -220,7 +219,6 @@ void WriteCmdQMAPC( uint32_t its_index, uint64_t *CMDQ_BASE, - uint32_t device_id, uint32_t Clctn_ID, uint32_t RDBase, uint64_t Valid @@ -431,7 +429,7 @@ void val_its_create_lpi_map(uint32_t its_index, uint32_t device_id, g_gic_its_info->GicIts[its_index].ITTBase, g_gic_its_info->GicIts[its_index].IDBits, 0x1 /*Valid*/); /* Map Collection using MAPC */ - WriteCmdQMAPC(its_index, (uint64_t *)(ItsCommandBase), device_id, + WriteCmdQMAPC(its_index, (uint64_t *)(ItsCommandBase), 0x1 /*Clctn_ID*/, RDBase, 0x1 /*Valid*/); /* Map Interrupt using MAPI */ WriteCmdQMAPI(its_index, (uint64_t *)(ItsCommandBase), device_id, int_id, 0x1 /*Clctn_ID*/); @@ -539,8 +537,7 @@ uint32_t val_its_init(void) } /* Configure Redistributor For LPIs */ - Status = ArmGicRedistributorConfigurationForLPI(g_gic_its_info->GicDBase, - g_gic_its_info->GicRdBase); + Status = ArmGicRedistributorConfigurationForLPI(g_gic_its_info->GicRdBase); if (Status) return Status; diff --git a/val/sys_arch_src/gic/its/sbsa_gic_its.h b/val/sys_arch_src/gic/its/sbsa_gic_its.h index eeb8a5cb..d865751d 100644 --- a/val/sys_arch_src/gic/its/sbsa_gic_its.h +++ b/val/sys_arch_src/gic/its/sbsa_gic_its.h @@ -170,7 +170,7 @@ #define ITS_NEXT_CMD_PTR 4 #define NUM_BYTES_IN_DW 8 -uint32_t ArmGicRedistributorConfigurationForLPI(uint64_t gicd_base, uint64_t rd_base); +uint32_t ArmGicRedistributorConfigurationForLPI(uint64_t rd_base); void ClearConfigTable(uint32_t int_id); void SetConfigTable(uint32_t int_id, uint32_t Priority); diff --git a/val/sys_arch_src/gic/its/sbsa_gic_redistributor.c b/val/sys_arch_src/gic/its/sbsa_gic_redistributor.c index c34afacf..329fc056 100644 --- a/val/sys_arch_src/gic/its/sbsa_gic_redistributor.c +++ b/val/sys_arch_src/gic/its/sbsa_gic_redistributor.c @@ -22,7 +22,6 @@ static uint64_t ConfigBase; uint32_t ArmGicSetItsConfigTableBase( - uint64_t GicDistributorBase, uint64_t GicRedistributorBase ) { @@ -65,7 +64,6 @@ ArmGicSetItsConfigTableBase( uint32_t ArmGicSetItsPendingTableBase( - uint64_t GicDistributorBase, uint64_t GicRedistributorBase ) { @@ -78,7 +76,6 @@ ArmGicSetItsPendingTableBase( uint32_t gicr_propbaser_idbits; uint64_t Address; - /* Get Memory size by reading the GICD_TYPER.IDBits, GICR_PROPBASER.IDBits field */ gicr_propbaser_idbits = ARM_GICR_PROPBASER_IDbits( val_mmio_read64(GicRedistributorBase + ARM_GICR_PROPBASER)); @@ -133,20 +130,19 @@ void EnableLPIsRD(uint64_t GicRedistributorBase) uint32_t ArmGicRedistributorConfigurationForLPI( - uint64_t GicDistributorBase, uint64_t GicRedistributorBase ) { uint32_t Status; /* Set Configuration Table Base */ - Status = ArmGicSetItsConfigTableBase(GicDistributorBase, GicRedistributorBase); + Status = ArmGicSetItsConfigTableBase(GicRedistributorBase); if ((Status)) { return Status; } /* Set Pending Table Base For Each Redistributor */ - Status = ArmGicSetItsPendingTableBase(GicDistributorBase, GicRedistributorBase); + Status = ArmGicSetItsPendingTableBase(GicRedistributorBase); if ((Status)) { return Status; } diff --git a/val/sys_arch_src/gic/sbsa_exception.c b/val/sys_arch_src/gic/sbsa_exception.c index f4620fe3..0f8d718b 100644 --- a/val/sys_arch_src/gic/sbsa_exception.c +++ b/val/sys_arch_src/gic/sbsa_exception.c @@ -29,8 +29,11 @@ irq_handler g_intr_handler[NUM_ARM_MAX_INTERRUPT]; void default_irq_handler(uint64_t exception_type, void *context) { + uint32_t ack_interrupt; uint32_t iar_ack_val; + (void) exception_type; + (void) context; iar_ack_val = val_sbsa_gic_acknowledgeInterrupt(); ack_interrupt = iar_ack_val & 0xFFFFFF; diff --git a/val/sys_arch_src/smmu_v3/smmu_v3.c b/val/sys_arch_src/smmu_v3/smmu_v3.c index 2cc418a5..e2ddf390 100644 --- a/val/sys_arch_src/smmu_v3/smmu_v3.c +++ b/val/sys_arch_src/smmu_v3/smmu_v3.c @@ -466,7 +466,7 @@ smmu_master_t *smmu_master_at(uint32_t sid) } // Event handler. Gives the info of the kind of event error generated. -static int smmu_handle_evt(smmu_dev_t *smmu, uint64_t *event) +static int smmu_handle_evt(uint64_t *event) { switch (BITFIELD_GET(EVTQ_0_ID, event[0])) { case EVT_ID_UUT: @@ -610,9 +610,9 @@ void smmu_evtq_thread(void) do { while (!smmu_queue_remove_raw(evntq, event)) { uint8_t id = BITFIELD_GET(EVTQ_0_ID, event[0]); - ret = smmu_handle_evt(smmu, event); + ret = smmu_handle_evt(event); val_print(AVS_PRINT_TEST, "\n event 0x%02x received: %d ", id); - for (int i = 0; i < ARRAY_SIZE(event); ++i) + for (int i = 0; i < EVNTQ_DWORDS_PER_ENT; ++i) { val_print(AVS_PRINT_TEST, "\n 0x%016llx ", (unsigned long long)event[i]); } diff --git a/val/sys_arch_src/smmu_v3/smmu_v3.h b/val/sys_arch_src/smmu_v3/smmu_v3.h index dbd12236..a6db5fcc 100644 --- a/val/sys_arch_src/smmu_v3/smmu_v3.h +++ b/val/sys_arch_src/smmu_v3/smmu_v3.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2020, 2022-2023, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,7 +24,7 @@ #include "smmu_reg.h" #include "../include/sbsa_avs_pe.h" -static uint64_t inline get_max(uint64_t x, uint64_t y) +static inline uint64_t get_max(uint64_t x, uint64_t y) { return x > y ? x : y; } diff --git a/val/val.mk b/val/val.mk deleted file mode 100644 index f679d9a8..00000000 --- a/val/val.mk +++ /dev/null @@ -1,116 +0,0 @@ -## @file - # Copyright (c) 2022, Arm Limited or its affiliates. All rights reserved. - # SPDX-License-Identifier : Apache-2.0 - # - # Licensed under the Apache License, Version 2.0 (the "License"); - # you may not use this file except in compliance with the License. - # You may obtain a copy of the License at - # - # http://www.apache.org/licenses/LICENSE-2.0 - # - # Unless required by applicable law or agreed to in writing, software - # distributed under the License is distributed on an "AS IS" BASIS, - # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - # See the License for the specific language governing permissions and - # limitations under the License. - ## - -SBSA_ROOT:= $(SBSA_PATH) -SBSA_DIR := $(SBSA_ROOT)/val/src/ -SMMU_DIR := $(SBSA_ROOT)/val/sys_arch_src/smmu_v3 -GIC_V3_DIR := $(SBSA_ROOT)/val/sys_arch_src/gic/v3 -GIC_V2_DIR := $(SBSA_ROOT)/val/sys_arch_src/gic/v2 -GIC_DIR := $(SBSA_ROOT)/val/sys_arch_src/gic -GIC_ITS_DIR := $(SBSA_ROOT)/val/sys_arch_src/gic/its - -SBSA_A64_DIR := $(SBSA_ROOT)/val/src/AArch64/ -SBSA_GIC_DIR := $(SBSA_ROOT)/val/sys_arch_src/gic/AArch64/ -SBSA_GIC_V3_DIR := $(SBSA_ROOT)/val/sys_arch_src/gic/v3/AArch64/ - -CFLAGS += -I$(SBSA_ROOT)/val/include -CFLAGS += -I$(SBSA_ROOT)/val/ -CFLAGS += -I$(SBSA_ROOT)/val/sys_arch_src/smmu_v3 -CFLAGS += -I$(SBSA_ROOT)/val/sys_arch_src/gic/ -CFLAGS += -I$(SBSA_ROOT)/val/sys_arch_src/gic/its -CFLAGS += -I$(SBSA_ROOT)/val/sys_arch_src/gic/v3 -CFLAGS += -I$(SBSA_ROOT)/val/sys_arch_src/gic/v2 -ASFLAGS += -I$(SBSA_ROOT)/val/src/AArch64/ - -DEPS = $(SBSA_ROOT)/val/include/val_interface.h -DEPS += $(SBSA_ROOT)/platform/pal_baremetal/FVP/RDN2/include/platform_override_fvp.h - -OUT_DIR = $(SBSA_ROOT)/build/ -OBJ_DIR := $(SBSA_ROOT)/build/obj -LIB_DIR := $(SBSA_ROOT)/build/lib - -CC = $(GCC49_AARCH64_PREFIX)gcc -march=armv8.2-a -DTARGET_EMULATION -AR = $(GCC49_AARCH64_PREFIX)ar -CC_FLAGS = -g -Os -fshort-wchar -fno-builtin -fno-strict-aliasing -Wall -Werror -Wextra -Wmissing-declarations -Wstrict-prototypes -Wconversion -Wsign-conversion -Wstrict-overflow - -FILES := $(foreach files,$(SBSA_DIR),$(wildcard $(files)/*.c)) -FILES += $(foreach files,$(SMMU_DIR),$(wildcard $(files)/*.c)) -FILES += $(foreach files,$(GIC_V3_DIR),$(wildcard $(files)/*.c)) -FILES += $(foreach files,$(GIC_DIR),$(wildcard $(files)/*.c)) -FILES += $(foreach files,$(SBSA_A64_DIR),$(wildcard $(files)/*.S)) -FILES += $(foreach files,$(SBSA_GIC_DIR),$(wildcard $(files)/*.S)) -FILES += $(foreach files,$(SBSA_GIC_V3_DIR),$(wildcard $(files)/*.S)) -FILES += $(foreach files,$(GIC_ITS_DIR),$(wildcard $(files)/*.c)) -FILE = `find $(FILES) -type f -exec sh -c 'echo {} $$(basename {})' \; | sort -u --stable -k2,2 | awk '{print $$1}'` -FILE_1 := $(shell echo $(FILE)) -XYZ := $(foreach a,$(FILE_1),$(info $(a))) -PAL_OBJS :=$(addprefix $(OBJ_DIR)/,$(addsuffix .o, $(basename $(notdir $(foreach dirz,$(FILE_1),$(dirz)))))) - -all: PAL_LIB - -create_dirs: - rm -rf ${OBJ_DIR} - rm -rf ${LIB_DIR} - rm -rf ${OUT_DIR} - @mkdir ${OUT_DIR} - @mkdir ${OBJ_DIR} - @mkdir ${LIB_DIR} - -$(OBJ_DIR)/%.o: $(DEPS) - $(CC) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_A64_DIR)/%.S - $(CC) $(CFLAGS) $(ASFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_GIC_DIR)/%.S - $(CC) $(CFLAGS) $(ASFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_GIC_V3_DIR)/%.S - $(CC) $(CFLAGS) $(ASFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_DIR)/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SMMU_DIR)/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(GIC_V3_DIR)/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(GIC_V2_DIR)/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(GIC_DIR)/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(GIC_ITS_DIR)/%.c - $(CC) $(CC_FLAGS) $(CFLAGS) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(OBJ_DIR)/%.o: $(SBSA_DIR)/%.S - $(CC) -c -o $@ $< >> $(OUT_DIR)/compile.log 2>&1 - -$(LIB_DIR)/lib_val.a: $(PAL_OBJS) - $(AR) $(ARFLAGS) $@ $^ >> $(OUT_DIR)/link.log 2>&1 - -PAL_LIB: $(LIB_DIR)/lib_val.a - -clean: - rm -rf ${OBJ_DIR} - rm -rf ${LIB_DIR} - rm -rf ${OUT_DIR} - -.PHONY: all PAL_LIB diff --git a/val/val_host.cmake b/val/val_host.cmake new file mode 100644 index 00000000..fb5ff694 --- /dev/null +++ b/val/val_host.cmake @@ -0,0 +1,65 @@ +## @file + # Copyright (c) 2023, Arm Limited or its affiliates. All rights reserved. + # SPDX-License-Identifier : Apache-2.0 + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + ## + +file(GLOB VAL_SRC + "${ROOT_DIR}/val/src/AArch64/*.S" + "${ROOT_DIR}/val/src/AArch64/*.s" + "${ROOT_DIR}/val/src/AArch64/*.h" + "${ROOT_DIR}/val/include/*.h" + "${ROOT_DIR}/val/src/*.c" + "${ROOT_DIR}/val/sys_arch_src/smmu_v3/*.h" + "${ROOT_DIR}/val/sys_arch_src/smmu_v3/*.c" + "${ROOT_DIR}/val/sys_arch_src/gic/*.h" + "${ROOT_DIR}/val/sys_arch_src/gic/*.c" + "${ROOT_DIR}/val/sys_arch_src/gic/AArch64/*.S" + "${ROOT_DIR}/val/sys_arch_src/gic/its/*.h" + "${ROOT_DIR}/val/sys_arch_src/gic/its/*.c" + "${ROOT_DIR}/val/sys_arch_src/gic/v2/*.h" + "${ROOT_DIR}/val/sys_arch_src/gic/v2/*.c" + "${ROOT_DIR}/val/sys_arch_src/gic/v3/*.h" + "${ROOT_DIR}/val/sys_arch_src/gic/v3/*.c" + "${ROOT_DIR}/val/sys_arch_src/gic/v3/AArch64/*.S" + "${ROOT_DIR}/baremetal_app/*.h" + "${ROOT_DIR}/baremetal_app/*.c" + +) + +#Create compile list files +list(APPEND COMPILE_LIST ${VAL_SRC}) +set(COMPILE_LIST ${COMPILE_LIST} PARENT_SCOPE) + +# Create VAL library +add_library(${VAL_LIB} STATIC ${VAL_SRC}) + +target_include_directories(${VAL_LIB} PRIVATE + ${CMAKE_CURRENT_BINARY_DIR} + ${ROOT_DIR}/ + ${ROOT_DIR}/val/ + ${ROOT_DIR}/val/include/ + ${ROOT_DIR}/val/src/AArch64/ + ${ROOT_DIR}/val/sys_arch_src/smmu_v3/ + ${ROOT_DIR}/val/sys_arch_src/gic/ + ${ROOT_DIR}/val/sys_arch_src/gic/its/ + ${ROOT_DIR}/val/sys_arch_src/gic/v2/ + ${ROOT_DIR}/val/sys_arch_src/gic/v3/ + ${ROOT_DIR}/platform/pal_baremetal/common/include/ + ${ROOT_DIR}/platform/pal_baremetal/${TARGET}/include/ + ${ROOT_DIR}/platform/pal_baremetal/common/src/AArch64/ + ${ROOT_DIR}/baremetal_app/ +) + +unset(VAL_SRC)