From f12dc36a11748ab366a7d080e7c7b9e45434e08a Mon Sep 17 00:00:00 2001 From: anumis01 Date: Wed, 10 May 2017 16:35:09 +0530 Subject: [PATCH 1/4] Added image cache flush and minor bug fixes --- platform/pal_uefi/src/pal_pe.c | 8 ++-- platform/pal_uefi/src/pal_peripherals.c | 8 ++-- platform/pal_uefi/src/pal_timer_wd.c | 8 ++-- test_pool/pe/test_c001.c | 55 +++++++++++++++++-------- test_pool/pe/test_c015.c | 38 ++++++++--------- uefi_app/SbsaAvs.inf | 1 + uefi_app/SbsaAvsMain.c | 17 ++++++++ val/include/sbsa_avs_pe.h | 2 + val/src/avs_gic_support.c | 4 +- val/src/avs_memory.c | 4 +- val/src/avs_pe.c | 4 +- val/src/avs_pe_infra.c | 20 ++++++++- val/src/avs_test_infra.c | 12 +++--- 13 files changed, 120 insertions(+), 61 deletions(-) diff --git a/platform/pal_uefi/src/pal_pe.c b/platform/pal_uefi/src/pal_pe.c index fe637be1..eed06802 100644 --- a/platform/pal_uefi/src/pal_pe.c +++ b/platform/pal_uefi/src/pal_pe.c @@ -74,18 +74,19 @@ PalGetMaxMpidr() VOID PalAllocateSecondaryStack(UINT64 mpidr) { - EFI_STATUS Status, NumPe, Aff0, Aff1, Aff2, Aff3; + EFI_STATUS Status; + UINT32 MaxPe, Aff0, Aff1, Aff2, Aff3; Aff0 = ((mpidr & 0x00000000ff) >> 0); Aff1 = ((mpidr & 0x000000ff00) >> 8); Aff2 = ((mpidr & 0x0000ff0000) >> 16); Aff3 = ((mpidr & 0xff00000000) >> 32); - NumPe = ((Aff3+1) * (Aff2+1) * (Aff1+1) * (Aff0+1)); + MaxPe = ((Aff3+1) * (Aff2+1) * (Aff1+1) * (Aff0+1)); if (gSecondaryPeStack == NULL) { Status = gBS->AllocatePool ( EfiBootServicesData, - (NumPe * SIZE_STACK_SECONDARY_PE), + (MaxPe * SIZE_STACK_SECONDARY_PE), (VOID **) &gSecondaryPeStack); if (EFI_ERROR(Status)) { Print(L"\n FATAL - Allocation for Seconday stack failed %x \n", Status); @@ -153,6 +154,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable) gMpidrMax = MpidrAff0Max | MpidrAff1Max | MpidrAff2Max | MpidrAff3Max; pal_pe_data_cache_ops_by_va((UINT64)PeTable, CLEAN_AND_INVALIDATE); + pal_pe_data_cache_ops_by_va((UINT64)&gMpidrMax, CLEAN_AND_INVALIDATE); PalAllocateSecondaryStack(gMpidrMax); } diff --git a/platform/pal_uefi/src/pal_peripherals.c b/platform/pal_uefi/src/pal_peripherals.c index db5f92ab..29512243 100644 --- a/platform/pal_uefi/src/pal_peripherals.c +++ b/platform/pal_uefi/src/pal_peripherals.c @@ -65,14 +65,14 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable) per_info++; } StartBdf = incrementBusDev(DeviceBdf); - + } while (DeviceBdf != 0); StartBdf = 0; /* check for any SATA Controllers */ do { - + DeviceBdf = palPcieGetBdf(SATA_CLASSCODE, StartBdf); if (DeviceBdf != 0) { per_info->type = PERIPHERAL_TYPE_SATA; @@ -105,7 +105,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable) per_info->type = PERIPHERAL_TYPE_UART; per_info++; } - + per_info->type = 0xFF; //indicate end of table } @@ -237,7 +237,7 @@ pal_memory_ioremap(VOID *ptr, UINT32 size, UINT32 attr) VOID -pal_memory_unmap(void *ptr) +pal_memory_unmap(VOID *ptr) { return; diff --git a/platform/pal_uefi/src/pal_timer_wd.c b/platform/pal_uefi/src/pal_timer_wd.c index 52a4a33a..44a76dc7 100644 --- a/platform/pal_uefi/src/pal_timer_wd.c +++ b/platform/pal_uefi/src/pal_timer_wd.c @@ -33,7 +33,7 @@ pal_get_gtdt_ptr(); /* Information about only one timer can be mentioned as an Override */ static -void +VOID pal_timer_platform_override(TIMER_INFO_TABLE *TimerTable) { if (PLATFORM_OVERRIDE_PLATFORM_TIMER) { @@ -63,7 +63,7 @@ pal_timer_platform_override(TIMER_INFO_TABLE *TimerTable) @return None **/ -void +VOID pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable) { EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE *Entry; @@ -146,7 +146,7 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable) /* Only one watchdog information can be assigned as an override */ -void +VOID pal_wd_platform_override(WD_INFO_TABLE *WdTable) { @@ -171,7 +171,7 @@ pal_wd_platform_override(WD_INFO_TABLE *WdTable) @return None **/ -void +VOID pal_wd_create_info_table(WD_INFO_TABLE *WdTable) { diff --git a/test_pool/pe/test_c001.c b/test_pool/pe/test_c001.c index c2f915da..52890ab8 100755 --- a/test_pool/pe/test_c001.c +++ b/test_pool/pe/test_c001.c @@ -21,37 +21,56 @@ #define TEST_NUM AVS_PE_TEST_NUM_BASE + 1 #define TEST_DESC "Check for number of PE " -uint32_t -c001_entry() +static +void +payload() { - uint32_t num_pe = 0; + uint64_t num_of_pe = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - val_print(AVS_PRINT_ERR, "%4d : ", TEST_NUM); - val_print(AVS_PRINT_TEST, TEST_DESC, 0); - val_report_status(0, SBSA_AVS_START(g_sbsa_level, TEST_NUM)); - - num_pe = val_pe_get_num(); + num_of_pe = val_pe_get_num(); // //g_sbsa_level is set based on runtime input to the tool // if (g_sbsa_level < 2) { - if (num_pe > MAX_NUM_PE_LEVEL0) { - val_report_status(0, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_pe); - return AVS_STATUS_FAIL; + if (num_of_pe > MAX_NUM_PE_LEVEL0) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_of_pe); + return; } } else { - if (num_pe > MAX_NUM_PE_LEVEL2) { - val_report_status(0, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_pe); - return AVS_STATUS_FAIL; + if (num_of_pe > MAX_NUM_PE_LEVEL2) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_of_pe); + return; } } - val_report_status(0, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +c001_entry() +{ + + uint32_t status = AVS_STATUS_FAIL; //default value + uint32_t num_pe = 1; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); - return AVS_STATUS_PASS; + return status; } diff --git a/test_pool/pe/test_c015.c b/test_pool/pe/test_c015.c index 84c417bf..3fff3c24 100755 --- a/test_pool/pe/test_c015.c +++ b/test_pool/pe/test_c015.c @@ -25,7 +25,7 @@ #define RAS 1 #define SPE 2 #define LOR 3 -#define AA64 4 +#define AA32 4 #define MASK_AA64MMFR0 0xF #define MASK_MIDR 0x00F0FFFF @@ -61,23 +61,23 @@ reg_details reg_list[] = { {MIDR_EL1, MASK_MIDR, "MIDR_EL1" , 0x0 }, {VPIDR_EL2, MASK_VPIDR, "VPIDR_EL2" , 0x0 }, {CCSIDR_EL1, MASK_CCSIDR, "CCSIDR_EL1" , 0x0 }, - {ID_DFR0_EL1, 0x0, "ID_DFR0_EL1" , AA64}, - {ID_ISAR0_EL1, 0x0, "ID_ISAR0_EL1" , AA64}, - {ID_ISAR1_EL1, 0x0, "ID_ISAR1_EL1" , AA64}, - {ID_ISAR2_EL1, 0x0, "ID_ISAR2_EL1" , AA64}, - {ID_ISAR3_EL1, 0x0, "ID_ISAR3_EL1" , AA64}, - {ID_ISAR4_EL1, 0x0, "ID_ISAR4_EL1" , AA64}, - {ID_ISAR5_EL1, 0x0, "ID_ISAR5_EL1" , AA64}, - {ID_MMFR0_EL1, 0x0, "ID_MMFR0_EL1" , AA64}, - {ID_MMFR1_EL1, 0x0, "ID_MMFR1_EL1" , AA64}, - {ID_MMFR2_EL1, 0x0, "ID_MMFR2_EL1" , AA64}, - {ID_MMFR3_EL1, 0x0, "ID_MMFR3_EL1" , AA64}, - {ID_MMFR4_EL1, 0x0, "ID_MMFR4_EL1" , AA64}, - {ID_PFR0_EL1, 0x0, "ID_PFR0_EL1" , AA64}, - {ID_PFR1_EL1, 0x0, "ID_PFR1_EL1" , AA64}, - {MVFR0_EL1, 0x0, "MVFR0_EL1" , AA64}, - {MVFR1_EL1, 0x0, "MVFR1_EL1" , AA64}, - {MVFR2_EL1, 0x0, "MVFR2_EL1" , AA64}, + {ID_DFR0_EL1, 0x0, "ID_DFR0_EL1" , AA32}, + {ID_ISAR0_EL1, 0x0, "ID_ISAR0_EL1" , AA32}, + {ID_ISAR1_EL1, 0x0, "ID_ISAR1_EL1" , AA32}, + {ID_ISAR2_EL1, 0x0, "ID_ISAR2_EL1" , AA32}, + {ID_ISAR3_EL1, 0x0, "ID_ISAR3_EL1" , AA32}, + {ID_ISAR4_EL1, 0x0, "ID_ISAR4_EL1" , AA32}, + {ID_ISAR5_EL1, 0x0, "ID_ISAR5_EL1" , AA32}, + {ID_MMFR0_EL1, 0x0, "ID_MMFR0_EL1" , AA32}, + {ID_MMFR1_EL1, 0x0, "ID_MMFR1_EL1" , AA32}, + {ID_MMFR2_EL1, 0x0, "ID_MMFR2_EL1" , AA32}, + {ID_MMFR3_EL1, 0x0, "ID_MMFR3_EL1" , AA32}, + {ID_MMFR4_EL1, 0x0, "ID_MMFR4_EL1" , AA32}, + {ID_PFR0_EL1, 0x0, "ID_PFR0_EL1" , AA32}, + {ID_PFR1_EL1, 0x0, "ID_PFR1_EL1" , AA32}, + {MVFR0_EL1, 0x0, "MVFR0_EL1" , AA32}, + {MVFR1_EL1, 0x0, "MVFR1_EL1" , AA32}, + {MVFR2_EL1, 0x0, "MVFR2_EL1" , AA32}, {PMCEID0_EL0, 0x0, "PMCEID0_EL0" , 0x0 }, {PMCEID1_EL0, 0x0, "PMCEID1_EL0" , 0x0 }, {PMCR_EL0, MASK_PMCR, "PMCR_EL0" , 0x0 }, @@ -128,7 +128,7 @@ return_reg_value(uint32_t reg, uint8_t dependency) return 0; break; - case AA64: // If the register is UNK in pure AArch64 implementation, then skip register check + case AA32: // If the register is UNK in pure AArch64 implementation, then skip register check temp = val_pe_reg_read(ID_AA64PFR0_EL1); temp = (temp & 1); if(temp == 0) diff --git a/uefi_app/SbsaAvs.inf b/uefi_app/SbsaAvs.inf index f2842fcd..4462e16c 100755 --- a/uefi_app/SbsaAvs.inf +++ b/uefi_app/SbsaAvs.inf @@ -103,6 +103,7 @@ gHardwareInterruptProtocolGuid ## CONSUMES gEfiCpuArchProtocolGuid ## CONSUMES gEfiPciIoProtocolGuid ## CONSUMES + gEfiLoadedImageProtocolGuid ## CONSUMES [Guids] gEfiAcpi20TableGuid diff --git a/uefi_app/SbsaAvsMain.c b/uefi_app/SbsaAvsMain.c index d687151e..43c899e3 100755 --- a/uefi_app/SbsaAvsMain.c +++ b/uefi_app/SbsaAvsMain.c @@ -21,6 +21,7 @@ #include #include "val/include/val_interface.h" +#include "val/include/sbsa_avs_pe.h" #include "SbsaAvs.h" @@ -34,6 +35,20 @@ UINT32 g_sbsa_tests_pass; UINT32 g_sbsa_tests_fail; SHELL_FILE_HANDLE g_sbsa_log_file_handle; +STATIC VOID FlushImage (VOID) +{ + EFI_LOADED_IMAGE_PROTOCOL *ImageInfo; + EFI_STATUS Status; + Status = gBS->HandleProtocol (gImageHandle, &gEfiLoadedImageProtocolGuid, (VOID **)&ImageInfo); + if(EFI_ERROR (Status)) + { + return; + } + + val_pe_cache_clean_range((UINT64)ImageInfo->ImageBase, (UINT64)ImageInfo->ImageSize); + +} + EFI_STATUS createPeInfoTable ( ) @@ -374,6 +389,8 @@ ShellAppMain ( val_allocate_shared_mem(); + FlushImage(); + if (g_execute_secure == TRUE) { Print(L"\n *** Starting Secure FW tests *** \n"); val_secure_execute_tests(g_sbsa_level, val_pe_get_num()); diff --git a/val/include/sbsa_avs_pe.h b/val/include/sbsa_avs_pe.h index 5d9b8105..42579d09 100644 --- a/val/include/sbsa_avs_pe.h +++ b/val/include/sbsa_avs_pe.h @@ -230,6 +230,8 @@ void val_pe_spe_disable(void); uint32_t val_pe_bigend_check(uint64_t *ptr); +void val_pe_cache_clean_range(uint64_t start_addr, uint64_t length); + uint32_t c001_entry(void); uint32_t c002_entry(uint32_t num_pe); uint32_t c003_entry(uint32_t num_pe); diff --git a/val/src/avs_gic_support.c b/val/src/avs_gic_support.c index 14f40fcc..0d020f42 100644 --- a/val/src/avs_gic_support.c +++ b/val/src/avs_gic_support.c @@ -36,7 +36,7 @@ val_gic_reg_read(uint32_t reg_id) case ICH_MISR_EL2: return GicReadIchMisr(); default: - val_report_status(255, 0x87655678); + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); } return 0x0; @@ -68,7 +68,7 @@ val_gic_reg_write(uint32_t reg_id, uint64_t write_data) GicWriteIccPmr(write_data); break; default: - val_report_status(255, 0x87655678); + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); } } diff --git a/val/src/avs_memory.c b/val/src/avs_memory.c index 12f9d358..45d5ed3c 100644 --- a/val/src/avs_memory.c +++ b/val/src/avs_memory.c @@ -79,7 +79,7 @@ val_memory_create_info_table(uint64_t *memory_info_table) which matches the input type and the input instance number Instance number is '0' based 1. Caller - VAL - 2. Prerequisite - + 2. Prerequisite - @param type - type of memory being requested @param instance - instance is '0' based and incremented to get different ranges @return index @@ -103,7 +103,7 @@ val_memory_get_entry_index(uint32_t type, uint32_t instance) } /** - @brief Returns a random address whose attributes match the input + @brief Returns a random address whose attributes match the input memory type 1. Caller - Test Suite 2. Prerequisite - val_memory_create_info_table diff --git a/val/src/avs_pe.c b/val/src/avs_pe.c index e26650d1..72e8e4b5 100644 --- a/val/src/avs_pe.c +++ b/val/src/avs_pe.c @@ -198,7 +198,7 @@ val_pe_reg_read(uint32_t reg_id) case ESR_EL2: return AA64ReadEsr2(); default: - val_report_status(255, 0x87655678); + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); } return 0x0; @@ -255,7 +255,7 @@ val_pe_reg_write(uint32_t reg_id, uint64_t write_data) AA64WritePmblimitr(write_data); break; default: - val_report_status(255, 0x87655678); + val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); } } diff --git a/val/src/avs_pe_infra.c b/val/src/avs_pe_infra.c index 1ed7c4a1..118efddc 100644 --- a/val/src/avs_pe_infra.c +++ b/val/src/avs_pe_infra.c @@ -210,7 +210,7 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) g_smc_args.Arg0 = ARM_SMC_ID_PSCI_CPU_ON_AARCH64; - /* Set the TEST function pointer in a shared memory location. This location is + /* Set the TEST function pointer in a shared memory location. This location is read by the Secondary PE (val_test_entry()) and executes the test. */ g_smc_args.Arg1 = val_pe_get_mpid_index(index); @@ -226,3 +226,21 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) } } + +/** + @brief Cache clean operation on a defined address range +**/ +void +val_pe_cache_clean_range(uint64_t start_addr, uint64_t length) +{ + uint64_t aligned_addr, end_addr, line_length; + + line_length = 2 << ((val_pe_reg_read(CTR_EL0) >> 16) & 0xf); + aligned_addr = start_addr - (start_addr & (line_length-1)); + end_addr = start_addr + length; + + while(aligned_addr < end_addr){ + val_data_cache_ops_by_va(aligned_addr, CLEAN); + aligned_addr += line_length; + } +} diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c index a548aee5..6950b63c 100644 --- a/val/src/avs_test_infra.c +++ b/val/src/avs_test_infra.c @@ -68,7 +68,7 @@ val_print_raw(uint32_t level, char8_t *string, uint64_t data) @param addr 64-bit address - @return 32-bits of data + @return 32-bits of data **/ uint32_t val_mmio_read(addr_t addr) @@ -120,7 +120,7 @@ val_initialize_test(uint32_t test_num, char8_t *desc, uint32_t num_pe, uint32_t val_print(AVS_PRINT_ERR, "%4d : ", test_num); //Always print this val_print(AVS_PRINT_TEST, desc, 0); val_report_status(0, SBSA_AVS_START(level, test_num)); - + g_sbsa_tests_total++; for (i = 0; i < num_pe; i++) @@ -299,7 +299,7 @@ val_run_test_payload(uint32_t test_num, uint32_t num_pe, void (*payload)(void), //Now run the test on all other PE for (i = 0; i < num_pe; i++) { - if (i != my_index) + if (i != my_index) val_execute_on_pe(i, payload, test_input); } @@ -324,7 +324,7 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe) uint32_t error_flag = 0; uint32_t my_index = val_pe_get_index_mpid(val_pe_get_mpid()); - /* this special case is needed when the Main PE is not the first entry + /* this special case is needed when the Main PE is not the first entry of pe_info_table but num_pe is 1 for SOC tests */ if (num_pe == 1) { status = val_get_status(my_index); @@ -365,10 +365,10 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe) } /** - @brief Clean and Invalidate the Data cache line containing + @brief Clean and Invalidate the Data cache line containing the input address tag **/ -void +void val_data_cache_ops_by_va(addr_t addr, uint32_t type) { pal_pe_data_cache_ops_by_va(addr, type); From db61b5c0cd07a7eb1db73826ac766c32074e56c5 Mon Sep 17 00:00:00 2001 From: anumis01 Date: Tue, 23 May 2017 15:54:40 +0530 Subject: [PATCH 2/4] Enhanced PCIe read config anf other minor bug fixes --- platform/pal_uefi/src/pal_timer_wd.c | 4 +- test_pool/pe/test_c002.c | 3 +- test_pool/pe/test_c007.c | 2 +- test_pool/peripherals/test_d002.c | 2 +- test_pool/power_wakeup/test_u001.c | 28 ++++---- test_pool/power_wakeup/test_u002.c | 6 +- test_pool/secure/test_s002.c | 2 +- test_pool/timer_wd/test_t001.c | 2 +- test_pool/timer_wd/test_t002.c | 2 +- test_pool/timer_wd/test_t003.c | 2 +- test_pool/timer_wd/test_t004.c | 2 +- test_pool/timer_wd/test_t005.c | 2 +- test_pool/timer_wd/test_t006.c | 16 ++--- test_pool/timer_wd/test_t007.c | 100 +++++++++++++++------------ test_pool/timer_wd/test_t008.c | 56 +++++++++------ val/include/sbsa_avs_pcie.h | 1 + val/include/val_interface.h | 6 +- val/src/avs_pcie.c | 4 +- val/src/avs_timer.c | 38 ++++++++-- 19 files changed, 164 insertions(+), 114 deletions(-) diff --git a/platform/pal_uefi/src/pal_timer_wd.c b/platform/pal_uefi/src/pal_timer_wd.c index 44a76dc7..a40617be 100644 --- a/platform/pal_uefi/src/pal_timer_wd.c +++ b/platform/pal_uefi/src/pal_timer_wd.c @@ -123,10 +123,10 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable) GtEntry->GtCntEl0Base[i] = GtBlockTimer->CntEL0BaseX; GtEntry->gsiv[i] = GtBlockTimer->GTxPhysicalTimerGSIV; GtEntry->virt_gsiv[i] = GtBlockTimer->GTxVirtualTimerGSIV; - GtEntry->flags[i] = GtBlockTimer->GTxPhysicalTimerFlags | (GtBlockTimer->GTxVirtualTimerFlags << 8); + GtEntry->flags[i] = GtBlockTimer->GTxPhysicalTimerFlags | (GtBlockTimer->GTxVirtualTimerFlags << 8) | (GtBlockTimer->GTxCommonFlags << 16); GtBlockTimer++; + TimerTable->header.num_platform_timer++; } - TimerTable->header.num_platform_timer++; GtEntry++; } diff --git a/test_pool/pe/test_c002.c b/test_pool/pe/test_c002.c index 967d3408..b8ba2d83 100755 --- a/test_pool/pe/test_c002.c +++ b/test_pool/pe/test_c002.c @@ -28,8 +28,9 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); data = val_pe_reg_read(ID_AA64PFR0_EL1); + data = (data & 0xF00000) >> 20; - if ((data & 0xF00000) == 0) + if ((data == 0x0) || (data == 0x1)) val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); else val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); diff --git a/test_pool/pe/test_c007.c b/test_pool/pe/test_c007.c index da28b39c..9ed50ba6 100755 --- a/test_pool/pe/test_c007.c +++ b/test_pool/pe/test_c007.c @@ -29,7 +29,7 @@ payload() data = val_pe_reg_read(ID_AA64ISAR0_EL1); - if (((data > 4) & 0xF) && ((data >> 8) & 0xF) && ((data >> 12) & 0xF)) //bits 7:4, 11:8, 15:12 must be non-zero + if (((data >> 4) & 0xF) && ((data >> 8) & 0xF) && ((data >> 12) & 0xF)) //bits 7:4, 11:8, 15:12 must be non-zero val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); else val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); diff --git a/test_pool/peripherals/test_d002.c b/test_pool/peripherals/test_d002.c index 1a0a6108..83f7faaa 100755 --- a/test_pool/peripherals/test_d002.c +++ b/test_pool/peripherals/test_d002.c @@ -39,7 +39,7 @@ payload() } while (count != 0) { - bdf = val_peripheral_get_info(USB_BDF, count - 1); + bdf = val_peripheral_get_info(SATA_BDF, count - 1); interface = val_pcie_read_cfg(bdf, 0x8); interface = (interface >> 8) & 0xFF; if (interface != 0x01) { diff --git a/test_pool/power_wakeup/test_u001.c b/test_pool/power_wakeup/test_u001.c index cd83b59d..fb7b040b 100755 --- a/test_pool/power_wakeup/test_u001.c +++ b/test_pool/power_wakeup/test_u001.c @@ -42,7 +42,7 @@ isr_failsafe() val_timer_set_phy_el1(0); val_print(AVS_PRINT_INFO, "\n Received Failsafe interrupt ", 0); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID); + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -54,7 +54,7 @@ isr1() val_timer_set_phy_el1(0); val_print(AVS_PRINT_INFO, "\n Received EL1 PHY interrupt ", 0); val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID); + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -68,7 +68,7 @@ isr2() val_timer_set_vir_el1(0); val_print(AVS_PRINT_INFO, "\n Received EL1 VIRT interrupt ", 0); val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM2, 01)); - intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID); + intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -81,7 +81,7 @@ isr3() val_timer_set_phy_el2(0); val_print(AVS_PRINT_INFO, "\n Received EL2 Physical interrupt ", 0); val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM3, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID); + intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -108,11 +108,11 @@ static void isr5() { - uint64_t cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N); + uint64_t cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, 0); val_timer_disable_system_timer((addr_t)cnt_base_n); val_print(AVS_PRINT_INFO, "\n Received Sys timer interrupt ", 0); val_set_status(0, RESULT_PASS(g_sbsa_level, TEST_NUM5, 01)); - intid = val_timer_get_info(TIMER_INFO_SYS_INTID); + intid = val_timer_get_info(TIMER_INFO_SYS_INTID, 0); val_gic_end_of_interrupt(intid); } @@ -122,7 +122,7 @@ wakeup_set_failsafe() { uint64_t timer_expire_val = 900000; - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID); + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_install_isr(intid, isr_failsafe); val_timer_set_phy_el1(timer_expire_val); } @@ -143,7 +143,7 @@ payload1() val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID); + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); val_gic_install_isr(intid, isr1); val_timer_set_phy_el1(timer_expire_val); val_power_enter_semantic(SBSA_POWER_SEM_B); @@ -158,7 +158,7 @@ payload2() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM2, 01)); - intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID); + intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); val_gic_install_isr(intid, isr2); wakeup_set_failsafe(); val_timer_set_vir_el1(timer_expire_val); @@ -175,7 +175,7 @@ payload3() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM3, 01)); - intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID); + intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); val_gic_install_isr(intid, isr3); wakeup_set_failsafe(); val_timer_set_phy_el2(timer_expire_val); @@ -220,22 +220,22 @@ payload5() uint32_t status; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - if (val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS)) { + if (val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0)) { //Read CNTACR to determine whether access permission from NS state is permitted - status = val_timer_skip_if_cntbase_access_not_allowed(); + status = val_timer_skip_if_cntbase_access_not_allowed(0); if(status == AVS_STATUS_SKIP){ val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM5, 02)); return; } - cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N); + cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, 0); if(cnt_base_n == 0){ val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM5, 03)); return; } - intid = val_timer_get_info(TIMER_INFO_SYS_INTID); + intid = val_timer_get_info(TIMER_INFO_SYS_INTID, 0); status = val_gic_install_isr(intid, isr5); if(status == 0) { diff --git a/test_pool/power_wakeup/test_u002.c b/test_pool/power_wakeup/test_u002.c index fb8f6f9a..ddf09943 100755 --- a/test_pool/power_wakeup/test_u002.c +++ b/test_pool/power_wakeup/test_u002.c @@ -50,11 +50,11 @@ wakeup_event_for_semantic_f() num = val_wd_get_info(0, WD_INFO_COUNT); if(num == 0){ - num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS); + num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); if(num == 0) return 0; else{ - intid = val_timer_get_info(TIMER_INFO_SYS_INTID); + intid = val_timer_get_info(TIMER_INFO_SYS_INTID, 0); return SYSTIMER_SEMF; } } @@ -128,7 +128,7 @@ payload() // Step5: Program timer/watchdog, which on expiry will generate an interrupt // and wake target PE if(wakeup_event == SYSTIMER_SEMF){ - cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N); + cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, 0); val_timer_set_system_timer((addr_t)cnt_base_n, timer_expire_ticks); } else if(wakeup_event == WATCHDOG_SEMF){ diff --git a/test_pool/secure/test_s002.c b/test_pool/secure/test_s002.c index 0fc4baf3..c5c25422 100755 --- a/test_pool/secure/test_s002.c +++ b/test_pool/secure/test_s002.c @@ -50,7 +50,7 @@ payload() SBSA_SMC_t smc; - if (!val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS)) { + if (!val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0)) { val_print(AVS_PRINT_WARN, "\n No System timers implemented ", 0); val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); return; diff --git a/test_pool/timer_wd/test_t001.c b/test_pool/timer_wd/test_t001.c index dedc4138..66778fb0 100755 --- a/test_pool/timer_wd/test_t001.c +++ b/test_pool/timer_wd/test_t001.c @@ -30,7 +30,7 @@ payload() uint32_t counter_freq; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - counter_freq = val_timer_get_info(TIMER_INFO_CNTFREQ); + counter_freq = val_timer_get_info(TIMER_INFO_CNTFREQ, 0); if ((counter_freq > 10*1000*1000) && (counter_freq < 400*1000*1000)) { val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); diff --git a/test_pool/timer_wd/test_t002.c b/test_pool/timer_wd/test_t002.c index a777ba36..0a27378e 100755 --- a/test_pool/timer_wd/test_t002.c +++ b/test_pool/timer_wd/test_t002.c @@ -44,7 +44,7 @@ payload() uint32_t timer_expire_val = 10000; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID); + intid = val_timer_get_info(TIMER_INFO_PHY_EL1_INTID, 0); /* For SBSA level 2 and above, the PPI has to be a specific value. */ if (g_sbsa_level > 1) { if (intid != 30) { diff --git a/test_pool/timer_wd/test_t003.c b/test_pool/timer_wd/test_t003.c index 561461fd..d2bc949f 100755 --- a/test_pool/timer_wd/test_t003.c +++ b/test_pool/timer_wd/test_t003.c @@ -47,7 +47,7 @@ payload() uint64_t timer_expire_val = 10000; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID); + intid = val_timer_get_info(TIMER_INFO_VIR_EL1_INTID, 0); /* For SBSA level 2 and above, the PPI has to be a specific value.*/ if (g_sbsa_level > 1) { if (intid != 27) { diff --git a/test_pool/timer_wd/test_t004.c b/test_pool/timer_wd/test_t004.c index dbd3f1e3..ab8bc34d 100755 --- a/test_pool/timer_wd/test_t004.c +++ b/test_pool/timer_wd/test_t004.c @@ -47,7 +47,7 @@ payload() uint64_t timer_expire_val = 10000; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID); + intid = val_timer_get_info(TIMER_INFO_PHY_EL2_INTID, 0); /* For SBSA level 2 and above, the PPI has to be a specific value. */ if (g_sbsa_level > 1) { if (intid != 26) { diff --git a/test_pool/timer_wd/test_t005.c b/test_pool/timer_wd/test_t005.c index 375a3a9d..0f25471c 100755 --- a/test_pool/timer_wd/test_t005.c +++ b/test_pool/timer_wd/test_t005.c @@ -58,7 +58,7 @@ payload() return; } - intid = val_timer_get_info(TIMER_INFO_VIR_EL2_INTID); + intid = val_timer_get_info(TIMER_INFO_VIR_EL2_INTID, 0); /* For SBSA level 2 and above, the PPI has to be a specific value.*/ if (g_sbsa_level > 1) { if (intid != 28) { diff --git a/test_pool/timer_wd/test_t006.c b/test_pool/timer_wd/test_t006.c index 2faabbe7..6b03c5a0 100755 --- a/test_pool/timer_wd/test_t006.c +++ b/test_pool/timer_wd/test_t006.c @@ -30,14 +30,14 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); - if (val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS) == 0) { - //val_print(AVS_PRINT_ERR, "\n %x \n", val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS)); - //val_print(AVS_PRINT_ERR, "\n %x \n", val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS)); - //val_print(AVS_PRINT_ERR, "\n %x \n", val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS)); - - if((val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS) & SBSA_TIMER_FLAG_ALWAYS_ON) && - (val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS) & SBSA_TIMER_FLAG_ALWAYS_ON) && - (val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS) & SBSA_TIMER_FLAG_ALWAYS_ON)) { + if (val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0) == 0) { + val_print(AVS_PRINT_INFO, "\n Physical EL1 timer flag = %x", val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS, 0)); + val_print(AVS_PRINT_INFO, "\n Physical EL2 timer flag = %x", val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS, 0)); + val_print(AVS_PRINT_INFO, "\n Virtual EL1 timer flag = %x", val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS, 0)); + + if((val_timer_get_info(TIMER_INFO_PHY_EL1_FLAGS, 0) & SBSA_TIMER_FLAG_ALWAYS_ON) && + (val_timer_get_info(TIMER_INFO_PHY_EL2_FLAGS, 0) & SBSA_TIMER_FLAG_ALWAYS_ON) && + (val_timer_get_info(TIMER_INFO_VIR_EL1_FLAGS, 0) & SBSA_TIMER_FLAG_ALWAYS_ON)) { val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } else { val_print(AVS_PRINT_ERR, "\n PE Timers are not always-on. ", 0); diff --git a/test_pool/timer_wd/test_t007.c b/test_pool/timer_wd/test_t007.c index 65632673..b4affaa8 100755 --- a/test_pool/timer_wd/test_t007.c +++ b/test_pool/timer_wd/test_t007.c @@ -30,60 +30,68 @@ payload() uint64_t cnt_ctl_base, cnt_base_n; uint32_t data; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); - if (!val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS)) { + if (!timer_num) { val_print(AVS_PRINT_WARN, "\n No System timers are defined ", 0); val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); return; } - cnt_ctl_base = val_timer_get_info(TIMER_INFO_SYS_CNTL_BASE); - cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N); - - if (cnt_ctl_base == 0) { - val_print(AVS_PRINT_WARN, "\n CNTCTL BASE_N is zero ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - - data = val_mmio_read(cnt_ctl_base + 0x0); - if (!data) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); - val_print(AVS_PRINT_ERR, "\n CNTCTLBase.CNTFRQ should not be 0 from NS mode ", 0); - return; + while(timer_num){ + --timer_num; //array index starts from 0, so subtract 1 from count + + if (val_timer_get_info(TIMER_INFO_IS_PLATFORM_TIMER_SECURE, timer_num)) + continue; //Skip Secure Timer + + cnt_ctl_base = val_timer_get_info(TIMER_INFO_SYS_CNTL_BASE, timer_num); + cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); + + if (cnt_ctl_base == 0) { + val_print(AVS_PRINT_WARN, "\n CNTCTL BASE_N is zero ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + + data = val_mmio_read(cnt_ctl_base + 0xFD0); + if ((data == 0x0) || ((data & 0xFFFF) == 0xFFFF)) { + val_print(AVS_PRINT_ERR, "\n Unxepected value for CNTCTLBase.CounterID %x ", data); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + + if (cnt_base_n == 0) { + val_print(AVS_PRINT_WARN, "\n CNT_BASE_N is zero ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + data = val_mmio_read(cnt_base_n + 0x0); + val_mmio_write(cnt_base_n + 0x0, 0xFFFFFF); + if(data != val_mmio_read(cnt_base_n + 0x0)) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); + val_print(AVS_PRINT_ERR, "\n CNTBaseN offset 0 should be read-only ", 0); + return; + } + + data = val_mmio_read(cnt_ctl_base + 0x10); + if (!data) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + val_print(AVS_PRINT_ERR, "\n CNTBaseN.CNTFRQ should not be 0 ", 0); + return; + } + + data = val_mmio_read(cnt_base_n + 0xFD0); + if ((data == 0x0) || ((data & 0xFFFF) == 0xFFFF)) { + val_print(AVS_PRINT_ERR, "\n Unxepected value for CNTBaseN.CounterID %x ", data); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 06)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } - data = val_mmio_read(cnt_ctl_base + 0xFD0); - if ((data == 0x0) || ((data & 0xFFFF) == 0xFFFF)) { - val_print(AVS_PRINT_ERR, "\n Unxepected value for CounterID %x ", data); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); - return; - } - - - if (cnt_base_n == 0) { - val_print(AVS_PRINT_WARN, "\n CNT_BASE_N is zero ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } - - data = val_mmio_read(cnt_base_n + 0x0); - val_mmio_write(cnt_base_n + 0x0, 0xFFFFFF); - if(data != val_mmio_read(cnt_base_n + 0x0)) { - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 05)); - val_print(AVS_PRINT_ERR, "\n CNTBaseN offset 0 should be read-only ", 0); - return; - } - data = val_mmio_read(cnt_base_n + 0xFD0); - if ((data == 0x0) || ((data & 0xFFFF) == 0xFFFF)) { - val_print(AVS_PRINT_ERR, "\n Unxepected value for CounterID %x ", data); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 06)); - return; - } - - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - } uint32_t diff --git a/test_pool/timer_wd/test_t008.c b/test_pool/timer_wd/test_t008.c index cb819e8e..2393b020 100644 --- a/test_pool/timer_wd/test_t008.c +++ b/test_pool/timer_wd/test_t008.c @@ -30,7 +30,7 @@ static void isr() { - uint64_t cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N); + uint64_t cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, 0); val_print(AVS_PRINT_INFO, "\n Received interrupt ", 0); val_timer_disable_system_timer((addr_t)cnt_base_n); @@ -48,38 +48,48 @@ payload() uint32_t timeout = TIMEOUT_MEDIUM; uint32_t status; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint64_t timer_num = val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS, 0); - if (!val_timer_get_info(TIMER_INFO_NUM_PLATFORM_TIMERS)) { + if (!timer_num) { val_print(AVS_PRINT_WARN, "\n No System timers are defined ", 0); val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); return; } - //Read CNTACR to determine whether access permission from NS state is permitted - status = val_timer_skip_if_cntbase_access_not_allowed(); - if(status == AVS_STATUS_SKIP){ - val_print(AVS_PRINT_WARN, "\n Security doesn't allow access to timer registers ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); - return; - } + while(timer_num){ + timer_num--; //array index starts from 0, so subtract 1 from count - cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N); - if (cnt_base_n == 0) { - val_print(AVS_PRINT_WARN, "\n CNT_BASE_N is zero ", 0); - val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); - return; - } - /* Install ISR */ - intid = val_timer_get_info(TIMER_INFO_SYS_INTID); - val_gic_install_isr(intid, isr); + if (val_timer_get_info(TIMER_INFO_IS_PLATFORM_TIMER_SECURE, timer_num)) + continue; //Skip Secure Timer - /* enable System timer */ - val_timer_set_system_timer((addr_t)cnt_base_n, timeout); + //Read CNTACR to determine whether access permission from NS state is permitted + status = val_timer_skip_if_cntbase_access_not_allowed(timer_num); + if(status == AVS_STATUS_SKIP){ + val_print(AVS_PRINT_WARN, "\n Security doesn't allow access to timer registers ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } - while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); + cnt_base_n = val_timer_get_info(TIMER_INFO_SYS_CNT_BASE_N, timer_num); + if (cnt_base_n == 0) { + val_print(AVS_PRINT_WARN, "\n CNT_BASE_N is zero ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } - if (timeout == 0) - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + /* Install ISR */ + intid = val_timer_get_info(TIMER_INFO_SYS_INTID, timer_num); + val_gic_install_isr(intid, isr); + + /* enable System timer */ + val_timer_set_system_timer((addr_t)cnt_base_n, timeout); + + while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); + + if (timeout == 0) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + timer_num = 0; + } } diff --git a/val/include/sbsa_avs_pcie.h b/val/include/sbsa_avs_pcie.h index ec5168eb..238a6629 100644 --- a/val/include/sbsa_avs_pcie.h +++ b/val/include/sbsa_avs_pcie.h @@ -17,6 +17,7 @@ #ifndef __SBSA_AVS_PCIE_H__ #define __SBSA_AVS_PCIE_H__ +#define PCIE_EXTRACT_BDF_SEG(bdf) ((bdf >> 24) & 0xFF) #define PCIE_EXTRACT_BDF_BUS(bdf) ((bdf >> 16) & 0xFF) #define PCIE_EXTRACT_BDF_DEV(bdf) ((bdf >> 8) & 0xFF) #define PCIE_EXTRACT_BDF_FUNC(bdf) (bdf & 0xFF) diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 5aaaa3f7..41b59011 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -92,6 +92,7 @@ typedef enum { TIMER_INFO_VIR_EL2_INTID, TIMER_INFO_VIR_EL2_FLAGS, TIMER_INFO_NUM_PLATFORM_TIMERS, + TIMER_INFO_IS_PLATFORM_TIMER_SECURE, TIMER_INFO_SYS_CNTL_BASE, TIMER_INFO_SYS_CNT_BASE_N, TIMER_INFO_SYS_INTID @@ -102,14 +103,15 @@ typedef enum { void val_timer_create_info_table(uint64_t *timer_info_table); void val_timer_free_info_table(void); uint32_t val_timer_execute_tests(uint32_t level, uint32_t num_pe); -uint64_t val_timer_get_info(TIMER_INFO_e info_type); +uint64_t val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance); void val_timer_set_phy_el1(uint64_t timeout); void val_timer_set_vir_el1(uint64_t timeout); void val_timer_set_phy_el2(uint64_t timeout); void val_timer_set_vir_el2(uint64_t timeout); void val_timer_set_system_timer(addr_t cnt_base_n, uint32_t timeout); void val_timer_disable_system_timer(addr_t cnt_base_n); -uint32_t val_timer_skip_if_cntbase_access_not_allowed(void); +uint32_t val_timer_skip_if_cntbase_access_not_allowed(uint64_t index); +void val_platform_timer_get_entry_index(uint64_t instance, uint32_t *block, uint32_t *index); /* Watchdog VAL APIs */ typedef enum { diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c index cab31a5f..941477b8 100644 --- a/val/src/avs_pcie.c +++ b/val/src/avs_pcie.c @@ -40,6 +40,7 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset) uint32_t bus = PCIE_EXTRACT_BDF_BUS(bdf); uint32_t dev = PCIE_EXTRACT_BDF_DEV(bdf); uint32_t func = PCIE_EXTRACT_BDF_FUNC(bdf); + uint32_t segment = PCIE_EXTRACT_BDF_SEG(bdf); uint32_t cfg_addr; addr_t ecam_base = 0; uint32_t i = 0; @@ -58,7 +59,8 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset) { if ((bus >= val_pcie_get_info(PCIE_INFO_START_BUS, i)) && - (bus <= val_pcie_get_info(PCIE_INFO_END_BUS, i))) { + (bus <= val_pcie_get_info(PCIE_INFO_END_BUS, i)) && + (segment == val_pcie_get_info(PCIE_INFO_SEGMENT, i))) { ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, i); if (ecam_base == 0) { diff --git a/val/src/avs_timer.c b/val/src/avs_timer.c index 545a1db1..724193ff 100644 --- a/val/src/avs_timer.c +++ b/val/src/avs_timer.c @@ -75,9 +75,10 @@ val_timer_execute_tests(uint32_t level, uint32_t num_pe) **/ uint64_t -val_timer_get_info(TIMER_INFO_e info_type) +val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance) { + uint32_t block_num, block_index; if (g_timer_info_table == NULL) return 0; @@ -94,12 +95,22 @@ val_timer_get_info(TIMER_INFO_e info_type) return g_timer_info_table->header.el2_virt_timer_gsiv; case TIMER_INFO_NUM_PLATFORM_TIMERS: return g_timer_info_table->header.num_platform_timer; + case TIMER_INFO_IS_PLATFORM_TIMER_SECURE: + val_platform_timer_get_entry_index (instance, &block_num, &block_index); + if (block_num != 0xFFFF) + return ((g_timer_info_table->gt_info[block_num].flags[block_index] >> 16) & 1); case TIMER_INFO_SYS_CNTL_BASE: - return g_timer_info_table->gt_info[0].block_cntl_base; + val_platform_timer_get_entry_index (instance, &block_num, &block_index); + if (block_num != 0xFFFF) + return g_timer_info_table->gt_info[block_num].block_cntl_base; case TIMER_INFO_SYS_CNT_BASE_N: - return g_timer_info_table->gt_info[0].GtCntBase[0]; + val_platform_timer_get_entry_index (instance, &block_num, &block_index); + if (block_num != 0xFFFF) + return g_timer_info_table->gt_info[block_num].GtCntBase[block_index]; case TIMER_INFO_SYS_INTID: - return g_timer_info_table->gt_info[0].gsiv[0]; + val_platform_timer_get_entry_index (instance, &block_num, &block_index); + if (block_num != 0xFFFF) + return g_timer_info_table->gt_info[block_num].gsiv[block_index]; case TIMER_INFO_PHY_EL1_FLAGS: return g_timer_info_table->header.ns_el1_timer_flag; case TIMER_INFO_VIR_EL1_FLAGS: @@ -111,7 +122,22 @@ val_timer_get_info(TIMER_INFO_e info_type) } } +void +val_platform_timer_get_entry_index(uint64_t instance, uint32_t *block, uint32_t *index) +{ + if(instance > g_timer_info_table->header.num_platform_timer){ + *block = 0xFFFF; + return; + } + *block = 0; + *index = instance; + while (instance > g_timer_info_table->gt_info[*block].timer_count){ + instance = instance - g_timer_info_table->gt_info[*block].timer_count; + *index = instance; + *block = *block + 1; + } +} /** @brief This API enables the Architecture timer whose register is given as the input parameter. 1. Caller - VAL @@ -307,12 +333,12 @@ val_timer_disable_system_timer(addr_t cnt_base_n) access permission from NS state is permitted **/ uint32_t -val_timer_skip_if_cntbase_access_not_allowed() +val_timer_skip_if_cntbase_access_not_allowed(uint64_t index) { uint64_t cnt_ctl_base; uint32_t data; - cnt_ctl_base = val_timer_get_info(TIMER_INFO_SYS_CNTL_BASE); + cnt_ctl_base = val_timer_get_info(TIMER_INFO_SYS_CNTL_BASE, index); if(cnt_ctl_base){ data = val_mmio_read(cnt_ctl_base + 0x40); if((data & 0x1) == 0x1) From e5b5e489f0a591a269c3d9c3994d91b899f0e32a Mon Sep 17 00:00:00 2001 From: anumis01 Date: Mon, 29 May 2017 18:57:54 +0530 Subject: [PATCH 3/4] Modified API used for updating ELR, added init code in PMUIRQ test and cache ops to happen on the struct member accessed, instead of base memory pointer --- platform/pal_uefi/src/AArch64/AvsTestInfra.S | 20 ---------------- platform/pal_uefi/src/pal_pe.c | 12 ++++------ test_pool/pe/test_c011.c | 7 +++++- test_pool/peripherals/test_m001.c | 4 ++-- test_pool/peripherals/test_m002.c | 4 ++-- test_pool/secure/test_s002.c | 4 ++-- val/include/pal_interface.h | 4 ++-- val/include/sbsa_avs_pe.h | 2 +- val/include/val_interface.h | 2 +- val/src/avs_pe.c | 24 -------------------- val/src/avs_pe_infra.c | 23 +++++++++++++++++++ val/src/avs_status.c | 4 ++-- val/src/avs_test_infra.c | 10 ++++---- 13 files changed, 51 insertions(+), 69 deletions(-) diff --git a/platform/pal_uefi/src/AArch64/AvsTestInfra.S b/platform/pal_uefi/src/AArch64/AvsTestInfra.S index e3f7c23e..9bfae852 100644 --- a/platform/pal_uefi/src/AArch64/AvsTestInfra.S +++ b/platform/pal_uefi/src/AArch64/AvsTestInfra.S @@ -18,13 +18,10 @@ .text .align 3 -GCC_ASM_EXPORT(UpdateElr) GCC_ASM_EXPORT(DataCacheCleanInvalidateVA) GCC_ASM_EXPORT(DataCacheInvalidateVA) GCC_ASM_EXPORT(DataCacheCleanVA) -#define FP_CONTEXT_SIZE 0x200 - ASM_PFX(DataCacheCleanInvalidateVA): dc civac, x0 dsb sy @@ -43,20 +40,3 @@ ASM_PFX(DataCacheInvalidateVA): isb ret -ASM_PFX(UpdateElr): - // This function returns the stacked address of ELR in UEFI exception path - // The sequence of context save before the control is handed over - // to test-specific handler includes: - // 1. General Purpose registers, occupying 0x100 bytes (32*8) - // 2. Floating Point registers, occupying 0x200 bytes (32*16) - // 3. System Registers, occupying 0x30 (6*8) - ELR,SPSR,FPSR,ESR,FAR - // X28 points to start of FP context, and an offset of 0x200 should be - // added to make it point to system register context and - // ELR is the first register stacked there. - // For more info on the calculation of stacked address, please refer following file: - // /ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S - - add x1, x28, #FP_CONTEXT_SIZE - str x0, [x1] // Update the stacked location with user address - - ret diff --git a/platform/pal_uefi/src/pal_pe.c b/platform/pal_uefi/src/pal_pe.c index eed06802..8a43ac59 100644 --- a/platform/pal_uefi/src/pal_pe.c +++ b/platform/pal_uefi/src/pal_pe.c @@ -169,7 +169,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable) @return status of the API **/ UINT32 -pal_pe_install_esr(UINT32 ExceptionType, VOID (*esr)()) +pal_pe_install_esr(UINT32 ExceptionType, VOID (*esr)(UINT64, VOID *)) { EFI_STATUS Status; @@ -195,7 +195,7 @@ pal_pe_install_esr(UINT32 ExceptionType, VOID (*esr)()) // // Register to receive interrupts // - Status = Cpu->RegisterInterruptHandler (Cpu, ExceptionType, esr); + Status = Cpu->RegisterInterruptHandler (Cpu, ExceptionType, (EFI_CPU_INTERRUPT_HANDLER)esr); if (EFI_ERROR (Status)) { return Status; } @@ -244,13 +244,9 @@ pal_pe_execute_payload(ARM_SMC_ARGS *ArmSmcArgs) } VOID -UpdateElr(UINT64 offset); - - -VOID -pal_pe_update_elr(UINT64 offset) +pal_pe_update_elr(VOID *context, UINT64 offset) { - UpdateElr(offset); + ((EFI_SYSTEM_CONTEXT_AARCH64*)context)->ELR = offset; } VOID diff --git a/test_pool/pe/test_c011.c b/test_pool/pe/test_c011.c index b912534a..050a4d6c 100755 --- a/test_pool/pe/test_c011.c +++ b/test_pool/pe/test_c011.c @@ -27,7 +27,12 @@ void set_pmu_overflow() { uint64_t pmcr; - + + //Initializing the state of overflow status and interrupt request registers + val_pe_reg_write(PMINTENCLR_EL1, 0xFFFFFFFF); + val_pe_reg_write(PMOVSCLR_EL0, 0xFFFFFFFF); + + //Sequence to generate PMUIRQ pmcr = val_pe_reg_read(PMCR_EL0); val_pe_reg_write(PMCR_EL0, pmcr|0x1); diff --git a/test_pool/peripherals/test_m001.c b/test_pool/peripherals/test_m001.c index 9c8ab6a2..5af2d5f7 100755 --- a/test_pool/peripherals/test_m001.c +++ b/test_pool/peripherals/test_m001.c @@ -35,12 +35,12 @@ payload(); static void -esr() +esr(uint64_t interrupt_type, void *context) { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); /* Update the ELR to point to next instrcution */ - val_pe_update_elr((uint64_t)branch_to_test); + val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(AVS_PRINT_INFO, "\n Received DAbort Exception ", 0); val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); diff --git a/test_pool/peripherals/test_m002.c b/test_pool/peripherals/test_m002.c index 18f0e4a3..7fd0ccae 100644 --- a/test_pool/peripherals/test_m002.c +++ b/test_pool/peripherals/test_m002.c @@ -28,13 +28,13 @@ static void *branch_to_test; static void -esr() +esr(uint64_t interrupt_type, void *context) { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); uint64_t syndrome; /* Update the ELR to return to test specified address */ - val_pe_update_elr((uint64_t)branch_to_test); + val_pe_update_elr(context, (uint64_t)branch_to_test); syndrome = val_pe_reg_read(ESR_EL2); syndrome &= 0x3F; // Get the DFSC field from ESR diff --git a/test_pool/secure/test_s002.c b/test_pool/secure/test_s002.c index c5c25422..b99c5307 100755 --- a/test_pool/secure/test_s002.c +++ b/test_pool/secure/test_s002.c @@ -28,12 +28,12 @@ static void *branch_to_test; static void -esr() +esr(uint64_t interrupt_type, void *context) { uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); /* Update the ELR to return to test specified address */ - val_pe_update_elr((uint64_t)branch_to_test); + val_pe_update_elr(context, (uint64_t)branch_to_test); val_print(AVS_PRINT_INFO, "\n Received exception ", 0); val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index 9f6a52ef..7bc6473f 100755 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -82,7 +82,7 @@ typedef struct { void pal_pe_call_smc(ARM_SMC_ARGS *args); void pal_pe_execute_payload(ARM_SMC_ARGS *args); -uint32_t pal_pe_install_esr(uint32_t exception_type, void (*esr)(void)); +uint32_t pal_pe_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void *)); /* ********** PE INFO END **********/ @@ -404,7 +404,7 @@ uint64_t pal_mem_get_shared_addr(void); uint32_t pal_mmio_read(uint64_t addr); void pal_mmio_write(uint64_t addr, uint32_t data); -void pal_pe_update_elr(uint64_t offset); +void pal_pe_update_elr(void *context, uint64_t offset); void pal_pe_data_cache_ops_by_va(uint64_t addr, uint32_t type); #define CLEAN_AND_INVALIDATE 0x1 diff --git a/val/include/sbsa_avs_pe.h b/val/include/sbsa_avs_pe.h index 42579d09..13b9f438 100644 --- a/val/include/sbsa_avs_pe.h +++ b/val/include/sbsa_avs_pe.h @@ -222,7 +222,7 @@ void DisableSpe(void); uint32_t BigEndianCheck(uint64_t *ptr); -void val_pe_update_elr(uint32_t offset); +void val_pe_update_elr(void *context, uint64_t offset); void val_pe_spe_program_under_profiling(uint64_t interval, addr_t address); diff --git a/val/include/val_interface.h b/val/include/val_interface.h index 41b59011..5e1cb792 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -51,7 +51,7 @@ uint64_t val_pe_get_mpid_index(uint32_t index); uint32_t val_pe_get_pmu_gsiv(uint32_t index); uint64_t val_pe_get_mpid(void); uint32_t val_pe_get_index_mpid(uint64_t mpid); -uint32_t val_pe_install_esr(uint32_t exception_type, void (*esr)(void)); +uint32_t val_pe_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void *)); void val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t args); void val_suspend_pe(uint32_t power_state, uint64_t entry, uint32_t context_id); diff --git a/val/src/avs_pe.c b/val/src/avs_pe.c index 72e8e4b5..4de04c26 100644 --- a/val/src/avs_pe.c +++ b/val/src/avs_pe.c @@ -318,30 +318,6 @@ val_pe_get_pmu_gsiv(uint32_t index) } - -/** - @brief This API installs the Exception handler pointed - by the function pointer to the input exception type. - 1. Caller - Test Suite - 2. Prerequisite - None - @param exception_type - one of the four exceptions defined by AARCH64 - @param esr - Function pointer of the exception handler - @return 0 if success or ERROR for invalid Exception type. -**/ -uint32_t -val_pe_install_esr(uint32_t exception_type, void (*esr)(void)) -{ - - if (exception_type > 3) { - val_print(AVS_PRINT_ERR, "Invalid Exception type %x \n", exception_type); - return AVS_STATUS_ERR; - } - - pal_pe_install_esr(exception_type, esr); - - return 0; -} - /** @brief This API will call an assembly sequence with interval as argument over which an SPE event is exected to be generated. diff --git a/val/src/avs_pe_infra.c b/val/src/avs_pe_infra.c index 118efddc..2b43dc57 100644 --- a/val/src/avs_pe_infra.c +++ b/val/src/avs_pe_infra.c @@ -244,3 +244,26 @@ val_pe_cache_clean_range(uint64_t start_addr, uint64_t length) aligned_addr += line_length; } } + +/** + @brief This API installs the Exception handler pointed + by the function pointer to the input exception type. + 1. Caller - Test Suite + 2. Prerequisite - None + @param exception_type - one of the four exceptions defined by AARCH64 + @param esr - Function pointer of the exception handler + @return 0 if success or ERROR for invalid Exception type. +**/ +uint32_t +val_pe_install_esr(uint32_t exception_type, void (*esr)(uint64_t, void *)) +{ + + if (exception_type > 3) { + val_print(AVS_PRINT_ERR, "Invalid Exception type %x \n", exception_type); + return AVS_STATUS_ERR; + } + + pal_pe_install_esr(exception_type, esr); + + return 0; +} diff --git a/val/src/avs_status.c b/val/src/avs_status.c index 695c8a37..4a670ff6 100644 --- a/val/src/avs_status.c +++ b/val/src/avs_status.c @@ -73,7 +73,7 @@ val_set_status(uint32_t index, uint32_t status) mem = mem + index; mem->status = status; - val_data_cache_ops_by_va((addr_t)mem, CLEAN_AND_INVALIDATE); + val_data_cache_ops_by_va((addr_t)&mem->status, CLEAN_AND_INVALIDATE); } /** @@ -91,7 +91,7 @@ val_get_status(uint32_t index) mem = (VAL_SHARED_MEM_t *) pal_mem_get_shared_addr(); mem = mem + index; - val_data_cache_ops_by_va((addr_t)mem, INVALIDATE); + val_data_cache_ops_by_va((addr_t)&mem->status, INVALIDATE); return (uint32_t)(mem->status); diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c index 6950b63c..98a28ae8 100644 --- a/val/src/avs_test_infra.c +++ b/val/src/avs_test_infra.c @@ -198,7 +198,8 @@ val_set_test_data(uint32_t index, uint64_t addr, uint64_t test_data) mem->data0 = addr; mem->data1 = test_data; - val_data_cache_ops_by_va((addr_t)mem, CLEAN_AND_INVALIDATE); + val_data_cache_ops_by_va((addr_t)&mem->data0, CLEAN_AND_INVALIDATE); + val_data_cache_ops_by_va((addr_t)&mem->data1, CLEAN_AND_INVALIDATE); } /** @@ -227,7 +228,8 @@ val_get_test_data(uint32_t index, uint64_t *data0, uint64_t *data1) mem = (VAL_SHARED_MEM_t *) pal_mem_get_shared_addr(); mem = mem + index; - val_data_cache_ops_by_va((addr_t)mem, INVALIDATE); + val_data_cache_ops_by_va((addr_t)&mem->data0, INVALIDATE); + val_data_cache_ops_by_va((addr_t)&mem->data1, INVALIDATE); *data0 = mem->data0; *data1 = mem->data1; @@ -379,7 +381,7 @@ val_data_cache_ops_by_va(addr_t addr, uint32_t type) @brief Update ELR based on the offset provided **/ void -val_pe_update_elr(uint32_t offset) +val_pe_update_elr(void *context, uint64_t offset) { - pal_pe_update_elr(offset); + pal_pe_update_elr(context, offset); } From 85151b597666b5c708953023e8da44849508d458 Mon Sep 17 00:00:00 2001 From: Sakar Arora Date: Wed, 31 May 2017 11:53:38 +0530 Subject: [PATCH 4/4] Bug fix for undefined function reference in kernel module Signed-off-by: Sakar Arora --- val/src/avs_pe_infra.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/val/src/avs_pe_infra.c b/val/src/avs_pe_infra.c index 2b43dc57..0356b9ee 100644 --- a/val/src/avs_pe_infra.c +++ b/val/src/avs_pe_infra.c @@ -233,6 +233,7 @@ val_execute_on_pe(uint32_t index, void (*payload)(void), uint64_t test_input) void val_pe_cache_clean_range(uint64_t start_addr, uint64_t length) { +#ifndef TARGET_LINUX uint64_t aligned_addr, end_addr, line_length; line_length = 2 << ((val_pe_reg_read(CTR_EL0) >> 16) & 0xf); @@ -243,6 +244,7 @@ val_pe_cache_clean_range(uint64_t start_addr, uint64_t length) val_data_cache_ops_by_va(aligned_addr, CLEAN); aligned_addr += line_length; } +#endif } /**