From f221ea99e86ea1d391b725c330599612fb9a73fb Mon Sep 17 00:00:00 2001 From: sakar arora Date: Mon, 16 Apr 2018 09:29:14 +0530 Subject: [PATCH 1/6] Bug fix test 58: use msi desc irq number (#45) Signed-off-by: Sakar Arora --- test_pool/pcie/test_p008.c | 11 +++++++---- val/include/pal_interface.h | 1 + val/src/avs_pcie.c | 2 +- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/test_pool/pcie/test_p008.c b/test_pool/pcie/test_p008.c index 559795ff..c85c25dc 100644 --- a/test_pool/pcie/test_p008.c +++ b/test_pool/pcie/test_p008.c @@ -62,17 +62,20 @@ check_list_duplicates (PERIPHERAL_VECTOR_LIST *list_one, PERIPHERAL_VECTOR_LIST uint32_t fcount = 0; uint32_t scount = 0; + uint32_t irq_start1, irq_end1; + uint32_t irq_start2, irq_end2; flist_node = list_one; slist_node = list_two; while (flist_node != NULL) { while (slist_node != NULL) { - if ((flist_node->vector.vector_lower_addr == slist_node->vector.vector_lower_addr) && - (flist_node->vector.vector_upper_addr == slist_node->vector.vector_upper_addr) && - (flist_node->vector.vector_data == slist_node->vector.vector_data)) { + irq_start1 = flist_node->vector.vector_irq_base; + irq_end1 = flist_node->vector.vector_irq_base + flist_node->vector.vector_n_irqs - 1; + irq_start2 = slist_node->vector.vector_irq_base; + irq_end2 = slist_node->vector.vector_irq_base + slist_node->vector.vector_n_irqs - 1; + if (!(irq_end1 < irq_start2 || irq_start1 > irq_end2)) return 1; - } slist_node = slist_node->next; scount++; } diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index ed489539..9e3860c3 100755 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -374,6 +374,7 @@ typedef struct { uint32_t vector_data; ///< Base Address of the controller uint32_t vector_control; ///< IRQ to install an ISR uint32_t vector_irq_base; ///< Base IRQ for the vectors in the block + uint32_t vector_n_irqs; ///< Number of irq vectors in the block }PERIPHERAL_VECTOR_BLOCK; typedef struct PERIPHERAL_VECTOR_LIST_STRUCT diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c index eb786a73..040c2594 100644 --- a/val/src/avs_pcie.c +++ b/val/src/avs_pcie.c @@ -201,7 +201,7 @@ val_pcie_execute_tests(uint32_t level, uint32_t num_pe) status |= p005_entry(num_pe); status |= p006_entry(num_pe); status |= p007_entry(num_pe); -//test needs to be changed status |= p008_entry(num_pe); + status |= p008_entry(num_pe); status |= p009_entry(num_pe); status |= p010_entry(num_pe); status |= p011_entry(num_pe); From 43a78af2ef2493c81a7f9019dc70c6aee9dd9351 Mon Sep 17 00:00:00 2001 From: Mahesh Bireddy Date: Wed, 18 Apr 2018 16:03:22 +0530 Subject: [PATCH 2/6] Bug fix test 57: Checks MSI/MSI-X support for all pcie devices (#46) Signed-off-by: Mahesh Bireddy --- test_pool/pcie/test_p007.c | 34 ++++++++++++++++++++-------------- val/include/pal_interface.h | 1 + val/include/val_interface.h | 1 + val/src/avs_pcie.c | 1 - val/src/avs_peripherals.c | 18 +++++++++++++++++- 5 files changed, 39 insertions(+), 16 deletions(-) diff --git a/test_pool/pcie/test_p007.c b/test_pool/pcie/test_p007.c index 8d4e8b00..70c58a2f 100644 --- a/test_pool/pcie/test_p007.c +++ b/test_pool/pcie/test_p007.c @@ -26,35 +26,41 @@ void payload(void) { - uint32_t count = val_peripheral_get_info(NUM_SATA, 0); + uint32_t count = val_peripheral_get_info(NUM_ALL, 0); uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); uint32_t data; + uint32_t dev_type; + uint64_t dev_bdf; + uint32_t status = 0; if (!count){ - val_print(AVS_PRINT_WARN, "\n Skipping because no SATA controller present ", 0); val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); return; } - while (count != 0) { - data = val_peripheral_get_info(SATA_FLAGS, count - 1); + while (count > 0) { + count--; + dev_bdf = val_peripheral_get_info(ANY_BDF, count); + /* Check for pcie device */ + if (!val_peripheral_is_pcie(dev_bdf)) + continue; + + dev_type = val_pcie_get_device_type(dev_bdf); + /* Skipping MSI check for type-1 and type-2 headers */ + if ((!dev_type) || (dev_type > 1)) + continue; + + data = val_peripheral_get_info(ANY_FLAGS, count); if ((data & PER_FLAG_MSI_ENABLED) == 0) { val_print(AVS_STATUS_ERR, "\n MSI should be enabled for a PCIe device ", 0); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + status = 1; break; - } else { - if (val_peripheral_get_info(SATA_GSIV, count - 1)) - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else { - val_print(AVS_STATUS_ERR, "\n IRQ not assigned to the Device ", 0); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - break; - } } - count--; } - + if (!status) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } uint32_t diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index 9e3860c3..a21dcee3 100755 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -363,6 +363,7 @@ typedef struct { }PERIPHERAL_INFO_TABLE; void pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *per_info_table); +uint32_t pal_peripheral_is_pcie(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn); /** @brief MSI(X) controllers info structure diff --git a/val/include/val_interface.h b/val/include/val_interface.h index b8819fee..41bfbed6 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -238,6 +238,7 @@ void val_peripheral_create_info_table(uint64_t *peripheral_info_table); void val_peripheral_free_info_table(void); uint32_t val_peripheral_execute_tests(uint32_t level, uint32_t num_pe); uint64_t val_peripheral_get_info(PERIPHERAL_INFO_e info_type, uint32_t index); +uint32_t val_peripheral_is_pcie(uint32_t bdf); /* Memory Tests APIs */ typedef enum { diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c index 040c2594..ca5233b8 100644 --- a/val/src/avs_pcie.c +++ b/val/src/avs_pcie.c @@ -368,7 +368,6 @@ val_pcie_is_devicedma_64bit(uint32_t bdf) return (pal_pcie_is_devicedma_64bit(seg, bus, dev, func)); } - /** @brief This API returns the bdf of root port @param bdf - PCIe BUS/Device/Function diff --git a/val/src/avs_peripherals.c b/val/src/avs_peripherals.c index 5099b757..65c3e61c 100644 --- a/val/src/avs_peripherals.c +++ b/val/src/avs_peripherals.c @@ -17,7 +17,7 @@ #include "include/sbsa_avs_val.h" #include "include/sbsa_avs_peripherals.h" #include "include/sbsa_avs_common.h" - +#include "include/sbsa_avs_pcie.h" PERIPHERAL_INFO_TABLE *g_peripheral_info_table; @@ -226,3 +226,19 @@ val_peripheral_free_info_table() pal_mem_free((void *)g_peripheral_info_table); } +/** + @brief Check if PCI device is PCI Express capable + 1. Caller - Test Suite + @param bdf - PCIe BUS/Device/Function + @return 1 -> PCIe capable 0 -> no PCIe capable +**/ +uint32_t val_peripheral_is_pcie(uint32_t bdf) +{ + uint32_t seg = PCIE_EXTRACT_BDF_SEG (bdf); + uint32_t bus = PCIE_EXTRACT_BDF_BUS (bdf); + uint32_t dev = PCIE_EXTRACT_BDF_DEV (bdf); + uint32_t func = PCIE_EXTRACT_BDF_FUNC (bdf); + + return pal_peripheral_is_pcie(seg, bus, dev, func); +} + From 5028af81b90f72f4bff29bfa3b4fd0bdd171f180 Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Thu, 3 May 2018 17:57:49 +0530 Subject: [PATCH 3/6] BugFix test #84 UART (#47) Poll wait for UART interrupt. Fix incorrect assumption of current PE index being 0. Signed-off-by: Rajat Goyal --- test_pool/peripherals/test_d003.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/test_pool/peripherals/test_d003.c b/test_pool/peripherals/test_d003.c index 50b2e90e..4dd8239e 100755 --- a/test_pool/peripherals/test_d003.c +++ b/test_pool/peripherals/test_d003.c @@ -70,7 +70,7 @@ uart_enable_txintr() { uint32_t data; - /* unmask TX interrupt bit 5 in */ + /* Enable TX interrupt by setting mask bit[5] in UARTIMSC */ data = uart_reg_read(SBSA_UARTIMSC, WIDTH_BIT32); data = data | (1<<5); uart_reg_write(SBSA_UARTIMSC, WIDTH_BIT32, data); @@ -81,7 +81,7 @@ uart_disable_txintr() { uint32_t data; - /* mask TX interrupt bit 5 in */ + /* Disable TX interrupt by clearing mask bit[5] in UARTIMSC */ data = uart_reg_read(SBSA_UARTIMSC, WIDTH_BIT32); data = data & (~(1<<5)); uart_reg_write(SBSA_UARTIMSC, WIDTH_BIT32, data); @@ -94,9 +94,10 @@ static void isr() { + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); uart_disable_txintr(); val_print(AVS_PRINT_DEBUG, "\n Received interrupt ", 0); - val_set_status(0, RESULT_PASS(g_sbsa_level, TEST_NUM, 0x01)); + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0x01)); val_gic_end_of_interrupt(int_id); } @@ -195,6 +196,7 @@ payload1() { uint32_t count = val_peripheral_get_info(NUM_UART, 0); uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t timeout = TIMEOUT_MEDIUM; if (count == 0) { val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM2, 01)); @@ -212,9 +214,13 @@ payload1() val_gic_install_isr(int_id, isr); uart_enable_txintr(); val_print(g_print_level, "\n Test Message ", 0); - if (IS_RESULT_PENDING(val_get_status(index))) { + + while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); + + if (timeout == 0) { val_print(AVS_PRINT_ERR, "\n Did not receive UART interrupt on %d ", int_id); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM2, 02)); + return; } } else { val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM2, 01)); From 6235681d8025823d74714111d61d14a1203835bc Mon Sep 17 00:00:00 2001 From: Sticklyman1936 Date: Fri, 15 Jun 2018 03:57:46 +0100 Subject: [PATCH 4/6] Update README.md with newest SBSA URL (#48) The latest version of the SBSA documentation has moved. This commit updates the URLs accordingly. --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 2cca4729..155f8746 100644 --- a/README.md +++ b/README.md @@ -5,13 +5,13 @@ ## Server Base System Architecture **Server Base System Architecture** (SBSA) specification specifies a hardware system architecture based on the ARM 64-bit architecture. Server system software such as operating systems, hypervisors, and firmware rely on this. It addresses processing element features and key aspects of system architecture. -For more information, download the [SBSA specification](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029/index.html) +For more information, download the [SBSA specification](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029b/index.html) ## SBSA - Architecture Compliance Suite SBSA **Architecture Compliance Suite** (ACS) is a collection of self-checking, portable C-based tests. -This suite includes a set of examples of the invariant behaviours that are provided by the [SBSA](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029/index.html) specification, so that implementers can verify if these behaviours have been interpreted correctly. +This suite includes a set of examples of the invariant behaviours that are provided by the [SBSA](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029b/index.html) specification, so that implementers can verify if these behaviours have been interpreted correctly. Most of the tests are executed from UEFI Shell by executing the SBSA UEFI shell application. A few tests are executed by running the SBSA ACS Linux application which in turn depends on the SBSA ACS Linux kernel module. From 21bfd61821aeac8f0b4a0fb8e3f1649e23ec6c02 Mon Sep 17 00:00:00 2001 From: sakar arora Date: Tue, 19 Jun 2018 20:49:11 +0530 Subject: [PATCH 5/6] Test 84 bug fix. Pick UART address from SPCR table. (#49) * Test 84 bug fix. Pick UART address from SPCR table. Use val_print_raw to print test message instead of val_print, since former uses UART base address taken from SPCR table, and the latter uses PCD defined UART base address. The GSIV on which ISR is installed in this test is also from SPCR table. With this change test message will always trigger the expected interrupt. Signed-off-by: Prasanth Pulla * test 63: Update failure log Signed-off-by: Sakar Arora --- test_pool/pcie/test_p013.c | 5 +++-- test_pool/peripherals/test_d003.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/test_pool/pcie/test_p013.c b/test_pool/pcie/test_p013.c index 9e08f0a5..9b133893 100644 --- a/test_pool/pcie/test_p013.c +++ b/test_pool/pcie/test_p013.c @@ -60,8 +60,9 @@ payload (void) data = val_pcie_is_devicedma_64bit(dev_bdf); if (data == 0) { if(!val_pcie_is_device_behind_smmu(dev_bdf)) { - val_print (AVS_STATUS_ERR, "\n The device with bdf=0x%x doesn't support 64 bit addressing", dev_bdf); - val_print (AVS_STATUS_ERR, "\n and is not behind SMMU", 0); + val_print (AVS_STATUS_ERR, "\n WARNING:The device with bdf=0x%x doesn't support 64 bit addressing", dev_bdf); + val_print (AVS_STATUS_ERR, "\n and is not behind SMMU. Please install driver for this device and", 0); + val_print (AVS_STATUS_ERR, "\n test again. If driver is already installed, this test has failed.", 0); val_print (AVS_STATUS_ERR, "\n The device is of type = %d", dev_type); val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 1)); return; diff --git a/test_pool/peripherals/test_d003.c b/test_pool/peripherals/test_d003.c index 4dd8239e..66ce970f 100755 --- a/test_pool/peripherals/test_d003.c +++ b/test_pool/peripherals/test_d003.c @@ -213,7 +213,7 @@ payload1() val_set_status(index, RESULT_PENDING(g_sbsa_level, TEST_NUM2)); val_gic_install_isr(int_id, isr); uart_enable_txintr(); - val_print(g_print_level, "\n Test Message ", 0); + val_print_raw(g_print_level, "\n Test Message ", 0); while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index)))); From 8420e2ada060a9fa1541ea7aa6cb051e0af1ece1 Mon Sep 17 00:00:00 2001 From: Sakar Arora Date: Wed, 20 Jun 2018 09:59:55 +0530 Subject: [PATCH 6/6] Update source code version to 1.5 Signed-off-by: Sakar Arora --- README.md | 2 +- linux_app/sbsa-acs-app/include/sbsa_app.h | 2 +- uefi_app/SbsaAvs.h | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index 155f8746..b546feb8 100644 --- a/README.md +++ b/README.md @@ -17,7 +17,7 @@ A few tests are executed by running the SBSA ACS Linux application which in turn ## Release details - - Code Quality: REL v1.4 + - Code Quality: REL v1.5 - The tests are written for version 3.0 of the SBSA specification. - The compliance suite is not a substitute for design verification. - To review the SBSA ACS logs, ARM licensees can contact ARM directly through their partner managers. diff --git a/linux_app/sbsa-acs-app/include/sbsa_app.h b/linux_app/sbsa-acs-app/include/sbsa_app.h index 57929c6d..dd5a0635 100644 --- a/linux_app/sbsa-acs-app/include/sbsa_app.h +++ b/linux_app/sbsa-acs-app/include/sbsa_app.h @@ -20,7 +20,7 @@ #define SBSA_APP_VERSION_MAJOR 1 -#define SBSA_APP_VERSION_MINOR 4 +#define SBSA_APP_VERSION_MINOR 5 #include "sbsa_drv_intf.h" diff --git a/uefi_app/SbsaAvs.h b/uefi_app/SbsaAvs.h index 1664e164..1724a917 100755 --- a/uefi_app/SbsaAvs.h +++ b/uefi_app/SbsaAvs.h @@ -20,7 +20,7 @@ #define SBSA_ACS_MAJOR_VER 1 - #define SBSA_ACS_MINOR_VER 4 + #define SBSA_ACS_MINOR_VER 5 #define G_SBSA_LEVEL 3 #define G_PRINT_LEVEL AVS_PRINT_TEST