From 883527d044ea787843b24f5eda825c360eda979c Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Tue, 15 Sep 2020 21:38:40 +0530 Subject: [PATCH 1/3] ACSv3.0 Release Updates - Added SBSA Level 6 PE Tests. - Added SBSA Level 6 SMMU Tests. - Added New PCIe, Exerciser Tests. - Tests Related to Address Translation Service Rules. - Tests on Peer-to-Peer, ACS Rules. - Added SMMU & Gic-ITS Functional Tests in Exerciser. - Bug Fixes & Test Updates Signed-off-by: Rajat Goyal Co-authored-by: Chetan Rathore Co-authored-by: Gowtham Siddarth Co-authored-by: Sujana M Co-authored-by: Rajat Goyal --- docs/testcase-checklist.md | 38 + linux_app/sbsa-acs-app/include/sbsa_app.h | 4 +- linux_app/sbsa-acs-app/sbsa_app_main.c | 2 +- platform/pal_uefi/SbsaPalLib.inf | 3 + platform/pal_uefi/SbsaPalNistLib.inf | 3 + platform/pal_uefi/include/pal_exerciser.h | 33 +- platform/pal_uefi/include/pal_uefi.h | 10 +- platform/pal_uefi/src/pal_exerciser.c | 45 +- platform/pal_uefi/src/pal_gic.c | 133 +- platform/pal_uefi/src/pal_misc.c | 165 ++- platform/pal_uefi/src/pal_pcie.c | 104 +- platform/pal_uefi/src/pal_pe.c | 14 + platform/pal_uefi/src_gic_its/sbsa_gic_its.c | 561 +++++++++ platform/pal_uefi/src_gic_its/sbsa_gic_its.h | 231 ++++ .../src_gic_its/sbsa_gic_redistributor.c | 173 +++ test_pool/Makefile | 5 - test_pool/exerciser/test_e003.c | 249 ++-- test_pool/exerciser/test_e004.c | 20 +- test_pool/exerciser/test_e005.c | 338 +++++- test_pool/exerciser/test_e007.c | 22 +- test_pool/exerciser/test_e011.c | 315 +++++ test_pool/exerciser/test_e012.c | 285 +++++ test_pool/exerciser/test_e013.c | 401 +++++++ test_pool/exerciser/test_e014.c | 236 ++++ test_pool/exerciser/test_e015.c | 341 ++++++ test_pool/io_virt/test_i003.c | 23 +- test_pool/io_virt/test_i007.c | 90 ++ test_pool/io_virt/test_i008.c | 93 ++ test_pool/io_virt/test_i009.c | 93 ++ test_pool/io_virt/test_i010.c | 129 ++ test_pool/io_virt/test_i011.c | 105 ++ test_pool/io_virt/test_i012.c | 105 ++ test_pool/io_virt/test_i013.c | 94 ++ test_pool/io_virt/test_i014.c | 94 ++ test_pool/io_virt/test_i015.c | 107 ++ test_pool/io_virt/test_i016.c | 105 ++ test_pool/pcie/test_p003.c | 58 +- test_pool/pcie/test_p004.c | 70 +- test_pool/pcie/test_p017.c | 4 +- test_pool/pcie/test_p018.c | 4 +- test_pool/pcie/test_p019.c | 4 +- test_pool/pcie/test_p045.c | 53 +- test_pool/pcie/test_p046.c | 168 +++ test_pool/pcie/test_p047.c | 114 ++ test_pool/pcie/test_p048.c | 152 +++ test_pool/pcie/test_p049.c | 171 +++ test_pool/pcie/test_p050.c | 115 ++ test_pool/pcie/test_p051.c | 204 ++++ test_pool/pcie/test_p052.c | 103 ++ test_pool/pcie/test_p053.c | 143 +++ test_pool/pcie/test_p054.c | 107 ++ test_pool/pcie/test_p055.c | 115 ++ test_pool/pcie/test_p056.c | 164 +++ test_pool/pcie/test_p057.c | 134 +++ test_pool/pe/test_c004.c | 37 +- test_pool/pe/test_c029.c | 63 + test_pool/pe/test_c030.c | 58 + test_pool/pe/test_c031.c | 58 + test_pool/pe/test_c032.c | 58 + test_pool/pe/test_c033.c | 58 + test_pool/pe/test_c034.c | 58 + test_pool/pe/test_c035.c | 58 + test_pool/pe/test_c036.c | 58 + test_pool/pe/test_c037.c | 68 ++ test_pool/pe/test_c038.c | 58 + test_pool/peripherals/test_m001.c | 27 +- test_pool/timer_wd/test_w002.c | 2 +- test_pool/timer_wd/test_w003.c | 98 ++ uefi_app/SbsaAvs.h | 6 +- uefi_app/SbsaAvs.inf | 39 + uefi_app/SbsaAvsMain.c | 22 +- uefi_app/SbsaAvsNist.inf | 39 + val/Makefile | 5 +- val/SbsaValLib.inf | 2 + val/SbsaValNistLib.inf | 2 + val/include/pal_interface.h | 91 +- val/include/sbsa_avs_common.h | 18 + val/include/sbsa_avs_exerciser.h | 5 + val/include/sbsa_avs_gic.h | 4 + val/include/sbsa_avs_gic_support.h | 4 +- val/include/sbsa_avs_iovirt.h | 4 +- val/include/sbsa_avs_memory.h | 10 +- val/include/sbsa_avs_pcie.h | 49 + val/include/sbsa_avs_pcie_spec.h | 56 +- val/include/sbsa_avs_pe.h | 66 +- val/include/sbsa_avs_pgt.h | 47 + val/include/sbsa_avs_smmu.h | 43 +- val/include/sbsa_avs_val.h | 8 +- val/include/sbsa_avs_wd.h | 17 +- val/include/val_interface.h | 13 +- val/src/AArch64/PeRegSysSupport.S | 42 +- val/src/avs_exerciser.c | 27 +- val/src/avs_gic.c | 39 +- val/src/avs_gic_support.c | 129 +- val/src/avs_iovirt.c | 101 +- val/src/avs_memory.c | 31 +- val/src/avs_pcie.c | 153 ++- val/src/avs_pe.c | 88 +- val/src/avs_pgt.c | 321 +++++ val/src/avs_smmu.c | 41 +- val/src/avs_test_infra.c | 106 +- val/src/avs_wd.c | 3 +- val/sys_arch_src/smmu_v3/smmu_reg.h | 185 +++ val/sys_arch_src/smmu_v3/smmu_v3.c | 1068 +++++++++++++++++ val/sys_arch_src/smmu_v3/smmu_v3.h | 140 +++ 105 files changed, 10013 insertions(+), 422 deletions(-) create mode 100644 platform/pal_uefi/src_gic_its/sbsa_gic_its.c create mode 100644 platform/pal_uefi/src_gic_its/sbsa_gic_its.h create mode 100644 platform/pal_uefi/src_gic_its/sbsa_gic_redistributor.c create mode 100644 test_pool/exerciser/test_e011.c create mode 100644 test_pool/exerciser/test_e012.c create mode 100644 test_pool/exerciser/test_e013.c create mode 100644 test_pool/exerciser/test_e014.c create mode 100644 test_pool/exerciser/test_e015.c create mode 100755 test_pool/io_virt/test_i007.c create mode 100644 test_pool/io_virt/test_i008.c create mode 100755 test_pool/io_virt/test_i009.c create mode 100644 test_pool/io_virt/test_i010.c create mode 100644 test_pool/io_virt/test_i011.c create mode 100644 test_pool/io_virt/test_i012.c create mode 100644 test_pool/io_virt/test_i013.c create mode 100644 test_pool/io_virt/test_i014.c create mode 100644 test_pool/io_virt/test_i015.c create mode 100644 test_pool/io_virt/test_i016.c mode change 100755 => 100644 test_pool/pcie/test_p004.c create mode 100644 test_pool/pcie/test_p046.c create mode 100644 test_pool/pcie/test_p047.c create mode 100644 test_pool/pcie/test_p048.c create mode 100644 test_pool/pcie/test_p049.c create mode 100644 test_pool/pcie/test_p050.c create mode 100644 test_pool/pcie/test_p051.c create mode 100644 test_pool/pcie/test_p052.c create mode 100644 test_pool/pcie/test_p053.c create mode 100644 test_pool/pcie/test_p054.c create mode 100644 test_pool/pcie/test_p055.c create mode 100644 test_pool/pcie/test_p056.c create mode 100644 test_pool/pcie/test_p057.c create mode 100755 test_pool/pe/test_c029.c create mode 100755 test_pool/pe/test_c030.c create mode 100755 test_pool/pe/test_c031.c create mode 100755 test_pool/pe/test_c032.c create mode 100644 test_pool/pe/test_c033.c create mode 100644 test_pool/pe/test_c034.c create mode 100644 test_pool/pe/test_c035.c create mode 100644 test_pool/pe/test_c036.c create mode 100644 test_pool/pe/test_c037.c create mode 100644 test_pool/pe/test_c038.c mode change 100644 => 100755 test_pool/peripherals/test_m001.c create mode 100644 test_pool/timer_wd/test_w003.c create mode 100644 val/include/sbsa_avs_pgt.h create mode 100644 val/src/avs_pgt.c create mode 100644 val/sys_arch_src/smmu_v3/smmu_reg.h create mode 100644 val/sys_arch_src/smmu_v3/smmu_v3.c create mode 100644 val/sys_arch_src/smmu_v3/smmu_v3.h diff --git a/docs/testcase-checklist.md b/docs/testcase-checklist.md index 40715ac3..51a8ef59 100644 --- a/docs/testcase-checklist.md +++ b/docs/testcase-checklist.md @@ -37,6 +37,16 @@ | 26 | PE | L5+ | All PEs must implement the Activity Monitors Extension | 4.4.1 | yes | UEFI App | | 27 | PE | L5+ | Where export control allows, all PEs must implement cryptography support for SHA3 and SHA512 | 4.4.1 | yes | UEFI App | | 28 | PE | L3+ | Where PEs implement the scalar vector extension, the vector length maximum must be at least 256 bits | 4.1.1 | yes | UEFI App | +| 29 | PE | L6+ | PEs must implement restrictions on speculation introduced in the Arm v8.5 extensions | 4.5.1 | yes | UEFI App | +| 30 | PE | L6+ | PEs must implement Speculative Store Bypass Safe | 4.5.1 | yes | UEFI App | +| 31 | PE | L6+ | PEs must implement the SB speculation barrier | 4.5.1 | yes | UEFI App | +| 32 | PE | L6+ | PEs must implement the CFP RCTX, DVP RCTX, CPP RCTX instructions | 4.5.1 | yes | UEFI App | +| 33 | PE | L6+ | PEs must provide support for Branch Target Identification | 4.5.1 | yes | UEFI App | +| 34 | PE | L6+ | PEs must protect against timing faults being used to guess page table mappings | 4.5.1 | yes | UEFI App | +| 35 | PE | L6+ | PEs will provide support for enhanced virtualization traps | 4.5.1 | yes | UEFI App | +| 36 | PE | L6+ | All PEs will implement Armv8.5-PMU | 4.5.1 | yes | UEFI App | +| 37 | PE | L6+ | If PEs implement the Scalable Vector Extension (SVE) and the Statistical Profiling Extension (SPE), the PEs will implement Armv8.5-SPE | 4.5.1 | yes | UEFI App | +| 38 | PE | L6+ | Hardware updates to Access flag and Dirty state in translation tables, must be supported | 4.5.1 | yes | UEFI App | | 101 | GICv3 | L2+ | Interrupt controller shall conform to GICv3 specification | 4.3.2 | yes | UEFI App | | 102 | GICv3 | L2+ | If the base server system includes PCI Express then the GICv3 interrupt controller shall implement ITS and LPI | 4.3.2 | yes | UEFI App | | 103 | GIC | L3+ | The GICv3 interrupt controller shall support two Security states | 4.4.4 | yes | UEFI App | @@ -58,6 +68,7 @@ | 301 | Watchdog | L3+ | The watchdog required by level 2 must have both its register frames mapped on to Non-secure address space; this is referred to as the Non-secure watchdog | 4.4.7 | yes | UEFI App | | 302 | Watchdog | L1- | Watchdog Signal 0 is routed as an SPI to the GIC and usable as a EL2 interrupt | 4.2.4 | yes | UEFI App | | 302 | Watchdog | L2+ | Watchdog Signal 0 is routed as an SPIor LPI to the GIC and usable as a EL2 interrupt | 4.3.8 | yes | UEFI App | +| 303 | Watchdog | L5+ | A system compatible with level 5 will implement a generic counter which counts in nanosecond units. ARM strongly recommends that such systems use revision 1 of the generic watchdog | 4.4.4 | yes | UEFI App | | 401 | PCIe | L1+ | Systems must map memory space to PCI Express configuration space, using the PCI Express Enhanced Configuration Access Mechanism (ECAM). Tests should be robust to ARI being implemented | 8.1 | yes | Linux driver | | 402 | PCIe | L1+ | The base address of each ECAM region is discoverable from system firmware data | 8.1 | yes | Linux driver | | 403 | PCIe | L1+ | PEs are able to access the ECAM region | 8.1 | yes | UEFI App | @@ -110,8 +121,25 @@ | 443 | PCIe | L3+ | Root Port must implement ARI forwarding enable as per in E.15.12 section | E.15.12 | yes | UEFI App | 444 | PCIe | L3+ | Root Port Configuration Space must be under same ECAM as the Configuration Space of Endpoints and switches in hierachy that originates from that port | D.1 | yes | UEFI App | 445 | PCIe | L3+ | All Root Port Configuration Space under same Host Bridge must be in same ECAM | D.1 | yes | UEFI App +| 446 | PCIe | L3+ | The Root Port must comply with the byte enable rules and must support 1 byte, 2 byte and 4 byte Configuration read and write requests | D.1 | yes | UEFI App +| 447 | PCIe | L3+ | Must recognize and consume Configuration transactions intended for the Root Port Configurationspace and read/write the appropriate Root Port Configuration register | D.1 | yes | UEFI App +| 448 | PCIe | L3+ | Must recognize transactions received on the primary side of the RP PCI-PCI bridge, targeting non-prefetchable memory spaces of devices and switches that are on the secondary side of the bridge : Where the address falls within the non-prefetchable memory window in the type 1 header registers, the transactions must be forwarded to the secondary side | D.1 | yes | UEFI App +| 449 | PCIe | L3+ | Must recognize transactions received on the primary side of the RP PCI-PCI bridge, targeting prefetchable memory spaces of devices and switches that are on the secondary side of the bridge : Where the address falls within the prefetchable memory window in the type 1 header registers, the transactions must be forwarded to the secondary side | D.1 | yes | UEFI App +| 450 | PCIe | L3+ | Each legacy interrupt SPI must be programmed as level-sensitive in the appropriate GIC_ICFGR | D.6 | yes | UEFI App +| 451 | PCIe | L3+ | For i-EP, the Root Port must provide the ability to do a hot reset of the Endpoint using the Secondary Bus Reset bit in bridge Control Register | E.10 | yes | UEFI App +| 452 | PCIe | L3+ | PCIe ATS capability must be supported if the RCiEP or i-EP has a software visible cache for address translations | E.9 | yes | UEFI App +| 453 | PCIe | L3+ | If the PCIe hierarchy allows peer-to-peer transactions, Root Port must support ACS capability. | D.11 | yes | UEFI App +| 454 | PCIe | L3+ | If the PCIe hierarchy allows peer-to-peer transactions, The root port must support ACS violation error detection, Logging and reporting must be through the usage of AER mechanism | D.11 | yes | UEFI App +| 455 | PCIe | L3+ | If the Root port supports peer-to-peer traffic with other root ports then - If the root port supports Address Translation services and peer-to-peer traffic with other root ports, then it must support ACS direct translated P2P | D.11 | yes | UEFI App +| 456 | PCIe | L3+ | If the i-EP endpoint is capable of sending transactions to a peer endpoint (RCiEP or i-EP endpoint or discrete), then the i-EP root port must have ACS capability | E.12 | yes | UEFI App +| 457 | PCIe | L3+ | ACS capability must be present in the RCiEP or i-EP endpoint functions if the RCiEP or i-EP Endpoint isa multi-function device and supports peer to peer traffic between its functions. | E.12 | yes | UEFI App | 809 | PCIe | L3+ | Configuration transactions indented for secondary bus of root port must be of Type0 | D.1 | yes | Baremetal | 810 | PCIe | L3+ | Configuration transactions indented for subordinate bus range of root port must be of Type1 | D.1 | yes | Baremetal +| 811 | PCIe | L3+ | Check Address Translation Service Functional Check | E.9 | yes | UEFI App +| 812 | PCIe | L3+ | Check Peer-to-Peer ACS Source Validation & Transaction Blocking Functionality | D.11 | yes | UEFI App +| 813 | PCIe | L3+ | Check Peer-to-Peer ACS Redirected Request Validation Functionality | D.11 | yes | UEFI App +| 814 | PCIe | L3+ | PCI Express transactions marked as No_snoop accessing memory must have coherency managed by software . | D.8 | yes | UEFI App | +| 815 | PCIe | L3+ | Transactions that are targeted at devices must be treated as device type access. They must be ordered, must not merge and must not allocate in caches . | D.8.1 | yes | UEFI App | | 504 | Watchdog | L1+ | Watchdog Signal 0 should be able to wakeup at least one PE from various low power states. Based off power states supported - this should be covered for 1 of N condition with some PEs in low power and from the lowest power stated where the Watchdog is ON. | 4.2.6 | yes | UEFI App | | 504 | System counter and generic timer | L1+ | Unless all local PE timers are Always ON, a system timer based on architecture memory mapped generic timer view shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.2.3 | yes | UEFI App | | 505 | System counter and generic timer | L0 | A system specific system timer shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.1.7 | no | UEFI App | @@ -137,6 +165,16 @@ | 704 | SMMU | L3+ | The SMMUv3 spec requires that PCIe root complex must not use the stall model due to potential deadlock. | Appendix H | yes | UEFI App | | 705 | SMMU | L3+ | If SMMUv2 is in use, Each context bank must present a unique physical interrupt to the GIC | 4.4.5 | yes | UEFI App | | 706 | PCIe | L1+ | Each function, or virtual function, that requires hardware I/O virtualization is associated with a SMMU context. The programming of this association is IMPLEMENTATION DEFINED and is expected to be described by system firmware data. | 8.6 | yes | UEFI App | +| 707 | SMMU | L1+ | SMMU Version Check | 8.5.2 | yes | UEFI App | +| 708 | SMMU | L6+ | SMMU must implement support for 16 bit VMID. | 8.5.2 | yes | UEFI App | +| 709 | SMMU | L6+ | SMMU must implement support for 16 bit ASID. | 8.5.2 | yes | UEFI App | +| 710 | SMMU | L6+ | SMMU must support the translation granule sizes supported by the PEs. | 8.5.2 | yes | UEFI App | +| 711 | SMMU | L6+ | if PEs implement ARMv8.2-LVA, the SMMU must support extended virtual addresses | 8.5.2 | yes | UEFI App | +| 712 | SMMU | L3+ | if PEs implement Armv8.2-LPA, it follows that the SMMU must support a 52 bit output size | 8.5.2 | yes | UEFI App | +| 713 | SMMU | L6+ | The SMMU must implement coherent access to in memory structures, queues, and page tables | 8.5.2 | yes | UEFI App | +| 714 | SMMU | L6+ | The SMMU must support hardware translation table update (HTTU) of the Access flag and the Dirty state of the page for AArch64 translation tables. | 8.5.2 | yes | UEFI App | +| 715 | SMMU | L6+ | SMMU will support little endian for translation table walks, and at a minimum must match the endianness support of the PE's. | 8.5.2 | yes | UEFI App | +| 716 | SMMU | L6+ | The DVM capabilities of all DVM receivers (SMMUs and PEs) need to be the same or a superset of the DVM capabilities of all DVM initiators (PEs). Check For TLB Range Invalidation. | 8.5.2 | yes | UEFI App | | 901 | Watchdog | L1+ | Watchdog Signal 1 is available. This may be confirmed in the data base. This may not be possible to exersice as its handling is platform specific | 4.2.4 | yes | Secure FW | | 901 | Watchdog | L3 FW | The Watchdog Signal 1 is routed as a SPI to GIC and usable as an EL3 interrupt, directly targetting a single PE | 4.5.3 | yes | Secure FW | | 902 | System counter and generic timer | L0+ | Must implement at least 56 bits | 4.1.5 | yes | Secure FW | diff --git a/linux_app/sbsa-acs-app/include/sbsa_app.h b/linux_app/sbsa-acs-app/include/sbsa_app.h index 47245686..87e63da9 100644 --- a/linux_app/sbsa-acs-app/include/sbsa_app.h +++ b/linux_app/sbsa-acs-app/include/sbsa_app.h @@ -20,8 +20,8 @@ #define __SBSA_APP_LINUX_H__ -#define SBSA_APP_VERSION_MAJOR 2 -#define SBSA_APP_VERSION_MINOR 5 +#define SBSA_APP_VERSION_MAJOR 3 +#define SBSA_APP_VERSION_MINOR 0 #include "sbsa_drv_intf.h" diff --git a/linux_app/sbsa-acs-app/sbsa_app_main.c b/linux_app/sbsa-acs-app/sbsa_app_main.c index 6a9befa4..5c8f4ebc 100644 --- a/linux_app/sbsa-acs-app/sbsa_app_main.c +++ b/linux_app/sbsa-acs-app/sbsa_app_main.c @@ -49,7 +49,7 @@ void print_help(){ "-v Verbosity of the Prints\n" " 1 shows all prints, 5 shows Errors\n" "-l Level of compliance to be tested for\n" - " As per SBSA spec, 0 to 3\n" + " As per SBSA spec, 0 to 6\n" "--skip Test(s) to be skipped\n" " Refer to section 4 of SBSA_ACS_User_Guide\n" " To skip a module, use Model_ID as mentioned in user guide\n" diff --git a/platform/pal_uefi/SbsaPalLib.inf b/platform/pal_uefi/SbsaPalLib.inf index c03aec31..3d53b27e 100644 --- a/platform/pal_uefi/SbsaPalLib.inf +++ b/platform/pal_uefi/SbsaPalLib.inf @@ -39,8 +39,11 @@ src/pal_peripherals.c src/pal_exerciser.c src/pal_smmu.c + src_gic_its/sbsa_gic_its.c + src_gic_its/sbsa_gic_redistributor.c [Packages] + ArmPkg/ArmPkg.dec MdePkg/MdePkg.dec ShellPkg/ShellPkg.dec EmbeddedPkg/EmbeddedPkg.dec diff --git a/platform/pal_uefi/SbsaPalNistLib.inf b/platform/pal_uefi/SbsaPalNistLib.inf index 2abf2e00..9ba9342b 100644 --- a/platform/pal_uefi/SbsaPalNistLib.inf +++ b/platform/pal_uefi/SbsaPalNistLib.inf @@ -40,8 +40,11 @@ src/pal_exerciser.c src/pal_smmu.c src/pal_nist.c + src_gic_its/sbsa_gic_its.c + src_gic_its/sbsa_gic_redistributor.c [Packages] + ArmPkg/ArmPkg.dec StdLib/StdLib.dec MdePkg/MdePkg.dec ShellPkg/ShellPkg.dec diff --git a/platform/pal_uefi/include/pal_exerciser.h b/platform/pal_uefi/include/pal_exerciser.h index ea245c5c..339aab16 100644 --- a/platform/pal_uefi/include/pal_exerciser.h +++ b/platform/pal_uefi/include/pal_exerciser.h @@ -61,7 +61,10 @@ #define CLR_INTR_MASK 0xFFFFFFFE #define PASID_TLP_STOP_MASK 0xFFFFFFBF -#define PASID_LEN_MASK 0xFFFFFC7F +#define PASID_VAL_MASK ((0x1ul << 20) - 1) +#define PASID_VAL_SHIFT 12 +#define PASID_LEN_SHIFT 7 +#define PASID_LEN_MASK 0x7ul #define DMA_TO_DEVICE_MASK 0xFFFFFFEF /* shift_bit */ @@ -75,6 +78,8 @@ #define PCI_CAP_PTR_OFFSET 8 #define PCIE_CAP_PTR_OFFSET 20 +#define MSI_GENERATION_MASK (1 << 31) + #define NO_SNOOP_START_MASK 0x20 #define NO_SNOOP_STOP_MASK 0xFFFFFFDF #define PCIE_CAP_DIS_MASK 0xFFFEFFFF @@ -107,9 +112,24 @@ typedef enum { DMA_ATTRIBUTES = 0x4, P2P_ATTRIBUTES = 0x5, PASID_ATTRIBUTES = 0x6, - CFG_TXN_ATTRIBUTES = 0x7 + CFG_TXN_ATTRIBUTES = 0x7, + ATS_RES_ATTRIBUTES = 0x8, + TRANSACTION_TYPE = 0x9, + NUM_TRANSACTIONS = 0xA } EXERCISER_PARAM_TYPE; +typedef enum { + TXN_REQ_ID = 0x0, + TXN_ADDR_TYPE = 0x1, +} EXERCISER_TXN_ATTR; + +typedef enum { + AT_UNTRANSLATED = 0x0, + AT_TRANS_REQ = 0x1, + AT_TRANSLATED = 0x2, + AT_RESERVED = 0x3 +} EXERCISER_TXN_ADDR_TYPE; + typedef enum { EXERCISER_RESET = 0x1, EXERCISER_ON = 0x2, @@ -126,10 +146,11 @@ typedef enum { CLEAR_INTR = 0x6, PASID_TLP_START = 0x7, PASID_TLP_STOP = 0x8, - NO_SNOOP_CLEAR_TLP_START = 0x9, - NO_SNOOP_CLEAR_TLP_STOP = 0xa, - START_TXN_MONITOR = 0xb, - STOP_TXN_MONITOR = 0xc + TXN_NO_SNOOP_ENABLE = 0x9, + TXN_NO_SNOOP_DISABLE = 0xa, + START_TXN_MONITOR = 0xb, + STOP_TXN_MONITOR = 0xc, + ATS_TXN_REQ = 0xd } EXERCISER_OPS; typedef enum { diff --git a/platform/pal_uefi/include/pal_uefi.h b/platform/pal_uefi/include/pal_uefi.h index 80dd0880..1d4f5e98 100644 --- a/platform/pal_uefi/include/pal_uefi.h +++ b/platform/pal_uefi/include/pal_uefi.h @@ -100,6 +100,7 @@ typedef enum { typedef struct { UINT32 type; UINT64 base; + UINT32 its_id; /* This its_id is only used in case of ITS Type entry */ }GIC_INFO_ENTRY; /** @@ -351,6 +352,7 @@ typedef struct { } PERIPHERAL_IRQ_MAP; UINT32 pal_pcie_get_root_port_bdf(UINT32 *seg, UINT32 *bus, UINT32 *dev, UINT32 *func); +UINT32 pal_pcie_max_pasid_bits(UINT32 bdf); /* Memory INFO table */ typedef enum { @@ -381,8 +383,12 @@ typedef struct { VOID pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable); VOID *pal_mem_alloc(UINT32 size); -VOID *pal_mem_alloc_coherent(UINT32 bdf, UINT32 size, VOID *pa); -VOID pal_mem_free_coherent(UINT32 bdf, UINT32 size, VOID *va, VOID *pa); +VOID *pal_mem_alloc_cacheable(UINT32 bdf, UINT32 size, VOID **pa); +VOID pal_mem_free_cacheable(UINT32 bdf, UINT32 size, VOID *va, VOID *pa); VOID *pal_mem_virt_to_phys(VOID *va); +VOID *pal_mem_phys_to_virt(UINT64 pa); UINT64 pal_memory_get_unpopulated_addr(UINT64 *addr, UINT32 instance); + +UINT32 pal_pe_get_num(); + #endif diff --git a/platform/pal_uefi/src/pal_exerciser.c b/platform/pal_uefi/src/pal_exerciser.c index 293eafa2..81328484 100644 --- a/platform/pal_uefi/src/pal_exerciser.c +++ b/platform/pal_uefi/src/pal_exerciser.c @@ -103,6 +103,7 @@ pal_exerciser_start_dma_direction ( ) { UINT32 Mask; + UINT32 Status; if (Direction == EDMA_TO_DEVICE) { Mask = DMA_TO_DEVICE_MASK;// DMA direction:to Device @@ -118,7 +119,8 @@ pal_exerciser_start_dma_direction ( pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) | MASK_BIT)); // Reading the Status of the DMA - return (pal_mmio_read(Base + DMASTATUS) & ((MASK_BIT << 1) | MASK_BIT)); + Status = (pal_mmio_read(Base + DMASTATUS) & ((MASK_BIT << 1) | MASK_BIT)); + return Status; } /** @@ -184,7 +186,7 @@ UINT32 pal_exerciser_set_param ( ) { UINT32 Status; - UINT32 Temp; + UINT32 Data; UINT64 Base; Base = pal_exerciser_get_ecsr_base(Bdf,0); @@ -199,19 +201,36 @@ UINT32 pal_exerciser_set_param ( case DMA_ATTRIBUTES: pal_mmio_write(Base + DMA_BUS_ADDR,Value1);// wrting into the DMA Control Register 2 pal_mmio_write(Base + DMA_LEN,Value2);// writing into the DMA Control Register 3 - Temp = pal_mmio_read(Base + DMASTATUS);// Reading the DMA status register - Status = Temp & ((MASK_BIT << 1) | MASK_BIT); + Data = pal_mmio_read(Base + DMASTATUS);// Reading the DMA status register + Status = Data & ((MASK_BIT << 1) | MASK_BIT); return Status; case P2P_ATTRIBUTES: return 0; case PASID_ATTRIBUTES: + Data = pal_mmio_read(Base + DMACTL1); + Data &= ~(PASID_LEN_MASK << PASID_LEN_SHIFT); + Data |= ((Value1 - 16) & PASID_LEN_MASK) << PASID_LEN_SHIFT; + pal_mmio_write(Base + DMACTL1, Data); return 0; case MSIX_ATTRIBUTES: return 0; + case CFG_TXN_ATTRIBUTES: + switch (Value1) { + + case TXN_REQ_ID: + /* Change Requester ID for DMA Transaction.*/ + return 0; + case TXN_ADDR_TYPE: + /* Change Address Type for DMA Transaction.*/ + return 0; + default: + return 1; + } + default: return 1; } @@ -254,6 +273,7 @@ pal_exerciser_get_param ( case P2P_ATTRIBUTES: return 0; case PASID_ATTRIBUTES: + *Value1 = ((pal_mmio_read(Base + DMACTL1) >> PASID_LEN_SHIFT) & PASID_LEN_MASK) + 16; return 0; case MSIX_ATTRIBUTES: *Value1 = pal_mmio_read(Base + MSICTL); @@ -313,6 +333,7 @@ pal_exerciser_ops ( UINT64 Base; UINT32 Ecam; UINT32 CapabilityOffset; + UINT32 data; Base = pal_exerciser_get_ecsr_base(Bdf,0); Ecam = pal_pcie_get_mcfg_ecam(); // Getting the ECAM address @@ -336,9 +357,9 @@ pal_exerciser_ops ( } case GENERATE_MSI: - pal_mmio_write( Base + MSICTL , Param << 1); - pal_mmio_write( Base + MSICTL ,(pal_mmio_read(Base + MSICTL) | MASK_BIT)); - return (pal_mmio_read(Base + MSICTL ) & MASK_BIT); + /* Param is the msi_index */ + pal_mmio_write( Base + MSICTL ,(pal_mmio_read(Base + MSICTL) | (MSI_GENERATION_MASK) | (Param))); + return 0; case GENERATE_L_INTR: pal_mmio_write(Base + INTXCTL , (pal_mmio_read(Base + INTXCTL) | MASK_BIT)); @@ -355,8 +376,10 @@ pal_exerciser_ops ( return 0; case PASID_TLP_START: - pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) | (MASK_BIT << 6))); - pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1) & PASID_LEN_MASK));// pasidlen + data = pal_mmio_read(Base + DMACTL1); + data &= ~(PASID_VAL_MASK << PASID_VAL_SHIFT); + data |= (MASK_BIT << 6) | ((Param & PASID_VAL_MASK) << PASID_VAL_SHIFT); + pal_mmio_write(Base + DMACTL1, data); if (!pal_exerciser_find_pcie_capability(PASID, Bdf, PCIE, &CapabilityOffset)) { pal_mmio_write(Ecam + pal_exerciser_get_pcie_config_offset(Bdf) + CapabilityOffset + PCIE_CAP_CTRL_OFFSET, @@ -375,11 +398,11 @@ pal_exerciser_ops ( } return 1; - case NO_SNOOP_CLEAR_TLP_START: + case TXN_NO_SNOOP_ENABLE: pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1)) | NO_SNOOP_START_MASK);//enabling the NO SNOOP return 0; - case NO_SNOOP_CLEAR_TLP_STOP: + case TXN_NO_SNOOP_DISABLE: pal_mmio_write(Base + DMACTL1, (pal_mmio_read(Base + DMACTL1)) & NO_SNOOP_STOP_MASK);//disabling the NO SNOOP return 0; diff --git a/platform/pal_uefi/src/pal_gic.c b/platform/pal_uefi/src/pal_gic.c index ee327e91..7ce343da 100644 --- a/platform/pal_uefi/src/pal_gic.c +++ b/platform/pal_uefi/src/pal_gic.c @@ -26,16 +26,20 @@ #include #include "include/pal_uefi.h" +#include "include/sbsa_pcie_enum.h" +#include "src_gic_its/sbsa_gic_its.h" static EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *gMadtHdr; EFI_HARDWARE_INTERRUPT_PROTOCOL *gInterrupt = NULL; EFI_HARDWARE_INTERRUPT2_PROTOCOL *gInterrupt2 = NULL; - UINT64 pal_get_madt_ptr(); +GIC_INFO_ENTRY *g_gic_entry = NULL; +GIC_ITS_INFO *g_gic_its_info; + /** @brief Populate information about the GIC sub-system at the input address. In a UEFI-ACPI framework, this information is part of the MADT table. @@ -58,6 +62,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable) } GicEntry = GicTable->gic_info; + g_gic_entry = GicTable->gic_info; GicTable->header.gic_version = 0; GicTable->header.num_gicrd = 0; GicTable->header.num_gicd = 0; @@ -100,14 +105,25 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable) GicEntry->type = ENTRY_TYPE_GICD; GicEntry->base = ((EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE *)Entry)->PhysicalBaseAddress; GicTable->header.gic_version = ((EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE *)Entry)->GicVersion; + sbsa_print(AVS_PRINT_INFO, L"GIC DIS base %x \n", GicEntry->base); GicTable->header.num_gicd++; GicEntry++; } + if (Entry->Type == EFI_ACPI_6_1_GICR) { + GicEntry->type = ENTRY_TYPE_GICRD; + GicEntry->base = ((EFI_ACPI_6_1_GICR_STRUCTURE *)Entry)->DiscoveryRangeBaseAddress; + sbsa_print(AVS_PRINT_INFO, L"GIC RD base Structure %x \n", GicEntry->base); + GicTable->header.num_gicrd++; + GicEntry++; + } + if (Entry->Type == EFI_ACPI_6_1_GIC_ITS) { GicEntry->type = ENTRY_TYPE_GICITS; GicEntry->base = ((EFI_ACPI_6_1_GIC_ITS_STRUCTURE *)Entry)->PhysicalBaseAddress; + GicEntry->its_id = ((EFI_ACPI_6_1_GIC_ITS_STRUCTURE *)Entry)->GicItsId; sbsa_print(AVS_PRINT_INFO, L"GIC ITS base %x \n", GicEntry->base); + sbsa_print(AVS_PRINT_INFO, L"GIC ITS ID%x \n", GicEntry->its_id); GicTable->header.num_its++; GicEntry++; } @@ -239,27 +255,124 @@ pal_gic_free_irq ( } -/* Place holder function. Need to be - * implemented if needed in later releases - */ +UINT32 +pal_gic_its_configure ( + ) +{ + /* + * This function configure the gic to have support for LPIs, + * If supported in the system. + */ + UINT64 mGicRedistributorBase = 0; + EFI_STATUS Status; + + /* Allocate memory to store ITS info */ + g_gic_its_info = (GIC_ITS_INFO *) pal_mem_alloc(1024); + if (!g_gic_its_info) { + sbsa_print(AVS_PRINT_ERR, L"GIC : ITS table memory allocation failed\n", 0); + return 0xFFFFFFFF; + } + + g_gic_its_info->GicNumIts = 0; + + while (g_gic_entry->type != 0xFF) { + if (g_gic_entry->type == ENTRY_TYPE_GICD) { + g_gic_its_info->GicDBase = g_gic_entry->base; + } else if (g_gic_entry->type == ENTRY_TYPE_GICRD) { + mGicRedistributorBase = g_gic_entry->base; + } else if (g_gic_entry->type == ENTRY_TYPE_GICITS) { + g_gic_its_info->GicIts[g_gic_its_info->GicNumIts].Base = g_gic_entry->base; + g_gic_its_info->GicIts[g_gic_its_info->GicNumIts++].ID = g_gic_entry->its_id; + } + g_gic_entry++; + } + + sbsa_print(AVS_PRINT_INFO, L"GIC Distributor base %x \n", g_gic_its_info->GicDBase); + + /* Get Redistributor base for Current CPU. */ + g_gic_its_info->GicRdBase = GetCurrentCpuRDBase(mGicRedistributorBase); + if (g_gic_its_info->GicRdBase == 0) { + sbsa_print(AVS_PRINT_DEBUG, L"Could not get GIC RD Base.\n", 0); + return 0xFFFFFFFF; + } + + sbsa_print(AVS_PRINT_INFO, L"GIC ReDistributor base for Current CPU %x \n", g_gic_its_info->GicRdBase); + + if (ArmGICDSupportsLPIs(g_gic_its_info->GicDBase) && ArmGICRSupportsLPIs(g_gic_its_info->GicRdBase)) { + Status = ArmGicItsConfiguration(); + if (EFI_ERROR(Status)) { + sbsa_print(AVS_PRINT_DEBUG, L"Could Not Configure ITS.\n", 0); + return 0xFFFFFFFF; + } + } else { + sbsa_print(AVS_PRINT_DEBUG, L"LPIs not supported in the system.\n", 0); + return 0xFFFFFFFF; + } + + return 0; +} + +UINT32 +pal_gic_get_max_lpi_id ( + ) +{ + return ArmGicItsGetMaxLpiID(); +} + +UINT32 +getItsIndex ( + IN UINT32 ItsID + ) +{ + UINT32 index; + + for (index=0; indexGicNumIts; index++) + { + if (ItsID == g_gic_its_info->GicIts[index].ID) + return index; + } + return 0xFFFFFFFF; +} + UINT32 pal_gic_request_msi ( - UINT32 bdf, + UINT32 ItsID, + UINT32 DevID, UINT32 IntID, - UINT32 msi_index + UINT32 msi_index, + UINT32 *msi_addr, + UINT32 *msi_data ) { + UINT32 ItsIndex; + + ItsIndex = getItsIndex(ItsID); + if (ItsIndex > g_gic_its_info->GicNumIts) { + sbsa_print(AVS_PRINT_ERR, L"\n Could not find ITS block in MADT", 0); return 0xFFFFFFFF; + } + + ArmGicItsCreateLpiMap(ItsIndex, DevID, IntID, LPI_PRIORITY1); + + *msi_addr = ArmGicItsGetGITSTranslatorAddress(ItsIndex); + *msi_data = IntID; + + return 0; } -/* Place holder function. Need to be - * implemented if needed in later releases - */ VOID pal_gic_free_msi ( - UINT32 bdf, + UINT32 ItsID, + UINT32 DevID, UINT32 IntID, UINT32 msi_index ) { + UINT32 ItsIndex; + + ItsIndex = getItsIndex(ItsID); + if (ItsIndex > g_gic_its_info->GicNumIts) + return ; + + ArmGicItsClearLpiMappings(ItsIndex, DevID, IntID); } diff --git a/platform/pal_uefi/src/pal_misc.c b/platform/pal_uefi/src/pal_misc.c index 21926281..bb220623 100644 --- a/platform/pal_uefi/src/pal_misc.c +++ b/platform/pal_uefi/src/pal_misc.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -20,12 +20,70 @@ #include #include #include +#include #include "include/pal_uefi.h" UINT8 *gSharedMemory; +VOID +pal_mmio_write8(UINT64 addr, UINT8 data) +{ + *(volatile UINT8 *)addr = data; + sbsa_print(AVS_PRINT_INFO, L" pal_mmio_write8 Address = %lx Data = %lx \n", addr, data); + +} + +VOID +pal_mmio_write16(UINT64 addr, UINT16 data) +{ + *(volatile UINT16 *)addr = data; + sbsa_print(AVS_PRINT_INFO, L" pal_mmio_write16 Address = %lx Data = %lx \n", addr, data); + +} + +VOID +pal_mmio_write64(UINT64 addr, UINT64 data) +{ + *(volatile UINT64 *)addr = data; + sbsa_print(AVS_PRINT_INFO, L" pal_mmio_write64 Address = %lx Data = %lx \n", addr, data); + +} + +UINT8 +pal_mmio_read8(UINT64 addr) +{ + UINT8 data; + + data = (*(volatile UINT8 *)addr); + sbsa_print(AVS_PRINT_INFO, L" pal_mmio_read8 Address = %lx Data = %lx \n", addr, data); + + return data; +} + +UINT16 +pal_mmio_read16(UINT64 addr) +{ + UINT16 data; + + data = (*(volatile UINT16 *)addr); + sbsa_print(AVS_PRINT_INFO, L" pal_mmio_read16 Address = %lx Data = %lx \n", addr, data); + + return data; +} + +UINT64 +pal_mmio_read64(UINT64 addr) +{ + UINT64 data; + + data = (*(volatile UINT64 *)addr); + sbsa_print(AVS_PRINT_INFO, L" pal_mmio_read64 Address = %lx Data = %lx \n", addr, data); + + return data; +} + /** @brief Provides a single point of abstraction to read from all Memory Mapped IO address @@ -64,7 +122,6 @@ pal_mmio_write(UINT64 addr, UINT32 data) { sbsa_print(AVS_PRINT_INFO, L" pal_mmio_write Address = %lx Data = %x \n", addr, data); *(volatile UINT32 *)addr = data; - } /** @@ -272,31 +329,73 @@ pal_mem_alloc ( } -/* Place holder function. Need to be - * implemented if needed in later releases +/** + * @brief Allocates requested buffer size in bytes in a contiguous cacheable + * memory and returns the base address of the range. + * + * @param Size allocation size in bytes + * @param Pa Pointer to Physical Addr + * @retval if SUCCESS Pointer to Virtual Addr + * @retval if FAILURE NULL */ VOID * -pal_mem_alloc_coherent ( +pal_mem_alloc_cacheable ( UINT32 Bdf, UINT32 Size, - VOID *Pa + VOID **Pa ) { - return NULL; + EFI_PHYSICAL_ADDRESS Address; + EFI_CPU_ARCH_PROTOCOL *Cpu; + EFI_STATUS Status; + + Status = gBS->AllocatePages (AllocateAnyPages, + EfiBootServicesData, + EFI_SIZE_TO_PAGES(Size), + &Address); + if (EFI_ERROR(Status)) { + sbsa_print(AVS_PRINT_ERR, L"Allocate Pool failed %x \n", Status); + return NULL; + } + + /* Check Whether Cpu architectural protocol is installed */ + Status = gBS->LocateProtocol ( &gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu); + if (EFI_ERROR(Status)) { + sbsa_print(AVS_PRINT_ERR, L"Could not get Cpu Arch Protocol %x \n", Status); + return NULL; + } + + /* Set Memory Attributes */ + Status = Cpu->SetMemoryAttributes (Cpu, + Address, + Size, + EFI_MEMORY_WB); + if (EFI_ERROR (Status)) { + sbsa_print(AVS_PRINT_ERR, L"Could not Set Memory Attribute %x \n", Status); + return NULL; + } + + *Pa = (VOID *)Address; + return (VOID *)Address; } -/* Place holder function. Need to be - * implemented if needed in later releases +/** + * @brief Free the cacheable memory region allocated above + * + * @param Size allocation size in bytes + * @param Va Pointer to Virtual Addr + * @param Pa Pointer to Physical Addr + * @retval None */ VOID -pal_mem_free_coherent ( +pal_mem_free_cacheable ( UINT32 Bdf, UINT32 Size, VOID *Va, VOID *Pa ) { - + gBS->FreePages((EFI_PHYSICAL_ADDRESS)(UINTN)Va, EFI_SIZE_TO_PAGES(Size)); } /* Place holder function. Need to be @@ -310,6 +409,14 @@ pal_mem_virt_to_phys ( return Va; } +VOID * +pal_mem_phys_to_virt ( + UINT64 Pa + ) +{ + return (VOID*)Pa; +} + /** @brief Compares two strings @@ -364,3 +471,39 @@ pal_time_delay_ms ( { return gBS->Stall(MicroSeconds); } + +UINT32 +pal_mem_page_size() +{ + return EFI_PAGE_SIZE; +} + +VOID * +pal_mem_alloc_pages ( + UINT32 NumPages + ) +{ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS PageBase; + + Status = gBS->AllocatePages (AllocateAnyPages, + EfiBootServicesData, + NumPages, + &PageBase); + if (EFI_ERROR(Status)) + { + sbsa_print(AVS_PRINT_ERR, L"Allocate Pages failed %x \n", Status); + return NULL; + } + + return (VOID*)(UINTN)PageBase; +} + +VOID +pal_mem_free_pages( + VOID *PageBase, + UINT32 NumPages + ) +{ + gBS->FreePages((EFI_PHYSICAL_ADDRESS)(UINTN)PageBase, NumPages); +} diff --git a/platform/pal_uefi/src/pal_pcie.c b/platform/pal_uefi/src/pal_pcie.c index 15db5a58..cb7a476d 100644 --- a/platform/pal_uefi/src/pal_pcie.c +++ b/platform/pal_uefi/src/pal_pcie.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -128,7 +128,7 @@ pal_pcie_create_info_table(PCIE_INFO_TABLE *PcieTable) @return success/failure **/ UINT32 -pal_pcie_read_cfg(UINT32 Bdf, UINT32 offset, UINT32 *data) +pal_pcie_io_read_cfg(UINT32 Bdf, UINT32 offset, UINT32 *data) { EFI_STATUS Status; @@ -167,6 +167,89 @@ pal_pcie_read_cfg(UINT32 Bdf, UINT32 offset, UINT32 *data) return PCIE_NO_MAPPING; } +/** + @brief Write 32-bit data to PCIe config space pointed by Bus, + Device, Function and register offset, using UEFI PciIoProtocol + + @param Bdf - BDF value for the device + @param offset - Register offset within a device PCIe config space + @param data - 32 bit value at offset from ECAM base of the device specified by BDF value + @return success/failure +**/ +VOID +pal_pcie_io_write_cfg(UINT32 Bdf, UINT32 offset, UINT32 data) +{ + + EFI_STATUS Status; + EFI_PCI_IO_PROTOCOL *Pci; + UINTN HandleCount; + EFI_HANDLE *HandleBuffer; + UINTN Seg, Bus, Dev, Func; + UINT32 Index; + UINT32 InputSeg, InputBus, InputDev, InputFunc; + + + Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer); + if (EFI_ERROR (Status)) { + sbsa_print(AVS_PRINT_INFO,L"No PCI devices found in the system\n"); + return; + } + + InputSeg = PCIE_EXTRACT_BDF_SEG(Bdf); + InputBus = PCIE_EXTRACT_BDF_BUS(Bdf); + InputDev = PCIE_EXTRACT_BDF_DEV(Bdf); + InputFunc = PCIE_EXTRACT_BDF_FUNC(Bdf); + + for (Index = 0; Index < HandleCount; Index++) { + Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **)&Pci); + if (!EFI_ERROR (Status)) { + Pci->GetLocation (Pci, &Seg, &Bus, &Dev, &Func); + if (InputSeg == Seg && InputBus == Bus && InputDev == Dev && InputFunc == Func) { + Status = Pci->Pci.Write (Pci, EfiPciIoWidthUint32, offset, 1, &data); + } + } + } +} + +/** + @brief This API checks the PCIe Hierarchy Supports P2P + 1. Caller - Test Suite + @return 1 - P2P feature not supported 0 - P2P feature supported +**/ +UINT32 +pal_pcie_p2p_support() +{ + /* + * TODO + * PCIe support for peer to peer + * transactions is platform implementation specific + */ + + return 1; +} + +/** + @brief This API checks the PCIe device P2P support + 1. Caller - Test Suite + @param bdf - PCIe BUS/Device/Function + @return 1 - P2P feature not supported 0 - P2P feature supported +**/ +UINT32 +pal_pcie_dev_p2p_support ( + UINT32 Seg, + UINT32 Bus, + UINT32 Dev, + UINT32 Fn) +{ + /* + * TODO + * Root port or Switch support for peer to peer + * transactions is platform implementation specific + */ + + return 1; +} + /* Place holder function. Need to be * implemented if needed in later releases */ @@ -210,3 +293,20 @@ pal_pcie_get_root_port_bdf ( { return 0; } + +/** + @brief Platform dependent API checks the Address Translation + Cache Support for BDF + 1. Caller - Test Suite + @return 0 - ATC not supported 1 - ATC supported +**/ +UINT32 +pal_pcie_is_cache_present ( + UINT32 Seg, + UINT32 Bus, + UINT32 Dev, + UINT32 Fn + ) +{ + return 0; +} diff --git a/platform/pal_uefi/src/pal_pe.c b/platform/pal_uefi/src/pal_pe.c index 65bba845..0f9823b1 100644 --- a/platform/pal_uefi/src/pal_pe.c +++ b/platform/pal_uefi/src/pal_pe.c @@ -28,6 +28,7 @@ static EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *gMadtHdr; UINT8 *gSecondaryPeStack; UINT64 gMpidrMax; +static UINT32 g_num_pe; #define SIZE_STACK_SECONDARY_PE 0x100 //256 bytes per core #define UPDATE_AFF_MAX(src,dest,mask) ((dest & mask) > (src & mask) ? (dest & mask) : (src & mask)) @@ -53,6 +54,18 @@ PalGetSecondaryStackBase() return (UINT64)gSecondaryPeStack; } +/** + @brief Return the number of PEs in the System. + @param None + @return num_of_pe +**/ +UINT32 +pal_pe_get_num() +{ + + return (UINT32)g_num_pe; +} + /** @brief Returns the Max of each 8-bit Affinity fields in MPIDR. @param None @@ -161,6 +174,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable) }while(Length < TableLength); gMpidrMax = MpidrAff0Max | MpidrAff1Max | MpidrAff2Max | MpidrAff3Max; + g_num_pe = PeTable->header.num_of_pe; pal_pe_data_cache_ops_by_va((UINT64)PeTable, CLEAN_AND_INVALIDATE); pal_pe_data_cache_ops_by_va((UINT64)&gMpidrMax, CLEAN_AND_INVALIDATE); PalAllocateSecondaryStack(gMpidrMax); diff --git a/platform/pal_uefi/src_gic_its/sbsa_gic_its.c b/platform/pal_uefi/src_gic_its/sbsa_gic_its.c new file mode 100644 index 00000000..6683e9a0 --- /dev/null +++ b/platform/pal_uefi/src_gic_its/sbsa_gic_its.c @@ -0,0 +1,561 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "Include/IndustryStandard/Acpi61.h" +#include +#include +#include + +#include "sbsa_gic_its.h" +#include "include/pal_uefi.h" + +UINT64 ArmReadMpidr(VOID); + +extern GIC_ITS_INFO *g_gic_its_info; +static UINT32 cwriter_ptr[10] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +UINT64 +GetCurrentCpuRDBase ( + UINT64 mGicRedistributorBase + ) +{ + UINT32 Index; + UINT64 Mpidr; + UINT32 Affinity, CpuAffinity; + UINT32 GicRedistributorGranularity; + UINT64 GicCpuRedistributorBase; + UINT32 num_pe; + + Mpidr = ArmReadMpidr(); + + CpuAffinity = (Mpidr & (ARM_CORE_AFF0 | ARM_CORE_AFF1 | ARM_CORE_AFF2)) | + ((Mpidr & ARM_CORE_AFF3) >> 8); + + GicRedistributorGranularity = ARM_GICR_CTLR_FRAME_SIZE + + ARM_GICR_SGI_PPI_FRAME_SIZE; + + GicCpuRedistributorBase = mGicRedistributorBase; + num_pe = pal_pe_get_num(); + + for (Index = 0; Index < num_pe; Index++) { + Affinity = MmioRead32(GicCpuRedistributorBase + ARM_GICR_TYPER + NEXT_DW_OFFSET); + if (Affinity == CpuAffinity) { + return GicCpuRedistributorBase; + } + + /* Move to the next GIC Redistributor frame */ + GicCpuRedistributorBase += GicRedistributorGranularity; + } + + return 0; +} + +EFIAPI +UINT32 +ArmGICDSupportsLPIs ( + IN UINT64 GicDistributorBase + ) +{ + return (MmioRead32(GicDistributorBase + ARM_GICD_TYPER) & ARM_GICD_TYPER_LPIS); +} + +EFIAPI +UINT32 +ArmGICRSupportsLPIs ( + IN UINT64 GicRedistributorBase + ) +{ + return (MmioRead32(GicRedistributorBase + ARM_GICR_TYPER) & ARM_GICR_TYPER_PLPIS); +} + +EFIAPI +EFI_STATUS +ArmGicSetItsCommandQueueBase ( + IN UINT32 ItsIndex + ) +{ + /* Allocate Memory for Command queue. Set command queue base in GITS_CBASER. */ + EFI_PHYSICAL_ADDRESS Address; + UINT64 write_value; + UINT64 ItsBase; + + ItsBase = g_gic_its_info->GicIts[ItsIndex].Base; + + Address = (EFI_PHYSICAL_ADDRESS)AllocateAlignedPages(EFI_SIZE_TO_PAGES(NUM_PAGES_8 * SIZE_4KB), SIZE_64KB); + if (!Address) { + DEBUG ((DEBUG_ERROR, "\n ITS : Could Not Allocate Memory For Command Q. Test may not pass.")); + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem((VOID *)Address, (NUM_PAGES_8*SIZE_4KB)); + + g_gic_its_info->GicIts[ItsIndex].CommandQBase = Address; + DEBUG((DEBUG_INFO, "%a Address Allocated : %x\n", __func__, Address)); + + write_value = MmioRead64(ItsBase + ARM_GITS_CBASER) & (~ARM_GITS_CBASER_PA_MASK); + write_value = write_value | (Address & ARM_GITS_CBASER_PA_MASK); + write_value = write_value | ARM_GITS_CBASER_VALID; + MmioWrite64(ItsBase + ARM_GITS_CBASER, write_value); + + return EFI_SUCCESS; +} + +EFIAPI +EFI_STATUS +ArmGicSetItsTables ( + IN UINT32 ItsIndex + ) +{ + UINT32 Pages; + UINT32 TableSize, entry_size; + UINT64 its_baser, its_typer; + UINT8 it, table_type; + UINT64 write_value; + UINT32 DevBits, CIDBits; + EFI_PHYSICAL_ADDRESS Address; + UINT64 ItsBase; + + ItsBase = g_gic_its_info->GicIts[ItsIndex].Base; + + /* Allocate Memory for Table Depending on the Type of the table in GITS_BASER. */ + for(it=0; itGicIts[ItsIndex].ITTBase = Address; + + return EFI_SUCCESS; +} + +EFIAPI +VOID +EnableITS ( + IN UINT64 GicItsBase + ) +{ + /* Set GITS_CTLR.Enable as 1 to enable the ITS */ + UINT32 value; + + value = MmioRead32(GicItsBase + ARM_GITS_CTLR); + MmioWrite32(GicItsBase + ARM_GITS_CTLR, (value | ARM_GITS_CTLR_ENABLE)); +} + +VOID +WriteCmdQMAPD ( + IN UINT32 ItsIndex, + IN UINT64 *CMDQ_BASE, + IN UINT64 DevID, + IN UINT64 ITT_BASE, + IN UINT32 Size, + IN UINT64 Valid + ) +{ + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex]), (UINT64)((DevID << ITS_CMD_SHIFT_DEVID) | ARM_ITS_CMD_MAPD)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 1), (UINT64)(Size)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 2), (UINT64)((Valid << ITS_CMD_SHIFT_VALID) | (ITT_BASE & ITT_PAR_MASK))); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0)); + cwriter_ptr[ItsIndex] = cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR; +} + +VOID +WriteCmdQMAPC ( + IN UINT32 ItsIndex, + IN UINT64 *CMDQ_BASE, + IN UINT32 DevID, + IN UINT32 Clctn_ID, + IN UINT32 RDBase, + IN UINT64 Valid + ) +{ + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] ), (UINT64)(ARM_ITS_CMD_MAPC)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 1), (UINT64)(0x0)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 2), (UINT64)((Valid << ITS_CMD_SHIFT_VALID) | RDBase | Clctn_ID)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0)); + cwriter_ptr[ItsIndex] = cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR; +} + +VOID +WriteCmdQMAPI ( + IN UINT32 ItsIndex, + IN UINT64 *CMDQ_BASE, + IN UINT64 DevID, + IN UINT32 IntID, + IN UINT32 Clctn_ID + ) +{ + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex]), (UINT64)((DevID << ITS_CMD_SHIFT_DEVID) | ARM_ITS_CMD_MAPI)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 1), (UINT64)(IntID)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 2), (UINT64)(Clctn_ID)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0)); + cwriter_ptr[ItsIndex] = cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR; +} + +VOID +WriteCmdQINV ( + IN UINT32 ItsIndex, + IN UINT64 *CMDQ_BASE, + IN UINT64 DevID, + IN UINT32 IntID + ) +{ + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex]), (UINT64)((DevID << ITS_CMD_SHIFT_DEVID) | ARM_ITS_CMD_INV)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 1), (UINT64)(IntID)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 2), (UINT64)(0x0)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0)); + cwriter_ptr[ItsIndex] = cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR; +} + +VOID +WriteCmdQDISCARD ( + IN UINT32 ItsIndex, + IN UINT64 *CMDQ_BASE, + IN UINT64 DevID, + IN UINT32 IntID + ) +{ + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex]), (UINT64)((DevID << ITS_CMD_SHIFT_DEVID) | ARM_ITS_CMD_DISCARD)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 1), (UINT64)(IntID)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 2), (UINT64)(0x0)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0)); + cwriter_ptr[ItsIndex] = cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR; +} + + +VOID +WriteCmdQSYNC ( + IN UINT32 ItsIndex, + IN UINT64 *CMDQ_BASE, + IN UINT32 RDBase + ) +{ + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex]), (UINT64)(ARM_ITS_CMD_SYNC)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 1), (UINT64)(0x0)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 2), (UINT64)(RDBase)); + MmioWrite64((UINT64)(CMDQ_BASE + cwriter_ptr[ItsIndex] + 3), (UINT64)(0x0)); + cwriter_ptr[ItsIndex] = cwriter_ptr[ItsIndex] + ITS_NEXT_CMD_PTR; +} + +VOID +PollTillCommandQueueDone ( + IN UINT32 ItsIndex + ) +{ + UINT32 count; + UINT64 creadr_value; + UINT64 stall_value; + UINT64 cwriter_value; + UINT64 ItsBase; + + count = 0; + ItsBase = g_gic_its_info->GicIts[ItsIndex].Base; + cwriter_value = MmioRead64(ItsBase + ARM_GITS_CWRITER); + creadr_value = MmioRead64(ItsBase + ARM_GITS_CREADR); + + while (creadr_value != cwriter_value) { + /* Check Stall Value */ + stall_value = creadr_value & ARM_GITS_CREADR_STALL; + + if (stall_value) { + /* Retry */ + MmioWrite64((ItsBase + ARM_GITS_CWRITER), + (cwriter_value | ARM_GITS_CWRITER_RETRY) + ); + } + + count++; + if (count > WAIT_ITS_COMMAND_DONE) { + DEBUG ((DEBUG_ERROR, "\n ITS : Command Queue READR not moving, Test may not pass.")); + break; + } + + creadr_value = MmioRead64(ItsBase + ARM_GITS_CREADR); + } + +} + +UINT64 +GetRDBaseFormat ( + IN UINT32 ItsIndex + ) +{ + UINT32 value; + UINT64 ItsBase; + + ItsBase = g_gic_its_info->GicIts[ItsIndex].Base; + + /* Check GITS_TYPER.PTA. + If PTA = 1 then RDBase = Physical Address, + Else RDBase = GICR_TYPER.Processor_Number + */ + value = MmioRead64(ItsBase + ARM_GITS_TYPER); + if (value & ARM_GITS_TYPER_PTA) { + return g_gic_its_info->GicRdBase; + } else { + value = MmioRead64(g_gic_its_info->GicRdBase + ARM_GICR_TYPER); + return (value & ARM_GICR_TYPER_PN_MASK); + } +} + +EFIAPI +VOID +ArmGicItsClearLpiMappings ( + IN UINT32 ItsIndex, + IN UINT32 DevID, + IN UINT32 IntID + ) +{ + UINT64 value; + UINT64 RDBase; + UINT64 ItsBase; + UINT64 ItsCommandBase; + + ItsBase = g_gic_its_info->GicIts[ItsIndex].Base; + ItsCommandBase = g_gic_its_info->GicIts[ItsIndex].CommandQBase; + + /* Clear Config table for LPI=IntID */ + ClearConfigTable(IntID); + + /* Get RDBase Depending on GITS_TYPER.PTA */ + RDBase = GetRDBaseFormat(ItsIndex); + + /* Discard Mappings */ + WriteCmdQDISCARD(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, IntID); + /* ITS SYNC Command */ + WriteCmdQSYNC(ItsIndex, (UINT64 *)(ItsCommandBase), RDBase); + + /* Update the CWRITER Register so that all the commands from Command queue gets executed.*/ + value = ((cwriter_ptr[ItsIndex] * NUM_BYTES_IN_DW)); + MmioWrite64((ItsBase + ARM_GITS_CWRITER), value); + + /* Check CREADR value which ensures Command Queue is processed */ + PollTillCommandQueueDone(ItsIndex); + +} + +EFIAPI +VOID +ArmGicItsCreateLpiMap ( + IN UINT32 ItsIndex, + IN UINT32 DevID, + IN UINT32 IntID, + IN UINT32 Priority + ) +{ + UINT64 value; + UINT64 RDBase; + UINT64 ItsBase; + UINT64 ItsCommandBase; + + ItsBase = g_gic_its_info->GicIts[ItsIndex].Base; + ItsCommandBase = g_gic_its_info->GicIts[ItsIndex].CommandQBase; + + /* Set Config table with enable the LPI = IntID, Priority. */ + SetConfigTable(IntID, Priority); + + /* Enable Redistributor */ + EnableLPIsRD(g_gic_its_info->GicRdBase); + + /* Enable ITS */ + EnableITS(ItsBase); + + /* Get RDBase Depending on GITS_TYPER.PTA */ + RDBase = GetRDBaseFormat(ItsIndex); + + /* Map Device using MAPD */ + WriteCmdQMAPD(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, + g_gic_its_info->GicIts[ItsIndex].ITTBase, + g_gic_its_info->GicIts[ItsIndex].IDBits, 0x1 /*Valid*/); + /* Map Collection using MAPC */ + WriteCmdQMAPC(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, 0x1 /*Clctn_ID*/, RDBase, 0x1 /*Valid*/); + /* Map Interrupt using MAPI */ + WriteCmdQMAPI(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, IntID, 0x1 /*Clctn_ID*/); + /* Invalid Entry */ + WriteCmdQINV(ItsIndex, (UINT64 *)(ItsCommandBase), DevID, IntID); + /* ITS SYNC Command */ + WriteCmdQSYNC(ItsIndex, (UINT64 *)(ItsCommandBase), RDBase); + + /* Update the CWRITER Register so that all the commands from Command queue gets executed.*/ + value = ((cwriter_ptr[ItsIndex] * NUM_BYTES_IN_DW)); + MmioWrite64((ItsBase + ARM_GITS_CWRITER), value); + + /* Check CREADR value which ensures Command Queue is processed */ + PollTillCommandQueueDone(ItsIndex); + +} + +EFIAPI +UINT32 +ArmGicItsGetMaxLpiID ( + ) +{ + UINT32 index; + UINT32 min_idbits = ARM_LPI_MAX_IDBITS; + + if (g_gic_its_info->GicNumIts == 0) + return 0; + + /* Return The Minimum IDBits supported in ITS */ + for (index=0; indexGicNumIts; index++) + { + min_idbits = (min_idbits < g_gic_its_info->GicIts[index].IDBits)? + (min_idbits): + (g_gic_its_info->GicIts[index].IDBits); + } + return ((1 << (min_idbits+1)) - 1); +} + +EFIAPI +UINT64 +ArmGicItsGetGITSTranslatorAddress ( + IN UINT32 ItsIndex + ) +{ + return (g_gic_its_info->GicIts[ItsIndex].Base + ARM_GITS_TRANSLATER); +} + +EFIAPI +EFI_STATUS +SetInitialConfiguration ( + UINT32 ItsIndex + ) +{ + /* Program GIC Redistributor with the Min ID bits supported. */ + UINT32 gicd_typer_idbits, gits_typer_bits; + UINT64 write_value; + UINT64 ItsBase; + + ItsBase = g_gic_its_info->GicIts[ItsIndex].Base; + + gicd_typer_idbits = ARM_GICD_TYPER_IDbits(MmioRead32(g_gic_its_info->GicDBase + ARM_GICD_TYPER)); + gits_typer_bits = ARM_GITS_TYPER_IDbits(MmioRead64(ItsBase + ARM_GITS_TYPER)); + + /* Check least bits implemented is 14 if LPIs are supported. */ + if (GET_MIN(gicd_typer_idbits, gits_typer_bits) < ARM_LPI_MIN_IDBITS) { + return EFI_UNSUPPORTED; + } + + write_value = MmioRead64(g_gic_its_info->GicRdBase + ARM_GICR_PROPBASER); + write_value |= GET_MIN(gicd_typer_idbits, gits_typer_bits); + + g_gic_its_info->GicIts[ItsIndex].IDBits = GET_MIN(gicd_typer_idbits, gits_typer_bits); + + MmioWrite64((g_gic_its_info->GicRdBase + ARM_GICR_PROPBASER), write_value); + + return EFI_SUCCESS; +} + +EFIAPI +EFI_STATUS +ArmGicItsConfiguration ( + ) +{ + EFI_STATUS Status; + UINT32 index; + + for (index=0; indexGicNumIts; index++) + { + /* Set Initial configuration */ + Status = SetInitialConfiguration(index); + if (EFI_ERROR(Status)) { + return Status; + } + } + + /* Configure Redistributor For LPIs */ + Status = ArmGicRedistributorConfigurationForLPI(g_gic_its_info->GicDBase, g_gic_its_info->GicRdBase); + if (EFI_ERROR(Status)) { + return Status; + } + + for (index=0; indexGicNumIts; index++) + { + /* Set Command Queue Base */ + Status = ArmGicSetItsCommandQueueBase(index); + if (EFI_ERROR(Status)) { + return Status; + } + + /* Set Up the ITS tables */ + Status = ArmGicSetItsTables(index); + if (EFI_ERROR(Status)) { + return Status; + } + } + + DEBUG ((DEBUG_INFO, "\n ITS : Info Block ")); + for (index=0; indexGicNumIts; index++) + { + DEBUG ((DEBUG_INFO, "\nGIC ITS Index : %x", index)); + DEBUG ((DEBUG_INFO, "\nGIC ITS ID : %x", g_gic_its_info->GicIts[index].ID)); + DEBUG ((DEBUG_INFO, "\nGIC ITS Base : %x\n\n", g_gic_its_info->GicIts[index].Base)); + } + + return EFI_SUCCESS; +} diff --git a/platform/pal_uefi/src_gic_its/sbsa_gic_its.h b/platform/pal_uefi/src_gic_its/sbsa_gic_its.h new file mode 100644 index 00000000..6e7df1a9 --- /dev/null +++ b/platform/pal_uefi/src_gic_its/sbsa_gic_its.h @@ -0,0 +1,231 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. +**/ + +#ifndef __SBSA_GIC_ITS_H +#define __SBSA_GIC_ITS_H + +#include + +#define ARM_LPI_MINID 8192 +#define ARM_LPI_MIN_IDBITS 14 +#define ARM_LPI_MAX_IDBITS 31 + +#define WAIT_ITS_COMMAND_DONE 10000 + +/* GICv3 specific registers */ + +/* Distributor Interrupt Controller Type Register */ +#define ARM_GICD_TYPER 0x0004 + +/* GICD_TYPER bits */ +#define ARM_GICD_TYPER_LPIS (1 << 17) /* LPIS Enable */ +#define ARM_GICD_TYPER_IDbits(GICD_Typer) ((GICD_Typer >> 19) & 0x1F) /* IDBits implemented */ + +/* GIC Redistributor Control frame */ +#define ARM_GICR_CTLR 0x0000 /* Redistributor Control Register */ +#define ARM_GICR_PROPBASER 0x0070 /* Redistributor Config base Register */ +#define ARM_GICR_PENDBASER 0x0078 /* Redistributor Pending base Register */ + +#define ARM_GICR_CTLR_ENABLE_LPIS (1 << 0) + +/* GICR_TYPER Bits */ +#define NEXT_DW_OFFSET 0x4 /* Used to read Upper 4 Bytes of GICR_TYPER */ +#define ARM_GICR_TYPER_PLPIS (1 << 0) +#define ARM_GICR_TYPER_VLPIS (1 << 1) +#define ARM_GICR_TYPER_PN_MASK (0xFFFF00) + +/* GICR_PROPBASER Bits */ +#define ARM_GICR_PROPBASER_IDbits(Propbaser) (Propbaser & 0x1F) /* IDBits implemented */ +#define PROPBASER_PA_SHIFT 12 +#define PROPBASER_PA_LEN 40 +#define ARM_GICR_PROPBASER_PA_MASK (((1ul << PROPBASER_PA_LEN) - 1) << PROPBASER_PA_SHIFT) + +#define PENDBASER_PA_SHIFT 16 +#define PENDBASER_PA_LEN 36 +#define ARM_GICR_PENDBASER_PA_MASK (((1ul << PENDBASER_PA_LEN) - 1) << PENDBASER_PA_SHIFT) + +/* GIC ITS Register Offset from ITS_CTRL_BASE */ +#define ARM_GITS_CTLR 0x0000 +#define ARM_GITS_IIDR 0x0004 +#define ARM_GITS_TYPER 0x0008 +#define ARM_GITS_CBASER 0x0080 +#define ARM_GITS_CWRITER 0x0088 +#define ARM_GITS_CREADR 0x0090 +#define ARM_GITS_BASER(n) (0x0100 + 8*n) + +#define ARM_GITS_TRANSLATER 0x10040 + +/* GITS_CTLR Register Bits */ +#define ARM_GITS_CTLR_ENABLE (1 << 0) + +/* GITS_BASER Register Bits */ +#define ARM_NUM_GITS_BASER 8 +#define ARM_GITS_BASER_INDIRECT (1ul << 62) +#define ARM_GITS_BASER_GET_TYPE(gits_baser) ((gits_baser >> 56) & 0x7) +#define ARM_GITS_BASER_GET_ENTRY_SIZE(gits_baser) ((gits_baser >> 48) & 0x1F) +#define BASER_PA_SHIFT 12 +#define BASER_PA_LEN 36 +#define ARM_GITS_BASER_PA_MASK (((1ul << BASER_PA_LEN) - 1) << BASER_PA_SHIFT) +#define ARM_GITS_BASER_VALID (1ul << 63) + +#define ARM_GITS_TBL_TYPE_DEVICE 0x1 +#define ARM_GITS_TBL_TYPE_CLCN 0x4 + +/* GITS_TYPER Bits */ +#define ARM_GITS_TYPER_DevBits(its_typer) ((its_typer >> 13) & 0x1F) +#define ARM_GITS_TYPER_CIDBits(its_typer) ((its_typer >> 32) & 0xF) +#define ARM_GITS_TYPER_IDbits(its_typer) ((its_typer >> 8) & 0x1F) +#define ARM_GITS_TYPER_PTA (1 << 19) + +/* GITS_CREADR Bits */ +#define ARM_GITS_CREADR_STALL (1 << 0) + +/* GITS_CWRITER Bits */ +#define ARM_GITS_CWRITER_RETRY (1 << 0) + +/* GITS_CBASER Bits */ +#define ARM_GITS_CBASER_VALID (1ul << 63) +#define CBASER_PA_SHIFT 12 +#define CBASER_PA_LEN 40 +#define ARM_GITS_CBASER_PA_MASK (((1ul << CBASER_PA_LEN) - 1) << CBASER_PA_SHIFT) +#define ITT_PAR_SHIFT 8 +#define ITT_PAR_LEN 44 +#define ITT_PAR_MASK (((1ul << ITT_PAR_LEN) - 1) << ITT_PAR_SHIFT) + +#define GET_CONFIG_TABLE_SIZE_BY_BITS(gicd_idbits, gicr_idbits) ((gicd_idbits < gicr_idbits)?((1 << (gicd_idbits+1)) - 8192):((1 << (gicr_idbits+1)) - 8192)) +#define GET_MIN(a,b) ((a +#include +#include +#include +#include +#include +#include +#include + +#include "Include/IndustryStandard/Acpi61.h" +#include +#include +#include + +#include "sbsa_gic_its.h" + +static UINT64 ConfigBase; + +EFIAPI +EFI_STATUS +ArmGicSetItsConfigTableBase ( + IN UINT64 GicDistributorBase, + IN UINT64 GicRedistributorBase + ) +{ + /* Allocate Memory for Redistributor Configuration Table */ + /* Set GICR_PROPBASER with the Config table base */ + EFI_STATUS Status; + EFI_PHYSICAL_ADDRESS Address; + UINT32 Pages; + UINT32 ConfigTableSize; + UINT64 write_value; + UINT32 gicr_propbaser_idbits; + + /* Get Memory size by reading the GICR_PROPBASER.IDBits field */ + gicr_propbaser_idbits = ARM_GICR_PROPBASER_IDbits(MmioRead64(GicRedistributorBase + ARM_GICR_PROPBASER)); + ConfigTableSize = ((1 << (gicr_propbaser_idbits+1)) - ARM_LPI_MINID); + + Pages = EFI_SIZE_TO_PAGES (ConfigTableSize) + 1; + + Status = gBS->AllocatePages ( + AllocateAnyPages, + EfiBootServicesData, + Pages, + &Address + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "\n ITS : Could Not Allocate Memory For Config Table. Test may not pass.")); + return Status; + } + ZeroMem((VOID *)Address, EFI_PAGES_TO_SIZE(Pages)); + + write_value = MmioRead64(GicRedistributorBase + ARM_GICR_PROPBASER); + write_value = write_value & (~ARM_GICR_PROPBASER_PA_MASK); + write_value = write_value | (Address & ARM_GICR_PROPBASER_PA_MASK); + MmioWrite64(GicRedistributorBase + ARM_GICR_PROPBASER, write_value); + + ConfigBase = Address; + + return EFI_SUCCESS; +} + +EFIAPI +EFI_STATUS +ArmGicSetItsPendingTableBase ( + IN UINT64 GicDistributorBase, + IN UINT64 GicRedistributorBase + ) +{ + /* Allocate Memory for Pending Table for each Redistributor*/ + /* Set GICR_PENDBASER with the Config table base */ + EFI_PHYSICAL_ADDRESS Address; + UINT32 Pages; + UINT32 PendingTableSize; + UINT64 write_value; + UINT32 gicr_propbaser_idbits; + + /* Get Memory size by reading the GICD_TYPER.IDBits, GICR_PROPBASER.IDBits field */ + gicr_propbaser_idbits = ARM_GICR_PROPBASER_IDbits(MmioRead64(GicRedistributorBase + ARM_GICR_PROPBASER)); + PendingTableSize = ((1 << (gicr_propbaser_idbits+1))/8); + + Pages = EFI_SIZE_TO_PAGES (PendingTableSize) + 1; + + Address = (EFI_PHYSICAL_ADDRESS)AllocateAlignedPages(Pages, SIZE_64KB); + if (!Address) { + DEBUG ((DEBUG_ERROR, "\n ITS : Could Not Allocate Memory For Pending Table. Test may not pass.")); + return EFI_OUT_OF_RESOURCES; + } + + ZeroMem((VOID *)Address, EFI_PAGES_TO_SIZE(Pages)); + + write_value = MmioRead64(GicRedistributorBase + ARM_GICR_PENDBASER); + write_value = write_value & (~ARM_GICR_PENDBASER_PA_MASK); + write_value = write_value | (Address & ARM_GICR_PENDBASER_PA_MASK); + MmioWrite64(GicRedistributorBase + ARM_GICR_PENDBASER, write_value); + + return EFI_SUCCESS; +} + +EFIAPI +VOID +ClearConfigTable ( + IN UINT32 IntID + ) +{ + MmioWrite8(ConfigBase + (IntID - ARM_LPI_MINID), LPI_DISABLE); +} + +EFIAPI +VOID +SetConfigTable ( + IN UINT32 IntID, + IN UINT32 Priority + ) +{ + UINT8 value; + + value = (Priority & LPI_PRIORITY_MASK) | LPI_ENABLE; + MmioWrite8(ConfigBase + (IntID - ARM_LPI_MINID), value); +} + +EFIAPI +VOID +EnableLPIsRD ( + IN UINT64 GicRedistributorBase + ) +{ + UINT32 value; + value = MmioRead32(GicRedistributorBase + ARM_GICR_CTLR); + + MmioWrite32(GicRedistributorBase + ARM_GICR_CTLR, + (value | ARM_GICR_CTLR_ENABLE_LPIS)); +} + +EFIAPI +EFI_STATUS +ArmGicRedistributorConfigurationForLPI ( + IN UINT64 GicDistributorBase, + IN UINT64 GicRedistributorBase + ) +{ + EFI_STATUS Status; + /* Set Configuration Table Base */ + Status = ArmGicSetItsConfigTableBase(GicDistributorBase, GicRedistributorBase); + if (EFI_ERROR(Status)) { + return Status; + } + + /* Set Pending Table Base For Each Redistributor */ + Status = ArmGicSetItsPendingTableBase(GicDistributorBase, GicRedistributorBase); + if (EFI_ERROR(Status)) { + return Status; + } + + return Status; +} diff --git a/test_pool/Makefile b/test_pool/Makefile index 08996191..68e47428 100644 --- a/test_pool/Makefile +++ b/test_pool/Makefile @@ -35,11 +35,6 @@ sbsa_acs_test-objs += $(TEST_POOL)/pcie/test_p001.o \ $(TEST_POOL)/pcie/test_p015.o $(TEST_POOL)/pcie/test_p016.o \ $(TEST_POOL)/pcie/test_p017.o $(TEST_POOL)/pcie/test_p018.o \ $(TEST_POOL)/pcie/test_p019.o \ - $(TEST_POOL)/exerciser/test_e001.o $(TEST_POOL)/exerciser/test_e002.o \ - $(TEST_POOL)/exerciser/test_e003.o $(TEST_POOL)/exerciser/test_e004.o \ - $(TEST_POOL)/exerciser/test_e005.o $(TEST_POOL)/exerciser/test_e006.o \ - $(TEST_POOL)/exerciser/test_e007.o $(TEST_POOL)/exerciser/test_e008.o \ - $(TEST_POOL)/exerciser/test_e009.o $(TEST_POOL)/exerciser/test_e010.o \ ccflags-y=-I$(PWD)/$(ACS_DIR)/.. -I$(PWD)/$(ACS_DIR)/val/ -I$(PWD)/$(ACS_DIR)/ -DTARGET_LINUX -Wall -Werror diff --git a/test_pool/exerciser/test_e003.c b/test_pool/exerciser/test_e003.c index 9271b2e5..13e0d7f8 100644 --- a/test_pool/exerciser/test_e003.c +++ b/test_pool/exerciser/test_e003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,7 +18,10 @@ #include "val/include/sbsa_avs_val.h" #include "val/include/val_interface.h" +#include "val/include/sbsa_avs_pe.h" #include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pgt.h" +#include "val/include/sbsa_avs_iovirt.h" #include "val/include/sbsa_avs_memory.h" #include "val/include/sbsa_avs_pcie_enumeration.h" #include "val/include/sbsa_avs_pcie.h" @@ -27,7 +30,7 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 3) #define TEST_DESC "PCIe Address translation check " -#define TEST_DATA_BLK_SIZE (16*1024) +#define TEST_DATA_NUM_PAGES 4 #define TEST_DATA 0xDE static @@ -46,106 +49,218 @@ write_test_data(void *buf, uint32_t size) static void -payload(void) +clear_dram_buf(void *buf, uint32_t size) { + uint32_t index; + + for (index = 0; index < size; index++) { + *((char8_t *)buf + index) = 0; + } + + val_data_cache_ops_by_va((addr_t)buf, CLEAN_AND_INVALIDATE); +} + +static +void +payload(void) +{ uint32_t pe_index; uint32_t dma_len; - uint32_t base_index; uint32_t instance; uint32_t e_bdf; - uint32_t smmu_index; - void *dram_buf1_virt; - void *dram_buf1_phys; - void *dram_buf2_virt; - void *dram_buf2_phys; - void *dram_buf2_iova; - - dram_buf1_phys = NULL; + void *dram_buf_in_virt; + void *dram_buf_out_virt; + uint64_t dram_buf_in_phys; + uint64_t dram_buf_out_phys; + uint64_t dram_buf_in_iova; + uint64_t dram_buf_out_iova; + uint32_t num_exercisers, num_smmus; + uint32_t device_id, its_id; + uint32_t page_size = val_memory_page_size(); + memory_region_descriptor_t mem_desc_array[2], *mem_desc; + pgt_descriptor_t pgt_desc; + smmu_master_attributes_t master; + uint64_t ttbr; + uint32_t test_data_blk_size = page_size * TEST_DATA_NUM_PAGES; + uint64_t *pgt_base_array; + + num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); + + /* Initialize DMA master and memory descriptors */ + val_memory_set(&master, sizeof(master), 0); + val_memory_set(mem_desc_array, sizeof(mem_desc_array), 0); + mem_desc = &mem_desc_array[0]; + dram_buf_in_phys = 0; pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - - while (instance-- != 0) { + num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + /* Allocate an array to store base addresses of page tables allocated for + * all exercisers + */ + pgt_base_array = val_memory_alloc(sizeof(uint64_t) * num_exercisers); + if (!pgt_base_array) { + val_print(AVS_PRINT_ERR, "\n mem alloc failure %x", 03); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + val_memory_set(pgt_base_array, sizeof(uint64_t) * num_exercisers, 0); + + /* Allocate a buffer to perform DMA tests on */ + dram_buf_in_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES); + if (!dram_buf_in_virt) { + val_print(AVS_PRINT_ERR, "\n Cacheable mem alloc failure %x", 02); + val_memory_free(pgt_base_array); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } - /* if init fail moves to next exerciser */ - if (val_exerciser_init(instance)) - continue; + /* Set the virtual and physical addresses for test buffers */ + dram_buf_in_phys = (uint64_t)val_memory_virt_to_phys(dram_buf_in_virt); + dram_buf_out_virt = dram_buf_in_virt + (test_data_blk_size / 2); + dram_buf_out_phys = dram_buf_in_phys + (test_data_blk_size / 2); + dma_len = test_data_blk_size / 2; + + /* Get translation attributes via TCR and translation table base via TTBR */ + if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) + goto test_fail; + if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) + goto test_fail; + pgt_desc.pgt_base = (ttbr & AARCH64_TTBR_ADDR_MASK); + pgt_desc.mair = val_pe_reg_read(MAIR_ELx); + pgt_desc.stage = PGT_STAGE1; + + /* Get memory attributes of the test buffer, we'll use the same attibutes to create + * our own page table later. + */ + if (val_pgt_get_attributes(pgt_desc, (uint64_t)dram_buf_in_virt, &mem_desc->attributes)) + goto test_fail; + + /* Enable all SMMUs */ + for (instance = 0; instance < num_smmus; ++instance) + val_smmu_enable(instance); + + for (instance = 0; instance < num_exercisers; ++instance) { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; /* Get exerciser bdf */ e_bdf = val_exerciser_get_bdf(instance); /* Get SMMU node index for this exerciser instance */ - smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + + clear_dram_buf(dram_buf_in_virt, test_data_blk_size); + + dram_buf_in_iova = dram_buf_in_phys; + dram_buf_out_iova = dram_buf_out_phys; + if (master.smmu_index != AVS_INVALID_INDEX && + val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, master.smmu_index) == 3) { + if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf), + PCIE_EXTRACT_BDF_SEG(e_bdf), + &device_id, &master.streamid, + &its_id)) + continue; + + /* Each exerciser instance accesses a unique IOVA, which, because of SMMU translations, + * will point to the same physical address. We create the requisite page tables and + * configure the SMMU for each exerciser as such. + */ - for (base_index = 0; base_index < TEST_DDR_REGION_CNT; base_index++) { + mem_desc->virtual_address = (uint64_t)dram_buf_in_virt + instance * test_data_blk_size; + mem_desc->physical_address = dram_buf_in_phys; + mem_desc->length = test_data_blk_size; + mem_desc->attributes |= PGT_STAGE1_AP_RW; - /* Get a non-cacheable DDR Buffer of size test data block size */ - dram_buf1_virt = val_memory_alloc(TEST_DATA_BLK_SIZE); - if (!dram_buf1_virt) { - val_print(AVS_PRINT_ERR, "\n Cacheable mem alloc failure %x", 02); - val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; - } + /* Need to know input and output address sizes before creating page table */ + if ((pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index)) == 0) + goto test_fail; - /* Set the virtual addresses for test buffers */ - dram_buf1_phys = val_memory_virt_to_phys(dram_buf1_virt); - dram_buf2_virt = dram_buf1_virt + (TEST_DATA_BLK_SIZE / 2); - dram_buf2_phys = dram_buf1_phys + (TEST_DATA_BLK_SIZE / 2); - dma_len = TEST_DATA_BLK_SIZE / 2; - if (smmu_index == AVS_INVALID_INDEX) { - dram_buf2_iova = dram_buf2_phys; - } else { - dram_buf2_iova = (void *)val_smmu_pa2iova(smmu_index, (uint64_t)dram_buf2_phys); - } + if ((pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index)) == 0) + goto test_fail; - /* Initialize the sender buffer with test specific data */ - write_test_data(dram_buf1_virt, dma_len); + if (val_pgt_create(mem_desc, &pgt_desc)) + goto test_fail; - /* Program Exerciser DMA controller with sender buffer information. - * As exerciser is not behind SMMU, IOVA is same as PA. Use PA to - * program the exerciser DMA. - */ + pgt_base_array[instance] = pgt_desc.pgt_base; - if (val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance)) { - val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + /* Configure the SMMU tables for this exerciser to use this page table for VA to PA translations*/ + if (val_smmu_map(master, pgt_desc)) + { + val_print(AVS_PRINT_ERR, "\n SMMU mapping failed (%x) ", e_bdf); goto test_fail; } - if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { - val_print(AVS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); - goto test_fail; - } + dram_buf_in_iova = mem_desc->virtual_address; + dram_buf_out_iova = dram_buf_in_iova + (test_data_blk_size / 2); + } - /* READ Back from Exerciser to validate above DMA write */ - if (val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf2_iova, dma_len, instance)) { - val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); - goto test_fail; - } + /* Initialize the sender buffer with test specific data */ + write_test_data(dram_buf_in_virt, dma_len); - if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { - val_print(AVS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); - goto test_fail; - } + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } - if (val_memory_compare(dram_buf1_virt, dram_buf2_virt, dma_len)) { - val_print(AVS_PRINT_ERR, "\n Data Comparasion failure for Exerciser %4x", instance); - goto test_fail; - } + /* Trigger DMA from input buffer to exerciser memory */ + if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); + goto test_fail; + } + + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } - /* Return the buffer to the heap manager */ - val_memory_free(dram_buf1_virt); + /* Trigger DMA from exerciser memory to output buffer*/ + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); + goto test_fail; } + if (val_memory_compare(dram_buf_in_virt, dram_buf_out_virt, dma_len)) { + val_print(AVS_PRINT_ERR, "\n Data Comparasion failure for Exerciser %4x", instance); + goto test_fail; + } + clear_dram_buf(dram_buf_in_virt, test_data_blk_size); } val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - return; + goto test_clean; test_fail: val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - val_memory_free(dram_buf1_virt); - return; +test_clean: + /* Return the pages to the heap manager */ + val_memory_free_pages(dram_buf_in_virt, TEST_DATA_NUM_PAGES); + + /* Remove all address mappings for each exerciser */ + for (instance = 0; instance < num_exercisers; ++instance) + { + e_bdf = val_exerciser_get_bdf(instance); + master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf), + PCIE_EXTRACT_BDF_SEG(e_bdf), + &device_id, &master.streamid, + &its_id)) + continue; + val_smmu_unmap(master); + if (pgt_base_array[instance] != 0) { + pgt_desc.pgt_base = pgt_base_array[instance]; + val_pgt_destroy(pgt_desc); + } + } + + /* Disable all SMMUs */ + for (instance = 0; instance < num_smmus; ++instance) + val_smmu_disable(instance); + + val_memory_free(pgt_base_array); } diff --git a/test_pool/exerciser/test_e004.c b/test_pool/exerciser/test_e004.c index d701ef9d..168cfd3a 100644 --- a/test_pool/exerciser/test_e004.c +++ b/test_pool/exerciser/test_e004.c @@ -19,6 +19,8 @@ #include "val/include/sbsa_avs_pcie_enumeration.h" #include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_iovirt.h" +#include "val/include/sbsa_avs_smmu.h" #include "val/include/sbsa_avs_memory.h" #include "val/include/sbsa_avs_exerciser.h" @@ -36,7 +38,7 @@ intr_handler(void) /* Clear the interrupt pending state */ irq_pending = 0; - val_print(AVS_PRINT_DEBUG, "\n Received MSI interrupt %x", lpi_int_id); + val_print(AVS_PRINT_INFO, "\n Received MSI interrupt %x ", lpi_int_id); val_gic_end_of_interrupt(lpi_int_id); return; } @@ -53,6 +55,7 @@ payload (void) uint32_t status; uint32_t instance; uint32_t num_cards; + uint32_t num_smmus; uint32_t msi_index = 0; if(!count) { @@ -63,7 +66,17 @@ payload (void) /* Read the number of excerciser cards */ num_cards = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); - for (instance = 0; instance < num_cards; num_cards++) { + /* Disable all SMMUs */ + num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); + for (instance = 0; instance < num_smmus; ++instance) + val_smmu_disable(instance); + + for (instance = 0; instance < num_cards; instance++) + { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); @@ -95,7 +108,8 @@ payload (void) while ((--timeout > 0) && irq_pending); if (timeout == 0) { - val_print(AVS_PRINT_ERR, "\n Interrupt trigger failed for Interrupt : 0x%x ", lpi_int_id); + val_print(AVS_PRINT_ERR, "\n Interrupt trigger failed for : 0x%x, ", lpi_int_id); + val_print(AVS_PRINT_ERR, "BDF : 0x%x ", e_bdf); val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); val_gic_free_msi(e_bdf, lpi_int_id, msi_index); return; diff --git a/test_pool/exerciser/test_e005.c b/test_pool/exerciser/test_e005.c index ec144c7f..5d33af01 100644 --- a/test_pool/exerciser/test_e005.c +++ b/test_pool/exerciser/test_e005.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,7 +18,10 @@ #include "val/include/sbsa_avs_val.h" #include "val/include/val_interface.h" +#include "val/include/sbsa_avs_pe.h" #include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pgt.h" +#include "val/include/sbsa_avs_iovirt.h" #include "val/include/sbsa_avs_pcie_enumeration.h" #include "val/include/sbsa_avs_pcie.h" #include "val/include/sbsa_avs_memory.h" @@ -27,11 +30,17 @@ #define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 5) #define TEST_DESC "Generate PASID PCIe transactions " -#define TEST_PASID_VALUE ((1 << 16) + (1 << 12)) -#define TEST_DATA_BLK_SIZE 512 +#define TEST_DATA_NUM_PAGES 2 #define TEST_DATA 0xDE -void write_source_buf_data(void *buf, uint32_t size) +#define MIN_PASID_BITS 16 +#define MAX_PASID_BITS 20 +#define TEST_PASID1 (0x1ul << (MIN_PASID_BITS - 1)) + (0x1ull << 8) +#define TEST_PASID2 (0x1ul << (MIN_PASID_BITS - 1)) + (0x2ull << 8) + +static +void +write_test_data(void *buf, uint32_t size) { uint32_t index; @@ -40,8 +49,31 @@ void write_source_buf_data(void *buf, uint32_t size) *((char8_t *)buf + index) = TEST_DATA; } + val_data_cache_ops_by_va((addr_t)buf, CLEAN_AND_INVALIDATE); +} + +static +void +clear_dram_buf(void *buf, uint32_t size) +{ + + uint32_t index; + + for (index = 0; index < size; index++) { + *((char8_t *)buf + index) = 0; + } + + val_data_cache_ops_by_va((addr_t)buf, CLEAN_AND_INVALIDATE); } +/* + * For each exerciser behind an SMMU, + * Create a mapping of 1 IOVA region to 2 PA regions, via SMMU + * Each of the 2 mappings is identified by a distinct PASID + * Confiugure exerciser DMA engine to access IOVA region base. + * Configure exerciser to execute DMA with TEST_PASID1 in transactions, Accesses must PA region 1. + * Configure exerciser to execute DMA with TEST_PASID2 in transactions, Accesses must PA region 2. + */ static void payload(void) { @@ -49,125 +81,307 @@ payload(void) uint32_t instance; uint64_t e_bdf; uint32_t e_valid_cnt; - uint32_t e_pasid; - uint64_t e_pasid_support; uint32_t dma_len; - uint32_t smmu_index; - void *src_buf_virt; - void *src_buf_phys; - void *dest_buf_virt; - void *dest_buf_phys; - + uint32_t smmu_ssid_bits; + void *dram_buf_base_virt; + void *dram_buf_pasid1_in_virt; + void *dram_buf_pasid2_in_virt; + void *dram_buf_pasid1_out_virt; + void *dram_buf_pasid2_out_virt; + uint64_t dram_buf_pasid1_base_phys; + uint64_t dram_buf_pasid2_base_phys; + uint64_t dram_buf_in_iova; + uint64_t dram_buf_out_iova; + uint32_t device_id, its_id; + uint32_t page_size = val_memory_page_size(); + uint32_t test_data_blk_size = page_size * TEST_DATA_NUM_PAGES; + memory_region_descriptor_t mem_desc_array[2], *mem_desc; + smmu_master_attributes_t master = {0, 0, 0, 0, 0}; + pgt_descriptor_t pgt_desc; + uint64_t ttbr, exerciser_ssid_bits; + uint64_t pgt_base_pasid1 = 0; + uint64_t pgt_base_pasid2 = 0; + + /* Initialize DMA master and memory descriptors */ + val_memory_set(&master, sizeof(master), 0); + val_memory_set(mem_desc_array, sizeof(mem_desc_array), 0); + mem_desc = &mem_desc_array[0]; e_valid_cnt = 0; - src_buf_virt = NULL; pe_index = val_pe_get_index_mpid (val_pe_get_mpid()); + + /* Allocate 2 test buffers, one for each pasid */ + dram_buf_base_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES * 2); + if (!dram_buf_base_virt) { + val_print(AVS_PRINT_ERR, "\n Cacheable mem alloc failure %x", 02); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Setup virtual and physical addresses for test buffers for each pasid */ + dram_buf_pasid1_in_virt = dram_buf_base_virt; + dram_buf_pasid2_in_virt = dram_buf_base_virt + test_data_blk_size; + dram_buf_pasid1_out_virt = dram_buf_pasid1_in_virt + test_data_blk_size/2; + dram_buf_pasid2_out_virt = dram_buf_pasid2_in_virt + test_data_blk_size/2; + + dram_buf_pasid1_base_phys = (uint64_t)val_memory_virt_to_phys(dram_buf_pasid1_in_virt); + dram_buf_pasid2_base_phys = (uint64_t)val_memory_virt_to_phys(dram_buf_pasid2_in_virt); + + dma_len = test_data_blk_size/2; + + /* Get translation attributes via TCR and translation table base via TTBR */ + if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) + { + val_print(AVS_PRINT_ERR, "\n TCR read failure %x", 03); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) + { + val_print(AVS_PRINT_ERR, "\n TTBR0 read failure %x", 04); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + pgt_desc.pgt_base = (ttbr & AARCH64_TTBR_ADDR_MASK); + pgt_desc.mair = val_pe_reg_read(MAIR_ELx); + pgt_desc.stage = PGT_STAGE1; + + /* Get memory attributes of the test buffer, we'll use the same attibutes to create + * our own page table later. + */ + if (val_pgt_get_attributes(pgt_desc, (uint64_t)dram_buf_base_virt, &mem_desc->attributes)) + goto test_fail; + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); while (instance-- != 0) { + clear_dram_buf(dram_buf_base_virt, test_data_blk_size * 2); + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; /* Get exerciser bdf */ e_bdf = val_exerciser_get_bdf(instance); - /* Check if exerciser and it's root port have PASID TLP Prefix support */ - val_exerciser_get_param(PASID_ATTRIBUTES, &e_bdf, &e_pasid_support, instance); - if(e_pasid_support == 0) { + /* Find SMMU node index for this pcie endpoint */ + master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + if (master.smmu_index == AVS_INVALID_INDEX) { continue; } + /* Check if SMMU supports substreamid (ssid), and number of ssid bits supported*/ + smmu_ssid_bits = val_smmu_get_info(SMMU_SSID_BITS, master.smmu_index); + + if (smmu_ssid_bits < MIN_PASID_BITS || smmu_ssid_bits > MAX_PASID_BITS) + { + val_print(AVS_PRINT_ERR, "SMMU substreamid support error %d\n", smmu_ssid_bits); + goto test_fail; + } + + /* We just want to test minimum pasid size (16-bits) functionality. + * Make sure exerciser supports at least that + */ + val_exerciser_get_param(PASID_ATTRIBUTES, &exerciser_ssid_bits, NULL, instance); + if (exerciser_ssid_bits < MIN_PASID_BITS) + { + val_print(AVS_PRINT_ERR, "exerciser substreamid support error %d\n", exerciser_ssid_bits); + goto test_fail; + } + + master.ssid_bits = MIN_PASID_BITS; + + /* Need to know input and output address sizes before creating page table */ + if ((pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index)) == 0) + goto test_fail; + + if ((pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index)) == 0) + goto test_fail; + + val_smmu_enable(master.smmu_index); + /* Increment the exerciser count with pasid support */ e_valid_cnt++; - /* Find SMMU node index for this pcie endpoint */ - smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); - if (smmu_index == AVS_INVALID_INDEX) { + if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf), + PCIE_EXTRACT_BDF_SEG(e_bdf), + &device_id, &master.streamid, + &its_id)) continue; - } - /* If the smmu already support the requested pasid, - * return success. Else, PAL layer has to set up the - * corresponding page tables correctlyi and then return - * to support e_pasid. Upon success return zero, else one. + /* Intent is to do DMA with PASID1 and PASID2 sequentially, with same IOVA. + * SMMU does virtual to physical address translation using + * tables configured for each pasid. + * Here we setup memory descriptor for creating page tables for pasid1. */ - e_pasid = TEST_PASID_VALUE; - if(val_smmu_create_pasid_entry(smmu_index, e_pasid)) { - val_print(AVS_PRINT_ERR, "\n Exerciser %x smmu PASID enable error", instance); - val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; + mem_desc->virtual_address = (uint64_t)dram_buf_base_virt; + mem_desc->physical_address = dram_buf_pasid1_base_phys; + mem_desc->length = test_data_blk_size; + mem_desc->attributes |= PGT_STAGE1_AP_RW; + + if (val_pgt_create(mem_desc, &pgt_desc)) + goto test_fail; + + pgt_base_pasid1 = pgt_desc.pgt_base; + + master.substreamid = TEST_PASID1; + if (val_smmu_map(master, pgt_desc)) + { + val_print(AVS_PRINT_ERR, "\n SMMU mapping failed (%d) ", master.substreamid); + goto test_fail; } - /* Program exerciser and it's root port to start sending TLPs + dram_buf_in_iova = mem_desc->virtual_address; + dram_buf_out_iova = dram_buf_in_iova + (test_data_blk_size / 2); + + write_test_data(dram_buf_pasid1_in_virt, dma_len); + + /* Program exerciser to start sending TLPs * with PASID TLP Prefixes. This includes setting PASID Enable bit * in exerciser PASID Control register and the implementation specific * PASID Enable bit of the Root Port. */ - if(val_exerciser_ops(PASID_TLP_START, (uint64_t)&e_pasid, instance)) { + if (val_exerciser_ops(PASID_TLP_START, (uint64_t)master.substreamid, instance)) { val_print(AVS_PRINT_ERR, "\n Exerciser %x PASID TLP Prefix enable error", instance); - val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; + goto test_fail; } - /* Get a Caheable DDR Buffer of size test data block size */ - src_buf_virt = val_memory_alloc(TEST_DATA_BLK_SIZE); - if (!src_buf_virt) { - val_print(AVS_PRINT_ERR, "\n Cacheable mem alloc failure %x", 02); - val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - return; + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; } - /* Set the virtual addresses for test buffers */ - src_buf_phys = val_memory_virt_to_phys(src_buf_virt); - dest_buf_virt = src_buf_virt + (TEST_DATA_BLK_SIZE / 2); - dest_buf_phys = src_buf_phys + (TEST_DATA_BLK_SIZE / 2); - dma_len = TEST_DATA_BLK_SIZE / 2; - - /* Initialize the source buffer with test specific data */ - write_source_buf_data(src_buf_virt, dma_len); - - /* Program Exerciser DMA controller with the source buffer information */ - val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)src_buf_phys, dma_len, instance); + /* Trigger DMA from input buffer to exerciser memory */ if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { val_print(AVS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); goto test_fail; } - /* READ Back from Exerciser to validate above DMA write */ - val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dest_buf_phys, dma_len, instance); + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } + + /* Trigger DMA from exerciser memory to output buffer*/ if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { val_print(AVS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); goto test_fail; } - /* Disbale exerciser and it's root port to stop sending TLPs + if (val_memory_compare(dram_buf_pasid1_in_virt, dram_buf_pasid1_out_virt, dma_len)) { + val_print(AVS_PRINT_ERR, "\n Data Comparision failure for Exerciser %4x", instance); + goto test_fail; + } + + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } + + /* + * Disable exerciser to stop sending TLPs * with PASID TLP Prefixes. This includes re-setting PASID Enable bit + * in exerciser PASID Control register. + */ + if(val_exerciser_ops(PASID_TLP_STOP, (uint64_t)master.substreamid, instance)) { + val_print(AVS_PRINT_ERR, "\n Exerciser %x PASID TLP Prefix disable error", instance); + goto test_fail; + } + + /* Now setup memory descriptor for creating page tables for pasid2. */ + mem_desc->virtual_address = (uint64_t)dram_buf_base_virt; + mem_desc->physical_address = dram_buf_pasid2_base_phys; + mem_desc->length = test_data_blk_size; + mem_desc->attributes |= PGT_STAGE1_AP_RW; + + if (val_pgt_create(mem_desc, &pgt_desc)) + goto test_fail; + + pgt_base_pasid2 = pgt_desc.pgt_base; + + master.substreamid = TEST_PASID2; + if (val_smmu_map(master, pgt_desc)) + { + val_print(AVS_PRINT_ERR, "\n SMMU mapping failed (%d) ", master.substreamid); + goto test_fail; + } + + dram_buf_in_iova = mem_desc->virtual_address; + dram_buf_out_iova = dram_buf_in_iova + (test_data_blk_size / 2); + + write_test_data(dram_buf_pasid2_in_virt, dma_len); + + /* Program exerciser and it's root port to start sending TLPs + * with PASID TLP Prefixes. This includes setting PASID Enable bit * in exerciser PASID Control register and the implementation specific * PASID Enable bit of the Root Port. */ - if(val_exerciser_ops(PASID_TLP_STOP, (uint64_t)&e_pasid, instance)) { + if(val_exerciser_ops(PASID_TLP_START, (uint64_t)master.substreamid, instance)) { + val_print(AVS_PRINT_ERR, "\n Exerciser %x PASID TLP Prefix enable error", instance); + goto test_fail; + } + + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } + + /* Trigger DMA from input buffer to exerciser memory */ + if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); + goto test_fail; + } + + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } + + /* Trigger DMA from exerciser memory to output buffer */ + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); + goto test_fail; + } + + if(val_exerciser_ops(PASID_TLP_STOP, (uint64_t)master.substreamid, instance)) { val_print(AVS_PRINT_ERR, "\n Exerciser %x PASID TLP Prefix disable error", instance); goto test_fail; } - if (val_memory_compare(src_buf_virt, dest_buf_virt, dma_len)) { - val_print(AVS_PRINT_ERR, "\n Data Comparison failure for Exerciser %4x", instance); + if (val_memory_compare(dram_buf_pasid2_in_virt, dram_buf_pasid2_out_virt, dma_len)) { + val_print(AVS_PRINT_ERR, "\n Data Comparasion failure for Exerciser %4x", instance); goto test_fail; } + val_smmu_unmap(master); + pgt_desc.pgt_base = pgt_base_pasid1; + val_pgt_destroy(pgt_desc); + pgt_desc.pgt_base = pgt_base_pasid2; + val_pgt_destroy(pgt_desc); + val_smmu_disable(master.smmu_index); + pgt_base_pasid1 = pgt_base_pasid2 = 0; } - if (e_valid_cnt) { - val_memory_free(src_buf_virt); val_set_status (pe_index, RESULT_PASS (g_sbsa_level, TEST_NUM, 01)); } else { val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 00)); } - - return; + goto test_clean; test_fail: - val_memory_free(src_buf_virt); val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02));; - return; +test_clean: + val_memory_free_pages(dram_buf_base_virt, TEST_DATA_NUM_PAGES * 2); + if (pgt_base_pasid1 != 0) + { + pgt_desc.pgt_base = pgt_base_pasid1; + val_pgt_destroy(pgt_desc); + } + if (pgt_base_pasid1 != 0) + { + pgt_desc.pgt_base = pgt_base_pasid2; + val_pgt_destroy(pgt_desc); + } } uint32_t diff --git a/test_pool/exerciser/test_e007.c b/test_pool/exerciser/test_e007.c index 6a3c698b..fe0668d6 100644 --- a/test_pool/exerciser/test_e007.c +++ b/test_pool/exerciser/test_e007.c @@ -167,6 +167,10 @@ payload (void) while (instance-- != 0) { + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + /* Get the exerciser BDF */ e_bdf = val_exerciser_get_bdf(instance); @@ -189,7 +193,7 @@ payload (void) } /* Get a WB, outer shareable DDR Buffer of size TEST_DATA_BLK_SIZE */ - dram_buf1_virt = val_memory_alloc_coherent(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_phys); + dram_buf1_virt = val_memory_alloc_cacheable(e_bdf, TEST_DATA_BLK_SIZE, &dram_buf1_phys); if (!dram_buf1_virt) { val_print(AVS_PRINT_ERR, "\n WB and OSH mem alloc failure %x", 02); val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); @@ -197,11 +201,11 @@ payload (void) } /* Program exerciser hierarchy to start sending/receiving TLPs - * with No Snoop attribute header. This includes enabling + * with No Snoop attribute header. This includes disabling * No snoop bit in exerciser control register. */ - if (val_exerciser_ops(NO_SNOOP_CLEAR_TLP_START, 0, instance)) { - val_print(AVS_PRINT_ERR, "\n Exerciser %x No Snoop enable error", instance); + if (val_exerciser_ops(TXN_NO_SNOOP_DISABLE, 0, instance)) { + val_print(AVS_PRINT_ERR, "\n Exerciser %x No Snoop disable error", instance); goto test_fail; } @@ -209,14 +213,8 @@ payload (void) test_sequence2(dram_buf1_virt, dram_buf1_phys, e_bdf, instance)) goto test_fail; - /* Stop exerciser hierarchy sending/receiving TLPs with No Snoop attribute header */ - if (val_exerciser_ops(NO_SNOOP_CLEAR_TLP_STOP, 0, instance)) { - val_print(AVS_PRINT_ERR, "\n Exerciser %x No snoop TLP disable error", instance); - goto test_fail; - } - /* Return this exerciser dma memory back to the heap manager */ - val_memory_free_coherent(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys); + val_memory_free_cacheable(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys); } @@ -225,7 +223,7 @@ payload (void) test_fail: val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); - val_memory_free_coherent(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys); + val_memory_free_cacheable(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys); return; } diff --git a/test_pool/exerciser/test_e011.c b/test_pool/exerciser/test_e011.c new file mode 100644 index 00000000..03f1e8a0 --- /dev/null +++ b/test_pool/exerciser/test_e011.c @@ -0,0 +1,315 @@ +/** @file + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pgt.h" +#include "val/include/sbsa_avs_iovirt.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 11) +#define TEST_DESC "ATS Functionality Check " + +#define TEST_DATA_NUM_PAGES 1 +#define TEST_DATA 0xDE + +static +void +write_test_data(void *buf, uint32_t size) +{ + + uint32_t index; + + for (index = 0; index < size; index++) { + *((char8_t *)buf + index) = TEST_DATA; + } + + val_data_cache_ops_by_va((addr_t)buf, CLEAN_AND_INVALIDATE); +} + +static +void +clear_dram_buf(void *buf, uint32_t size) +{ + + uint32_t index; + + for (index = 0; index < size; index++) { + *((char8_t *)buf + index) = 0; + } + + val_data_cache_ops_by_va((addr_t)buf, CLEAN_AND_INVALIDATE); +} + +static +void +payload(void) +{ + uint32_t pe_index; + uint32_t dma_len; + uint32_t instance; + uint32_t e_bdf; + uint32_t cap_base; + void *dram_buf_in_virt; + void *dram_buf_out_virt; + uint64_t dram_buf_in_phys; + uint64_t dram_buf_out_phys; + uint64_t dram_buf_in_iova; + uint64_t dram_buf_out_iova; + uint32_t num_exercisers, num_smmus; + uint32_t device_id, its_id; + uint32_t page_size = val_memory_page_size(); + memory_region_descriptor_t mem_desc_array[2], *mem_desc; + pgt_descriptor_t pgt_desc; + smmu_master_attributes_t master; + uint64_t ttbr; + uint32_t test_data_blk_size = page_size * TEST_DATA_NUM_PAGES; + uint64_t *pgt_base_array; + uint64_t translated_addr; + + /* Initialize DMA master and memory descriptors */ + val_memory_set(&master, sizeof(master), 0); + val_memory_set(mem_desc_array, sizeof(mem_desc_array), 0); + mem_desc = &mem_desc_array[0]; + dram_buf_in_phys = 0; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); + + /* Allocate an array to store base addresses of page tables allocated for + * all exercisers + */ + pgt_base_array = val_memory_alloc(sizeof(uint64_t) * num_exercisers); + if (!pgt_base_array) { + val_print(AVS_PRINT_ERR, "\n mem alloc failure", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + val_memory_set(pgt_base_array, sizeof(uint64_t) * num_exercisers, 0); + + /* Allocate a buffer to perform DMA tests on */ + dram_buf_in_virt = val_memory_alloc_pages(TEST_DATA_NUM_PAGES); + if (!dram_buf_in_virt) { + val_print(AVS_PRINT_ERR, "\n Cacheable mem alloc failure", 0); + val_memory_free(pgt_base_array); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* Set the virtual and physical addresses for test buffers */ + dram_buf_in_phys = (uint64_t)val_memory_virt_to_phys(dram_buf_in_virt); + dram_buf_out_virt = dram_buf_in_virt + (test_data_blk_size / 2); + dram_buf_out_phys = dram_buf_in_phys + (test_data_blk_size / 2); + dma_len = test_data_blk_size / 2; + + /* Get translation attributes via TCR and translation table base via TTBR */ + if (val_pe_reg_read_tcr(0 /*for TTBR0*/, + &pgt_desc.tcr)) + goto test_fail; + + if (val_pe_reg_read_ttbr(0 /*for TTBR0*/, + &ttbr)) + goto test_fail; + + pgt_desc.pgt_base = (ttbr & AARCH64_TTBR_ADDR_MASK); + pgt_desc.mair = val_pe_reg_read(MAIR_ELx); + pgt_desc.stage = PGT_STAGE1; + + /* Get memory attributes of the test buffer, we'll use the same attibutes to create + * our own page table later. + */ + if (val_pgt_get_attributes(pgt_desc, (uint64_t)dram_buf_in_virt, &mem_desc->attributes)) + goto test_fail; + + /* Enable all SMMUs */ + for (instance = 0; instance < num_smmus; ++instance) + val_smmu_enable(instance); + + for (instance = 0; instance < num_exercisers; ++instance) { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + /* Get exerciser bdf */ + e_bdf = val_exerciser_get_bdf(instance); + + /* If ATS Capability Not Present, Skip. */ + if (val_pcie_find_capability(e_bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS) + continue; + + /* Get SMMU node index for this exerciser instance */ + master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + + clear_dram_buf(dram_buf_in_virt, test_data_blk_size); + + dram_buf_in_iova = dram_buf_in_phys; + dram_buf_out_iova = dram_buf_out_phys; + if (master.smmu_index != AVS_INVALID_INDEX && + val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, master.smmu_index) == 3) { + if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf), + PCIE_EXTRACT_BDF_SEG(e_bdf), + &device_id, &master.streamid, + &its_id)) + continue; + + /* Each exerciser instance accesses a unique IOVA, which, because of SMMU translations, + * will point to the same physical address. We create the requisite page tables and + * configure the SMMU for each exerciser as such. + */ + + mem_desc->virtual_address = (uint64_t)dram_buf_in_virt + instance * test_data_blk_size; + mem_desc->physical_address = dram_buf_in_phys; + mem_desc->length = test_data_blk_size; + mem_desc->attributes |= PGT_STAGE1_AP_RW; + + /* Need to know input and output address sizes before creating page table */ + if ((pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index)) == 0) + goto test_fail; + + if ((pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index)) == 0) + goto test_fail; + + if (val_pgt_create(mem_desc, &pgt_desc)) + goto test_fail; + + pgt_base_array[instance] = pgt_desc.pgt_base; + + /* Configure the SMMU tables for this exerciser to use this page table for VA to PA translations*/ + if (val_smmu_map(master, pgt_desc)) + { + val_print(AVS_PRINT_ERR, "\n SMMU mapping failed (%x) ", e_bdf); + goto test_fail; + } + + dram_buf_in_iova = mem_desc->virtual_address; + dram_buf_out_iova = dram_buf_in_iova + (test_data_blk_size / 2); + } + + /* Send an ATS Translation Request for the VA */ + if (val_exerciser_ops(ATS_TXN_REQ, (uint64_t)dram_buf_in_virt + instance * test_data_blk_size, instance)) { + val_print(AVS_PRINT_ERR, "\n ATS Translation Req Failed exerciser %4x", instance); + goto test_fail; + } + + /* Get ATS Translation Response */ + if (val_exerciser_get_param(ATS_RES_ATTRIBUTES, &translated_addr, NULL, instance)) { + val_print(AVS_PRINT_ERR, "\n ATS Response failure %4x", instance); + goto test_fail; + } + + /* Compare Translated Addr with Physical Address from the Mappings */ + if (translated_addr != dram_buf_in_phys) { + val_print(AVS_PRINT_ERR, "\n ATS Translation failure %4x", instance); + goto test_fail; + } + + /* Initialize the sender buffer with test specific data */ + write_test_data(dram_buf_in_virt, dma_len); + + /* Configure Exerciser to issue subsequent DMA transactions with AT(Address Translated) bit Set */ + val_exerciser_set_param(CFG_TXN_ATTRIBUTES, TXN_ADDR_TYPE, AT_TRANSLATED, instance); + + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_in_phys, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } + + /* Trigger DMA from input buffer to exerciser memory */ + if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); + goto test_fail; + } + + if (val_exerciser_set_param(DMA_ATTRIBUTES, dram_buf_out_iova, dma_len, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA attributes setting failure %4x", instance); + goto test_fail; + } + + /* Trigger DMA from exerciser memory to output buffer*/ + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); + goto test_fail; + } + + if (val_memory_compare(dram_buf_in_virt, dram_buf_out_virt, dma_len)) { + val_print(AVS_PRINT_ERR, "\n Data Comparasion failure for Exerciser %4x", instance); + goto test_fail; + } + clear_dram_buf(dram_buf_in_virt, test_data_blk_size); + } + + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + goto test_clean; + +test_fail: + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + +test_clean: + /* Return the pages to the heap manager */ + val_memory_free_pages(dram_buf_in_virt, TEST_DATA_NUM_PAGES); + + /* Remove all address mappings for each exerciser */ + for (instance = 0; instance < num_exercisers; ++instance) + { + e_bdf = val_exerciser_get_bdf(instance); + master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf), + PCIE_EXTRACT_BDF_SEG(e_bdf), + &device_id, &master.streamid, + &its_id)) + continue; + + val_smmu_unmap(master); + if (pgt_base_array[instance] != 0) { + pgt_desc.pgt_base = pgt_base_array[instance]; + val_pgt_destroy(pgt_desc); + } + } + + /* Disable all SMMUs */ + for (instance = 0; instance < num_smmus; ++instance) + val_smmu_disable(instance); + + val_memory_free(pgt_base_array); +} + + +uint32_t +e011_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/exerciser/test_e012.c b/test_pool/exerciser/test_e012.c new file mode 100644 index 00000000..1132f99c --- /dev/null +++ b/test_pool/exerciser/test_e012.c @@ -0,0 +1,285 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 12) +#define TEST_DESC "Check P2P ACS Functionality " + +static +uint32_t +get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, + uint32_t *tgt_rp_bdf, uint64_t *bar_base) +{ + + uint32_t erp_bdf; + uint32_t e_bdf; + uint32_t instance; + uint32_t cap_base; + + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) + { + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + e_bdf = val_exerciser_get_bdf(instance); + + /* Read e_bdf BAR Register to get the Address to perform P2P */ + /* If No BAR Space, continue */ + val_pcie_get_mmio_bar(e_bdf, bar_base); + if (*bar_base == 0) + continue; + + /* Get RP of the exerciser */ + if (val_pcie_get_rootport(e_bdf, &erp_bdf)) + continue; + + /* It ACS Not Supported, continue */ + if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { + val_print(AVS_PRINT_DEBUG, "\n ACS Not Supported for BDF : 0x%x", erp_bdf); + continue; + } + + if(req_rp_bdf != erp_bdf) + { + *tgt_e_bdf = e_bdf; + *tgt_rp_bdf = erp_bdf; + + /* Enable Bus Master Enable */ + val_pcie_enable_bme(e_bdf); + /* Enable Memory Space Access */ + val_pcie_enable_msa(e_bdf); + + return AVS_STATUS_PASS; + } + } + + /* Return failure if No Such Exerciser Found */ + *tgt_e_bdf = 0; + *tgt_rp_bdf = 0; + *bar_base = 0; + return AVS_STATUS_FAIL; +} + +uint32_t +check_source_validation (uint32_t req_instance, uint32_t req_e_bdf, + uint32_t req_rp_bdf, uint32_t tgt_e_bdf, + uint64_t bar_base) +{ + /* Check 1 : ACS Source Validation */ + + uint32_t reg_value; + uint32_t sub_bus; + uint32_t new_bdf; + + /* Pass Sequence */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)bar_base, 1, req_instance); + + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance)) { + val_print(AVS_PRINT_DEBUG, "\n DMA failure from exerciser %4x", req_instance); + return AVS_STATUS_FAIL; + } + + /* Clear Device Status Register Error Bits */ + val_pcie_clear_device_status_error(req_rp_bdf); + + /* Change Requester ID for DMA such that it does not fall under req_rp_bdf + * Secondary & Subordinate bdf + */ + val_pcie_read_cfg(req_rp_bdf, TYPE1_PBN, ®_value); + sub_bus = (reg_value >> SUBBN_SHIFT) & SUBBN_MASK; + new_bdf = PCIE_CREATE_BDF(PCIE_EXTRACT_BDF_SEG(req_rp_bdf), + (sub_bus+1), 0, 0); + + val_exerciser_set_param(CFG_TXN_ATTRIBUTES, TXN_REQ_ID, new_bdf, req_instance); + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)bar_base, 1, req_instance); + + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance)) { + val_print(AVS_PRINT_DEBUG, "\n DMA failure from exerciser %4x", req_instance); + return AVS_STATUS_FAIL; + } + + /* Check For Error in Device Status Register / Status Register + * Secondary Status Register + */ + if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) && + (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) { + /* Fail the part */ + val_print(AVS_PRINT_DEBUG, "\n Src Validation Expected Error RootPort : 0x%x", req_rp_bdf); + return AVS_STATUS_FAIL; + } + + return AVS_STATUS_PASS; +} + +uint32_t +check_transaction_blocking (uint32_t req_instance, uint32_t req_e_bdf, + uint32_t req_rp_bdf, uint32_t tgt_e_bdf, + uint64_t bar_base) +{ + /* Check 2 : ACS Transaction Blocking */ + + /* Clear Device Status Register Error Bits */ + val_pcie_clear_device_status_error(req_rp_bdf); + + /* Transaction with Address Type other than default(0x0) + * Should result into Transaction blocking. + */ + val_exerciser_set_param(CFG_TXN_ATTRIBUTES, TXN_ADDR_TYPE, AT_RESERVED, req_instance); + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)bar_base, 1, req_instance); + + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance)) { + val_print(AVS_PRINT_DEBUG, "\n DMA failure from exerciser %4x", req_instance); + return AVS_STATUS_FAIL; + } + + /* Check For Error in Device Status Register / Status Register + * Secondary Status Register + */ + if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) && + (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) { + /* Fail the part */ + val_print(AVS_PRINT_DEBUG, "\n Traxn Blocking Expected Error RootPort : 0x%x", req_rp_bdf); + return AVS_STATUS_FAIL; + } + + return AVS_STATUS_PASS; +} + +static +void +payload(void) +{ + + uint32_t status; + uint32_t pe_index; + uint32_t req_e_bdf; + uint32_t req_rp_bdf; + uint32_t tgt_e_bdf; + uint32_t tgt_rp_bdf; + uint32_t instance; + uint32_t fail_cnt; + uint32_t cap_base; + uint32_t reg_value; + uint32_t test_skip; + uint64_t bar_base; + uint32_t curr_bdf_failed = 0; + + fail_cnt = 0; + test_skip = 1; + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + /* Check If PCIe Hierarchy supports P2P. */ + if (val_pcie_p2p_support()) + { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + while (instance-- != 0) + { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + req_e_bdf = val_exerciser_get_bdf(instance); + + /* Get RP of the exerciser */ + if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf)) + continue; + + /* It ACS Not Supported, Fail.*/ + if (val_pcie_find_capability(req_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n ACS Not Supported for BDF : 0x%x", req_rp_bdf); + fail_cnt++; + continue; + } + + /* Enable Source Validation & Transaction Blocking */ + val_pcie_read_cfg(req_rp_bdf, cap_base + ACSCR_OFFSET, ®_value); + reg_value = reg_value | (1 << ACS_CTRL_SVE_SHIFT) | (1 << ACS_CTRL_TBE_SHIFT); + val_pcie_write_cfg(req_rp_bdf, cap_base + ACSCR_OFFSET, reg_value); + + /* Find another exerciser on other rootport, + Break from the test if no such exerciser if found */ + if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base)) + break; + + /* If Both RP's Supports ACS Then Only Run Otherwise Skip the EP */ + test_skip = 0; + + /* Check For ACS Functionality */ + status = check_source_validation(instance, req_e_bdf, req_rp_bdf, tgt_e_bdf, bar_base); + if (status == AVS_STATUS_SKIP) + val_print(AVS_PRINT_DEBUG, "\n ACS Source Validation Skipped for 0x%x", req_rp_bdf); + else if (status) + curr_bdf_failed++; + + status = check_transaction_blocking(instance, req_e_bdf, req_rp_bdf, tgt_e_bdf, bar_base); + if (status == AVS_STATUS_SKIP) + val_print(AVS_PRINT_DEBUG, "\n ACS Transaction Blocking Skipped for 0x%x", req_rp_bdf); + else if (status) + curr_bdf_failed++; + + if(curr_bdf_failed > 0) { + val_print(AVS_PRINT_ERR, "\n ACS Functional Check Failed, RP Bdf : 0x%x", req_rp_bdf); + curr_bdf_failed = 0; + fail_cnt++; + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +e012_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/exerciser/test_e013.c b/test_pool/exerciser/test_e013.c new file mode 100644 index 00000000..db9e5264 --- /dev/null +++ b/test_pool/exerciser/test_e013.c @@ -0,0 +1,401 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pgt.h" +#include "val/include/sbsa_avs_iovirt.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 13) +#define TEST_DESC "Check ACS Redirected Req Valid " + +static +uint32_t +get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf, + uint32_t *tgt_rp_bdf, uint64_t *bar_base) +{ + + uint32_t erp_bdf; + uint32_t e_bdf; + uint32_t instance; + uint32_t cap_base; + + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) + { + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + e_bdf = val_exerciser_get_bdf(instance); + + /* Read e_bdf BAR Register to get the Address to perform P2P */ + /* If No BAR Space, continue */ + val_pcie_get_mmio_bar(e_bdf, bar_base); + if (*bar_base == 0) + continue; + + /* Get RP of the exerciser */ + if (val_pcie_get_rootport(e_bdf, &erp_bdf)) + continue; + + /* It ACS Not Supported, continue */ + if (val_pcie_find_capability(erp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { + val_print(AVS_PRINT_DEBUG, "\n ACS Not Supported for BDF : 0x%x", erp_bdf); + continue; + } + + if(req_rp_bdf != erp_bdf) + { + *tgt_e_bdf = e_bdf; + *tgt_rp_bdf = erp_bdf; + + /* Enable Bus Master Enable */ + val_pcie_enable_bme(e_bdf); + /* Enable Memory Space Access */ + val_pcie_enable_msa(e_bdf); + + return AVS_STATUS_PASS; + } + } + + /* Return failure if No Such Exerciser Found */ + *tgt_e_bdf = 0; + *tgt_rp_bdf = 0; + *bar_base = 0; + return AVS_STATUS_FAIL; +} + +uint32_t +create_va_pa_mapping (uint64_t txn_va, uint64_t txn_pa, + smmu_master_attributes_t *smmu_master, + pgt_descriptor_t *pgt_descriptor, + uint32_t e_bdf, uint32_t pgt_ap) +{ + smmu_master_attributes_t master; + pgt_descriptor_t pgt_desc; + memory_region_descriptor_t mem_desc_array[2], *mem_desc; + uint64_t ttbr; + uint32_t num_smmus; + uint32_t instance; + uint32_t device_id, its_id; + + master = *smmu_master; + pgt_desc = *pgt_descriptor; + + val_memory_set(&master, sizeof(master), 0); + val_memory_set(mem_desc_array, sizeof(mem_desc_array), 0); + mem_desc = &mem_desc_array[0]; + + /* Get translation attributes via TCR and translation table base via TTBR */ + if (val_pe_reg_read_tcr(0 /*for TTBR0*/, &pgt_desc.tcr)) + return AVS_STATUS_FAIL; + if (val_pe_reg_read_ttbr(0 /*TTBR0*/, &ttbr)) + return AVS_STATUS_FAIL; + pgt_desc.pgt_base = (ttbr & AARCH64_TTBR_ADDR_MASK); + pgt_desc.mair = val_pe_reg_read(MAIR_ELx); + pgt_desc.stage = PGT_STAGE1; + + /* Get memory attributes of the test buffer, we'll use the same attibutes to create + * our own page table later. + */ + if (val_pgt_get_attributes(pgt_desc, (uint64_t)txn_va, &mem_desc->attributes)) + return AVS_STATUS_FAIL; + + num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); + + /* Enable all SMMUs */ + for (instance = 0; instance < num_smmus; ++instance) + val_smmu_enable(instance); + + /* Get SMMU node index for this exerciser instance */ + master.smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + + if (master.smmu_index != AVS_INVALID_INDEX && + val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, master.smmu_index) == 3) { + if (val_iovirt_get_device_info(PCIE_CREATE_BDF_PACKED(e_bdf), + PCIE_EXTRACT_BDF_SEG(e_bdf), + &device_id, &master.streamid, + &its_id)) + return AVS_STATUS_FAIL; + + /* Each exerciser instance accesses a unique IOVA, which, because of SMMU translations, + * will point to the same physical address. We create the requisite page tables and + * configure the SMMU for each exerciser as such. + */ + + mem_desc->virtual_address = (uint64_t)txn_va; + mem_desc->physical_address = txn_pa; + mem_desc->length = 4; /* 4 Bytes */ + mem_desc->attributes |= pgt_ap; + + /* Need to know input and output address sizes before creating page table */ + if ((pgt_desc.ias = val_smmu_get_info(SMMU_IN_ADDR_SIZE, master.smmu_index)) == 0) + return AVS_STATUS_FAIL; + + if ((pgt_desc.oas = val_smmu_get_info(SMMU_OUT_ADDR_SIZE, master.smmu_index)) == 0) + return AVS_STATUS_FAIL; + + if (val_pgt_create(mem_desc, &pgt_desc)) + return AVS_STATUS_FAIL; + + /* Configure the SMMU tables for this exerciser to use this page table for VA to PA translations*/ + if (val_smmu_map(master, pgt_desc)) + { + val_print(AVS_PRINT_DEBUG, "\n SMMU mapping failed (%x) ", e_bdf); + return AVS_STATUS_FAIL; + } + return AVS_STATUS_PASS; + } + return AVS_STATUS_FAIL; +} + +uint32_t +check_redirected_req_validation (uint32_t req_instance, uint32_t req_e_bdf, + uint32_t req_rp_bdf, uint32_t tgt_e_bdf, + uint64_t bar_base) +{ + uint64_t txn_va; + uint32_t instance; + uint32_t e_bdf; + uint32_t num_smmus; + uint32_t status; + smmu_master_attributes_t master; + pgt_descriptor_t pgt_desc; + + /* Sequence 1 : No Write Permission, Trigger a DMA Write to bar address + * It should Result into ACS Violation + */ + + /* Clear Device Status Register Error Bits */ + val_pcie_clear_device_status_error(req_rp_bdf); + + /* Create VA-PA Mapping in SMMU with PGT permissions as Read Only */ + /* Initialize DMA master and memory descriptors */ + + /* Set the virtual and physical addresses for test buffers */ + txn_va = (uint64_t)val_memory_phys_to_virt(bar_base); + + /* Get exerciser bdf */ + e_bdf = val_exerciser_get_bdf(req_instance); + + num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); + + status = create_va_pa_mapping(txn_va, bar_base, &master, + &pgt_desc, e_bdf, + PGT_STAGE1_AP_RO); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Seq1:SMMU Mapping Failed For : %4x", req_instance); + goto test_fail; + } + + /* Trigger DMA from req_e_bdf */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)txn_va, 1, req_instance); + + /* DMA Should fail because Write permission not given */ + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance) == 0) { + val_print(AVS_PRINT_DEBUG, "\n Seq1:DMA Write Should not happen For : %4x", req_instance); + goto test_fail; + } + + /* Check For Error in Device Status Register / Status Register + * Secondary Status Register + */ + if ((val_pcie_is_device_status_error(req_rp_bdf) == 0) && + (val_pcie_is_sig_target_abort(req_rp_bdf) == 0)) { + val_print(AVS_PRINT_DEBUG, "\n Seq1:Expected Error For RootPort : 0x%x", req_rp_bdf); + goto test_fail; + } + + /* Unmap SMMU & Pgt */ + val_smmu_unmap(master); + val_pgt_destroy(pgt_desc); + + /* Disable all SMMUs */ + for (instance = 0; instance < num_smmus; ++instance) + val_smmu_disable(instance); + + /* Sequence 2 : Read Write Permission, Trigger a DMA Write to bar address + * It should NOT Result into ACS Violation + */ + + /* Create VA-PA Mapping in SMMU with PGT permissions as Read Write */ + status = create_va_pa_mapping(txn_va, bar_base, &master, + &pgt_desc, e_bdf, + PGT_STAGE1_AP_RW); + if (status) { + val_print(AVS_PRINT_DEBUG, "\n Seq2:SMMU Mapping Failed For : %4x", req_instance); + goto test_fail; + } + + /* Trigger DMA from req_e_bdf */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)txn_va, 1, req_instance); + + /* DMA Should fail not because Write permission given */ + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, req_instance) != 0) { + val_print(AVS_PRINT_DEBUG, "\n Seq2:DMA Write Should happen For : %4x", req_instance); + goto test_fail; + } + + /* Check For Error in Device Status Register / Status Register + * Secondary Status Register + */ + if (val_pcie_is_device_status_error(req_rp_bdf) || + val_pcie_is_sig_target_abort(req_rp_bdf)) { + val_print(AVS_PRINT_DEBUG, "\n Seq2:Expected No Error For RootPort : 0x%x", req_rp_bdf); + goto test_fail; + } + + status = AVS_STATUS_PASS; + goto test_clean; + +test_fail: + status = AVS_STATUS_FAIL; + +test_clean: + val_smmu_unmap(master); + val_pgt_destroy(pgt_desc); + + /* Disable all SMMUs */ + for (instance = 0; instance < num_smmus; ++instance) + val_smmu_disable(instance); + return status; +} + +static +void +payload(void) +{ + + uint32_t status; + uint32_t pe_index; + uint32_t bdf; + uint32_t req_e_bdf; + uint32_t req_rp_bdf; + uint32_t tgt_e_bdf; + uint32_t tgt_rp_bdf; + uint32_t instance; + uint32_t fail_cnt; + uint32_t cap_base; + uint32_t reg_value; + uint32_t test_skip; + uint32_t tbl_index; + uint64_t bar_base; + + fail_cnt = 0; + test_skip = 1; + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + pcie_device_bdf_table *bdf_tbl_ptr; + + tbl_index = 0; + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + /* Check If PCIe Hierarchy supports P2P. */ + if (val_pcie_p2p_support()) + { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) == PCIE_SUCCESS) { + /* Enable P2P Request Redirect & Upstream Forwarding */ + val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, ®_value); + + reg_value = reg_value | (1 << ACS_CTRL_RRE_SHIFT) | (1 << ACS_CTRL_UFE_SHIFT); + val_pcie_write_cfg(bdf, cap_base + ACSCR_OFFSET, reg_value); + } + } + + while (instance-- != 0) + { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + req_e_bdf = val_exerciser_get_bdf(instance); + + /* Get RP of the exerciser */ + if (val_pcie_get_rootport(req_e_bdf, &req_rp_bdf)) + continue; + + /* It ACS Not Supported, Fail.*/ + if (val_pcie_find_capability(req_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n ACS Not Supported for BDF : 0x%x", req_rp_bdf); + fail_cnt++; + continue; + } + + /* Find another exerciser on other rootport, + Break from the test if no such exerciser if found */ + if (get_target_exer_bdf(req_rp_bdf, &tgt_e_bdf, &tgt_rp_bdf, &bar_base)) + break; + + /* If Both RP's Supports ACS Then Only Run Otherwise Skip the EP */ + test_skip = 0; + + /* Check For Redirected Request Validation Functionality */ + status = check_redirected_req_validation(instance, req_e_bdf, req_rp_bdf, tgt_e_bdf, bar_base); + if (status == AVS_STATUS_SKIP) + val_print(AVS_PRINT_ERR, "\n ACS Validation Check Skipped for 0x%x", req_rp_bdf); + else if (status) { + fail_cnt++; + val_print(AVS_PRINT_ERR, "\n ACS Redirected Req Check Failed for 0x%x", req_rp_bdf); + } + + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + + return; + +} + +uint32_t +e013_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/exerciser/test_e014.c b/test_pool/exerciser/test_e014.c new file mode 100644 index 00000000..b0893e15 --- /dev/null +++ b/test_pool/exerciser/test_e014.c @@ -0,0 +1,236 @@ +/** @file + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + + +/* Test sequence - Initialize a main memory region marked as WB, + * outer shareable by the PE page tables. CPU Write to this region with + * new data. Perform actions to maintain software coherency. + * Read the same data locations from the Exerciser with NS=1. The + * exerciser should get the latest data. The exerciser updates the + * location with newest data. PE reads the location and must get NEWEST VAL. + */ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pcie_enumeration.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 14) +#define TEST_DESC "Check PCIe Software Coherency " + +#define TEST_DATA_BLK_SIZE (4*1024) +#define NEW_DATA 0xAD +#define NEWEST_DATA 0xBC + +static uint32_t test_sequence2(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, + uint32_t instance) +{ + + uint32_t dma_len; + void *dram_buf2_virt; + void *dram_buf2_phys; + + /* Set up a second dram buffer to send NEWEST_DATA to exerciser memory */ + dram_buf2_virt = dram_buf1_virt + (TEST_DATA_BLK_SIZE / 2); + dram_buf2_phys = dram_buf1_phys + (TEST_DATA_BLK_SIZE / 2); + dma_len = TEST_DATA_BLK_SIZE / 2; + + /* Write dram_buf2 with known data and flush the buffer to main memory */ + val_memory_set(dram_buf2_virt, dma_len, NEWEST_DATA); + val_data_cache_ops_by_va((addr_t)dram_buf2_virt, CLEAN_AND_INVALIDATE); + + /* Perform DMA OUT to copy contents of dram_buf2 to exerciser memory */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf2_phys, dma_len, instance); + if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); + return 1; + } + + /* Perform DMA IN to copy content back from exerciser memory to dram_buf1 */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance); + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); + return 1; + } + + /* Invalidate dram_buf1 and dram_buf2 contents present in CPU caches */ + val_data_cache_ops_by_va((addr_t)dram_buf1_virt, INVALIDATE); + val_data_cache_ops_by_va((addr_t)dram_buf2_virt, INVALIDATE); + + /* Compare the contents of ddr_buf1 and ddr_buf2 for NEW_DATA */ + if (val_memory_compare(dram_buf1_virt, dram_buf2_virt, dma_len)) { + val_print(AVS_PRINT_ERR, "\n I/O coherency failure for Exerciser %4x", instance); + return 1; + } + + /* Return success */ + return 0; +} + +static uint32_t test_sequence1(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t e_bdf, + uint32_t instance) +{ + + uint32_t dma_len; + void *dram_buf2_virt; + void *dram_buf2_phys; + + dram_buf2_virt = dram_buf1_virt + (TEST_DATA_BLK_SIZE / 2); + dram_buf2_phys = dram_buf1_phys + (TEST_DATA_BLK_SIZE / 2); + dma_len = TEST_DATA_BLK_SIZE / 2; + + /* Write dram_buf1 cache with new data */ + val_memory_set(dram_buf1_virt, dma_len, NEW_DATA); + + /* Maintain software coherency */ + val_data_cache_ops_by_va((addr_t)dram_buf1_virt, CLEAN_AND_INVALIDATE); + + /* Perform DMA OUT to copy contents of dram_buf1 to exerciser memory */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance); + if (val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA write failure to exerciser %4x", instance); + return 1; + } + + /* Perform DMA IN to copy the content from exerciser memory to dram_buf2 */ + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf2_phys, dma_len, instance); + if (val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance)) { + val_print(AVS_PRINT_ERR, "\n DMA read failure from exerciser %4x", instance); + return 1; + } + + /* Invalidate dram_buf2 contents present in CPU caches */ + val_data_cache_ops_by_va((addr_t)dram_buf2_virt, INVALIDATE); + + /* Compare the contents of ddr_buf1 and ddr_buf2 for NEW_DATA */ + if (val_memory_compare(dram_buf1_virt, dram_buf2_virt, dma_len)) { + val_print(AVS_PRINT_ERR, "\n I/O coherency failure for Exerciser %4x", instance); + return 1; + } + + /* Return success */ + return 0; +} + + +static +void +payload (void) +{ + + uint32_t pe_index; + uint32_t instance; + uint32_t e_bdf; + uint32_t smmu_index; + void *dram_buf1_virt; + void *dram_buf1_phys; + + dram_buf1_virt = NULL; + dram_buf1_phys = NULL; + + pe_index = val_pe_get_index_mpid (val_pe_get_mpid()); + + /* Read the number of excerciser cards */ + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + /* Get the exerciser BDF */ + e_bdf = val_exerciser_get_bdf(instance); + + /* Find SMMU node index for this exerciser instance */ + smmu_index = val_iovirt_get_rc_smmu_index(PCIE_EXTRACT_BDF_SEG(e_bdf)); + + /* Disable SMMU globally so that the transaction passes + * through the SMMU without any address modification. + * Global attributes, such as memory type or Shareability, + * might be applied from the SMMU_GBPA register of the SMMU. + * Or, the SMMU_GBPA register might be configured to abort + * all transactions. Do this only if the RC is behind an SMMU. + */ + if (smmu_index != AVS_INVALID_INDEX) { + if(val_smmu_disable(smmu_index)) { + val_print(AVS_PRINT_ERR, "\n Exerciser %x smmu disable error", instance); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + } + + /* Get a WB, outer shareable DDR Buffer of size TEST_DATA_BLK_SIZE */ + dram_buf1_virt = val_memory_alloc_cacheable(e_bdf, TEST_DATA_BLK_SIZE, &dram_buf1_phys); + + if (!dram_buf1_virt) { + + val_print(AVS_PRINT_ERR, "\n WB and OSH mem alloc failure %x", 02); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Program exerciser hierarchy to start sending/receiving TLPs + * with No Snoop attribute header. This includes enabling + * No snoop bit in exerciser control register. + */ + if (val_exerciser_ops(TXN_NO_SNOOP_ENABLE, 0, instance)) { + val_print(AVS_PRINT_ERR, "\n Exerciser %x No Snoop enable error", instance); + goto test_fail; + } + + if (test_sequence1(dram_buf1_virt, dram_buf1_phys, e_bdf, instance) || + test_sequence2(dram_buf1_virt, dram_buf1_phys, e_bdf, instance)) + goto test_fail; + + /* Return this exerciser dma memory back to the heap manager */ + val_memory_free_cacheable(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys); + + } + + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0)); + return; + +test_fail: + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + val_memory_free_cacheable(e_bdf, TEST_DATA_BLK_SIZE, dram_buf1_virt, dram_buf1_phys); + return; +} + +uint32_t +e014_entry (void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test (TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + + if (status != AVS_STATUS_SKIP) { + val_run_test_payload (TEST_NUM, num_pe, payload, 0); + } + + /* Get the result from all PE and check for failure */ + status = val_check_for_error (TEST_NUM, num_pe); + + val_report_status (0, SBSA_AVS_END (g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/exerciser/test_e015.c b/test_pool/exerciser/test_e015.c new file mode 100644 index 00000000..1e0e33a4 --- /dev/null +++ b/test_pool/exerciser/test_e015.c @@ -0,0 +1,341 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie_enumeration.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_memory.h" +#include "val/include/sbsa_avs_exerciser.h" + +#define TEST_NUM (AVS_EXERCISER_TEST_NUM_BASE + 15) +#define TEST_DESC "Arrival order & Gathering Check " + +#define TEST_DATA_1B 0xEC +#define TEST_DATA_2B 0xABDE +#define TEST_DATA_4B 0xDEADDAED +#define TEST_DATA_8B 0xDEADDAEDABEDCEAC + +/* 0 means read transction, 1 means write transaction */ +static uint32_t transaction_order[] = {1, 1, 0, 1, 0, 0, 0, 0}; +static uint32_t run_flag; +static uint32_t fail_cnt; + +/* num of transactions captured and thier attributes is checked */ +static uint32_t test_sequence_check(uint32_t instance) +{ + uint64_t idx; + uint64_t num_transactions; + uint64_t transaction_type; + + /* Get number of transactions captured from exerciser */ + val_exerciser_get_param(NUM_TRANSACTIONS, NULL, &num_transactions, instance); + if (num_transactions != sizeof(transaction_order)/sizeof(transaction_order[0])) { + val_print(AVS_PRINT_ERR, "\n Exerciser %d gathering check failed", instance); + return 1; + } + + /* Check transactions arrival order */ + for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) { + val_exerciser_get_param(TRANSACTION_TYPE, &idx, &transaction_type, instance); + if (transaction_type != transaction_order[idx]) { + val_print(AVS_PRINT_ERR, "\n Exerciser %d arrival order check failed", instance); + return 1; + } + } + return 0; +} + +/* Performs reads/write on 1B data */ +static uint32_t test_sequence_1B(uint8_t *addr, uint8_t increment_addr, uint32_t instance) +{ + uint64_t idx; + + /* Start monitoring exerciser transactions */ + if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) + return AVS_STATUS_SKIP; + + run_flag = 1; + + /* Send the transaction on incrementalt addresses */ + for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) { + /* Write transaction */ + if (transaction_order[idx]) + val_mmio_write8((addr_t)addr, TEST_DATA_1B); + else + val_mmio_read8((addr_t)addr); + if (increment_addr) + addr++; + } + + /* Stop monitoring exerciser transactions */ + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + + return test_sequence_check(instance); +} + +/* Performs reads/write on 2B data */ +static uint32_t test_sequence_2B(uint16_t *addr, uint8_t increment_addr, uint32_t instance) +{ + uint64_t idx; + + /* Start monitoring exerciser transactions */ + if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) + return AVS_STATUS_SKIP; + + run_flag = 1; + + /* Send the transaction on incrementalt addresses */ + for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) { + /* Write transaction */ + if (transaction_order[idx]) + val_mmio_write16((addr_t)addr, TEST_DATA_2B); + else + val_mmio_read16((addr_t)addr); + if (increment_addr) + addr++; + } + + /* Stop monitoring exerciser transactions */ + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + + return test_sequence_check(instance); +} + +/* Performs reads/write on 4B data */ +static uint32_t test_sequence_4B(uint32_t *addr, uint8_t increment_addr, uint32_t instance) +{ + uint64_t idx; + + /* Start monitoring exerciser transactions */ + if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) + return AVS_STATUS_SKIP; + + run_flag = 1; + + /* Send the transaction on incrementalt addresses */ + for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) { + /* Write transaction */ + if (transaction_order[idx]) + val_mmio_write((addr_t)addr, TEST_DATA_4B); + else + val_mmio_read((addr_t)addr); + if (increment_addr) + addr++; + } + + /* Stop monitoring exerciser transactions */ + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + + return test_sequence_check(instance); +} + +/* Performs reads/write on 8B data */ +static uint32_t test_sequence_8B(uint64_t *addr, uint8_t increment_addr, uint32_t instance) +{ + uint64_t idx; + + /* Start monitoring exerciser transactions */ + if (val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance)) + return AVS_STATUS_SKIP; + + run_flag = 1; + + /* Send the transaction on incrementalt addresses */ + for (idx = 0; idx < sizeof(transaction_order)/sizeof(transaction_order[0]); idx++) { + /* Write transaction */ + if (transaction_order[idx]) + val_mmio_write64((addr_t)addr, TEST_DATA_8B); + else + val_mmio_read64((addr_t)addr); + if (increment_addr) + addr++; + } + + /* Stop monitoring exerciser transactions */ + val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance); + + return test_sequence_check(instance); +} + +/* Read and Write on config space mapped to Device memory */ + +static +void +cfgspace_transactions_order_check(void) +{ + uint32_t instance; + uint32_t bdf; + char *baseptr; + uint32_t cid_offset; + uint64_t bdf_addr; + + /* Read the number of excerciser cards */ + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + /* Get exerciser bdf */ + bdf = val_exerciser_get_bdf(instance); + + /* If exerciser doesn't have PCI_ECAP skip the bdf */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, CID_PCIECS, &cid_offset) == PCIE_CAP_NOT_FOUND) + continue; + + bdf_addr = val_pcie_get_bdf_config_addr(bdf); + + /* Map config space to ARM device memory in MMU page tables */ + baseptr = (char *)val_memory_ioremap((void *)bdf_addr, 512, DEVICE_nGnRnE); + + if (!baseptr) { + val_print(AVS_PRINT_ERR, "\n Failed in config ioremap for instance %x", instance); + continue; + } + + /* Test Scenario 1 : Transactions on aligned address */ + fail_cnt += test_sequence_1B((uint8_t *)baseptr, 1, instance); + fail_cnt += test_sequence_2B((uint16_t *)baseptr, 1, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, 1, instance); + + /* Test Scenario 2 : Transactions on PCIe misaligned address */ + baseptr += 1; + fail_cnt += test_sequence_2B((uint16_t *)baseptr, 1, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, 1, instance); + + /* Test Scenario 3 : Transactions on same address */ + fail_cnt += test_sequence_1B((uint8_t *)baseptr, 0, instance); + fail_cnt += test_sequence_2B((uint16_t *)baseptr, 0, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, 0, instance); + + /* Test Scenario 4 : Transactions on same misaligned PCIe address */ + baseptr += 3; + fail_cnt += test_sequence_2B((uint16_t *)baseptr, 0, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, 0, instance); + + } +} + +/* Read and Write on BAR space mapped to Device memory */ + +static +void +barspace_transactions_order_check(void) +{ + uint32_t instance; + exerciser_data_t e_data; + char *baseptr; + + /* Read the number of excerciser cards */ + instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0); + + while (instance-- != 0) { + + /* if init fail moves to next exerciser */ + if (val_exerciser_init(instance)) + continue; + + /* Get BAR 0 details for this instance */ + if (val_exerciser_get_data(EXERCISER_DATA_BAR0_SPACE, &e_data, instance)) { + val_print(AVS_PRINT_ERR, "\n Exerciser %d data read error ", instance); + continue; + } + + /* If BAR region is not Prefetchable, skip the exerciser */ + if (e_data.bar_space.type != MMIO_PREFETCHABLE) + continue; + + /* Map mmio space to ARM device memory in MMU page tables */ + baseptr = (char *)val_memory_ioremap((void *)e_data.bar_space.base_addr, 512, DEVICE_nGnRnE); + + if (!baseptr) { + val_print(AVS_PRINT_ERR, "\n Failed in BAR ioremap for instance %x", instance); + continue;; + } + + /* Test Scenario 1 : Transactions on aligned address */ + fail_cnt += test_sequence_1B((uint8_t *)baseptr, 1, instance); + fail_cnt += test_sequence_2B((uint16_t *)baseptr, 1, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, 1, instance); + fail_cnt += test_sequence_8B((uint64_t *)baseptr, 1, instance); + + /* Test Scenario 2 : Transactions on PCIe misaligned address */ + baseptr += 1; + fail_cnt += test_sequence_2B((uint16_t *)baseptr, 1, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, 1, instance); + fail_cnt += test_sequence_8B((uint64_t *)baseptr, 1, instance); + + /* Test Scenario 3 : Transactions on same address */ + fail_cnt += test_sequence_1B((uint8_t *)baseptr, 0, instance); + fail_cnt += test_sequence_2B((uint16_t *)baseptr, 0, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, 0, instance); + fail_cnt += test_sequence_8B((uint64_t *)baseptr, 0, instance); + + /* Test Scenario 4 : Transactions on same misaligned PCIe address */ + baseptr += 3; + fail_cnt += test_sequence_2B((uint16_t *)baseptr, 0, instance); + fail_cnt += test_sequence_4B((uint32_t *)baseptr, 0, instance); + fail_cnt += test_sequence_8B((uint64_t *)baseptr, 0, instance); + + } +} + +static +void +payload(void) +{ + uint32_t pe_index; + + pe_index = val_pe_get_index_mpid (val_pe_get_mpid()); + + cfgspace_transactions_order_check(); + barspace_transactions_order_check(); + + if(!run_flag) { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +e015_entry(void) +{ + uint32_t num_pe = 1; + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* Get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i003.c b/test_pool/io_virt/test_i003.c index 3720bedc..5d27999a 100755 --- a/test_pool/io_virt/test_i003.c +++ b/test_pool/io_virt/test_i003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -81,28 +81,11 @@ static void payload() val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); return; } - - data = val_smmu_read_cfg(SMMUv3_AIDR, num_smmu); - - if (g_sbsa_level < 5) { - if (((data & 0xFF) != 0) && ((data & 0xFF) != 0x1) && ((data & 0xFF) != 0x2)) { - val_print(AVS_PRINT_ERR, "\n\t Invalid Architecture Revision %x ", data); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); - return; - } - } else { - if ((data & 0xFF) < 0x2) { - /* Smmuv3.2 or higher not implemented */ - val_print(AVS_PRINT_ERR, "\n\t Level %x should support Smmuv3.2 or higher ", - g_sbsa_level); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); - return; - } - } } - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + } uint32_t diff --git a/test_pool/io_virt/test_i007.c b/test_pool/io_virt/test_i007.c new file mode 100755 index 00000000..8d375011 --- /dev/null +++ b/test_pool/io_virt/test_i007.c @@ -0,0 +1,90 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 7) +#define TEST_DESC "Check SMMU Version " + +static void payload() +{ + uint64_t data; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\nNo SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + if (g_sbsa_level > 3) { + val_print(AVS_PRINT_ERR, "\nSmmuv3 should be supported Level %x", g_sbsa_level); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } else { + /* Read SMMU Version */ + data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_AIDR, num_smmu), 0, 7); + + if (g_sbsa_level < 5) { + if ((data != 0) && (data != 0x1) && (data != 0x2)) { + val_print(AVS_PRINT_ERR, "\nInvalid Architecture Revision %x ", data); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + } else { + if (data < 0x2) { /* Smmuv3.2 or higher not implemented */ + val_print(AVS_PRINT_ERR, "\n\tLevel %x should support Smmuv3.2 or higher ", + g_sbsa_level); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + } + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +i007_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i008.c b/test_pool/io_virt/test_i008.c new file mode 100644 index 00000000..0045f83a --- /dev/null +++ b/test_pool/io_virt/test_i008.c @@ -0,0 +1,93 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 8) +#define TEST_DESC "Check SMMU 16 Bit VMID Support " + +static +void +payload() +{ + + uint64_t data; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 18, 18); + + if (data != 1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i008_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i009.c b/test_pool/io_virt/test_i009.c new file mode 100755 index 00000000..a363629a --- /dev/null +++ b/test_pool/io_virt/test_i009.c @@ -0,0 +1,93 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 9) +#define TEST_DESC "Check SMMU 16 Bit ASID Support " + +static +void +payload() +{ + + uint64_t data; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 12, 12); + + if (data != 1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i009_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i010.c b/test_pool/io_virt/test_i010.c new file mode 100644 index 00000000..1860897b --- /dev/null +++ b/test_pool/io_virt/test_i010.c @@ -0,0 +1,129 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 10) +#define TEST_DESC "Check SMMU Granule Support " + +static +void +payload() +{ + + uint64_t data; + uint64_t data_pe_mmfr0, data_smmu_idr5; + uint32_t is_gran4k = 0; + uint32_t is_gran64k = 0; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + data_pe_mmfr0 = val_pe_reg_read(ID_AA64MMFR0_EL1); + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + data_smmu_idr5 = val_smmu_read_cfg(SMMUv3_IDR5, num_smmu); + + /* If PE Supports 4KB Gran, (TGran4 == 0) or (TGran4_2 == 0x2) */ + if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 28, 31) == 0x0) || + (VAL_EXTRACT_BITS(data_pe_mmfr0, 40, 43) == 0x2)) { + is_gran4k = 1; + if (VAL_EXTRACT_BITS(data_smmu_idr5, 4, 4) != 1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + + /* If PE Supports 16KB Gran, (TGran16 == 1) or (TGran16_2 == 0x2) */ + if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 20, 23) == 0x1) || + (VAL_EXTRACT_BITS(data_pe_mmfr0, 32, 35) == 0x2)) { + if (VAL_EXTRACT_BITS(data_smmu_idr5, 5, 5) != 1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + } + + /* If PE Supports 64KB Gran, (TGran64 == 0) or (TGran64_2 == 0x2) */ + if ((VAL_EXTRACT_BITS(data_pe_mmfr0, 24, 27) == 0x0) || + (VAL_EXTRACT_BITS(data_pe_mmfr0, 36, 39) == 0x2)) { + is_gran64k = 1; + if (VAL_EXTRACT_BITS(data_smmu_idr5, 6, 6) != 1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + } + + /* If 4K & 64K Granule Not Supported */ + if (!(is_gran4k && is_gran64k)) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i010_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i011.c b/test_pool/io_virt/test_i011.c new file mode 100644 index 00000000..05cc1f5a --- /dev/null +++ b/test_pool/io_virt/test_i011.c @@ -0,0 +1,105 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 11) +#define TEST_DESC "Check Large Virtual Addr Support " + +static +void +payload() +{ + + uint64_t data; + uint64_t data_va_range, data_vax; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + data_va_range = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 16, 19); + if (data_va_range == 0) { + val_print(AVS_PRINT_WARN, "\n Large VA Not Supported by PE ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 05)); + return; + } + + data_vax = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR5, num_smmu), 10, 11); + + /* If PE Supports Large VA Range then SMMU_IDR5.VAX = 0b01 */ + if (data_va_range == 1) { + if (data_vax != 1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i011_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i012.c b/test_pool/io_virt/test_i012.c new file mode 100644 index 00000000..6526e3ca --- /dev/null +++ b/test_pool/io_virt/test_i012.c @@ -0,0 +1,105 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 12) +#define TEST_DESC "Check SMMU 52 Bit OAS Support " + +static +void +payload() +{ + + uint64_t data; + uint64_t data_pa_range, data_oas; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 3) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + data_pa_range = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR0_EL1), 0, 3); + if (data_pa_range != 0x6) { + val_print(AVS_PRINT_WARN, "\n Large PA Not Supported by PE ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 05)); + return; + } + + data_oas = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR5, num_smmu), 0, 2); + + /* If PE Supports Large PA then SMMU_IDR5.OAS = 0b110 */ + if (data_pa_range == 0x6) { + if (data_oas != 0x6) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i012_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i013.c b/test_pool/io_virt/test_i013.c new file mode 100644 index 00000000..ce399d1f --- /dev/null +++ b/test_pool/io_virt/test_i013.c @@ -0,0 +1,94 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 13) +#define TEST_DESC "Check SMMU Coherent Access Support" + +static +void +payload() +{ + + uint64_t data; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 4, 4); + + /* Check If SMMU_IDR0.COHACC == 1*/ + if (data != 1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i013_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i014.c b/test_pool/io_virt/test_i014.c new file mode 100644 index 00000000..9f4a65ed --- /dev/null +++ b/test_pool/io_virt/test_i014.c @@ -0,0 +1,94 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 14) +#define TEST_DESC "Check SMMU HTTU Support " + +static +void +payload() +{ + + uint64_t data; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 6, 7); + + /* Check If SMMU_IDR0.HTTU == 0b10 */ + if (data != 2) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i014_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i015.c b/test_pool/io_virt/test_i015.c new file mode 100644 index 00000000..a145b81a --- /dev/null +++ b/test_pool/io_virt/test_i015.c @@ -0,0 +1,107 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 15) +#define TEST_DESC "Check SMMU Endianess Support " + +static +void +payload() +{ + + uint64_t data; + uint64_t data_pe_endian; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* Check the current endianness setting of SCTLR.EE */ + if (val_pe_reg_read(CurrentEL) == AARCH64_EL2) { + data_pe_endian = VAL_EXTRACT_BITS(val_pe_reg_read(SCTLR_EL2), 25, 25); + } else if (val_pe_reg_read(CurrentEL) == AARCH64_EL1) { + data_pe_endian = VAL_EXTRACT_BITS(val_pe_reg_read(SCTLR_EL1), 25, 25); + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + data = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR0, num_smmu), 21, 22); + + if ((data_pe_endian == 1) && ((data == 1) || (data == 2))) { + /* If PE supports big endian */ + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } else if ((data_pe_endian == 0) && ((data == 1) || (data == 3))) { + /* If PE supports little endian */ + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i015_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/io_virt/test_i016.c b/test_pool/io_virt/test_i016.c new file mode 100644 index 00000000..87d207e8 --- /dev/null +++ b/test_pool/io_virt/test_i016.c @@ -0,0 +1,105 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_smmu.h" +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_SMMU_TEST_NUM_BASE + 16) +#define TEST_DESC "Check SMMU DVM Capability Support " + +static +void +payload() +{ + + uint64_t data; + uint64_t data_pe_tlb, data_ril; + uint32_t num_smmu; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); + + if (data == 0) { + val_print(AVS_PRINT_WARN, "\n PCIe Subsystem not discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + + if (num_smmu == 0) { + val_print(AVS_PRINT_ERR, "\n No SMMU Controllers are discovered ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + data_pe_tlb = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR0_EL1), 56, 59); + if (data_pe_tlb != 0x2) { + val_print(AVS_PRINT_WARN, "\n TLB Range Invalid Not Supported ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 04)); + return; + } + + while (num_smmu--) { + if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) { + val_print(AVS_PRINT_WARN, "\n Not valid for SMMU v2 ", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 05)); + return; + } + + data_ril = VAL_EXTRACT_BITS(val_smmu_read_cfg(SMMUv3_IDR3, num_smmu), 10, 10); + + /* If PE TLB Range Invalidation then SMMU_IDR3.RIL = 0b1 */ + if (data_pe_tlb == 0x2) { + if (data_ril != 0x1) { + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + } + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +i016_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p003.c b/test_pool/pcie/test_p003.c index 3d1e0b6d..2dd8fc06 100644 --- a/test_pool/pcie/test_p003.c +++ b/test_pool/pcie/test_p003.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -41,6 +41,7 @@ payload(void) uint32_t end_bus; uint32_t bus_index; uint32_t dev_index; + uint32_t func_index; uint32_t ret; num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0); @@ -73,28 +74,43 @@ payload(void) return; } + /* Accessing the BDF PCIe config range */ for(bus_index = bus; bus_index <= end_bus; bus_index++) { for(dev_index = 0; dev_index < PCIE_MAX_DEV; dev_index++) { - - /* Only function zero is checked */ - bdf = PCIE_CREATE_BDF(segment, bus_index, dev_index, 0); - ret = val_pcie_read_cfg(bdf, PCIE_VENDOR_ID_REG_OFFSET, &data); - - //If this is really PCIe CFG space, Device ID and Vendor ID cannot be 0 or 0xFFFF - if (ret == PCIE_NO_MAPPING || (data == 0) || ((data & 0xFFFF) == 0xFFFF)) { - val_print(AVS_PRINT_ERR, "\n Incorrect data at ECAM Base %4x ", data); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus_index << 8)|dev_index)); - return; - } - - ret = val_pcie_read_cfg(bdf, PCIE_CACHE_LINE_SIZE_REG_OFFSET, &data); - - //If this really is PCIe CFG, Header type[6:0] must be 01 or 00 - if (ret == PCIE_NO_MAPPING || (((data >> 16) & 0x7F) > 01)) { - val_print(AVS_PRINT_ERR, "\n Incorrect PCIe CFG Hdr type %4x ", data); - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus_index << 8)|dev_index)); - return; - } + for(func_index = 0; func_index < PCIE_MAX_FUNC; func_index++) { + + bdf = PCIE_CREATE_BDF(segment, bus_index, dev_index, func_index); + ret = val_pcie_read_cfg(bdf, PCIE_VENDOR_ID_REG_OFFSET, &data); + + //If this is really PCIe CFG space, Device ID and Vendor ID cannot be 0 + if (ret == PCIE_NO_MAPPING || (data == 0)) { + val_print(AVS_PRINT_ERR, "\n Incorrect data at ECAM Base %4x ", data); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus_index << 8)|dev_index)); + return; + } + + ret = val_pcie_read_cfg(bdf, PCIE_CACHE_LINE_SIZE_REG_OFFSET, &data); + if (ret == PCIE_NO_MAPPING) { + val_print(AVS_PRINT_ERR, "\n Incorrect PCIe CFG Hdr type %4x ", data); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus_index << 8)|dev_index)); + return; + } + + /* Accessing the PCIe Ext capability region */ + ret = val_pcie_read_cfg(bdf, PCIE_ECAP_START + 0x100, &data); + if (ret == PCIE_NO_MAPPING) { + val_print(AVS_PRINT_ERR, "\n PCIe Extended Capability region error for BDF %x", bdf); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus_index << 8)|dev_index)); + return; + } + + ret = val_pcie_read_cfg(bdf, PCIE_ECAP_END - 0x100, &data); + if (ret == PCIE_NO_MAPPING) { + val_print(AVS_PRINT_ERR, "\n PCIe Extended Capability region error for BDF %x", bdf); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, (bus_index << 8)|dev_index)); + return; + } + } } } } diff --git a/test_pool/pcie/test_p004.c b/test_pool/pcie/test_p004.c old mode 100755 new mode 100644 index aebaf87c..5056c28c --- a/test_pool/pcie/test_p004.c +++ b/test_pool/pcie/test_p004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -24,6 +24,8 @@ #define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 4) #define TEST_DESC "PCIe Unaligned access, Norm mem " +#define DATA 0xC0DECAFE + static void payload(void) @@ -31,21 +33,77 @@ payload(void) uint32_t count = 0; uint64_t base; uint32_t data; - char *baseptr; + uint32_t bdf; + uint32_t bar_reg_value; + uint32_t bar_value; + uint32_t bar_size; + char *baseptr; uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t test_skip = 1; + uint32_t test_fail = 0; - /* Map SATA Controller BARs to a NORMAL memory attribute. check unaligned access */ count = val_peripheral_get_info(NUM_SATA, 0); while (count--) { base = val_peripheral_get_info(SATA_BASE1, count); - baseptr = (char *)val_memory_ioremap((void *)base, 1024, 0); + bdf = val_peripheral_get_info(SATA_BDF, count); + + val_pcie_read_cfg(bdf, TYPE01_BAR, &bar_value); + val_print(AVS_PRINT_DEBUG, "\n The BAR value of bdf %x", bdf); + val_print(AVS_PRINT_DEBUG, " is %x ", bar_value); + + /* Determine the BAR size */ + val_pcie_write_cfg(bdf, TYPE01_BAR, 0xFFFFFFF0); + val_pcie_read_cfg(bdf, TYPE01_BAR, &bar_reg_value); + bar_reg_value = bar_reg_value & 0xFFFFFFF0; + bar_size = ~bar_reg_value + 1; + val_print(AVS_PRINT_DEBUG, "\n BAR size is %x", bar_size); + + /* Restore the original BAR value */ + val_pcie_write_cfg(bdf, TYPE01_BAR, bar_value); + + /* Check if bar supports the remap size */ + if (1024 > bar_size) { + val_print(AVS_PRINT_ERR, "Bar size less than remap requested size", 0); + continue; + } + + test_skip = 0; + + /* Map SATA Controller BARs to a NORMAL memory attribute. check unaligned access */ + baseptr = (char *)val_memory_ioremap((void *)base, 1024, NORMAL_NC); - data = *(uint32_t *)(baseptr+3); + /* Check for unaligned access */ + *(uint32_t *)(baseptr) = DATA; + data = *(char *)(baseptr+3); val_memory_unmap(baseptr); + + if (data != (DATA >> 24)) { + val_print(AVS_PRINT_ERR, "Unaligned data mismatch", 0); + test_fail++; + } + + /* Map SATA Controller BARs to a DEVICE memory attribute and check transaction */ + baseptr = (char *)val_memory_ioremap((void *)base, 1024, DEVICE_nGnRnE); + + *(uint32_t *)(baseptr) = DATA; + data = *(uint32_t *)(baseptr); + + val_memory_unmap(baseptr); + + if (data != DATA) { + val_print(AVS_PRINT_ERR, "Data value mismatch", 0); + test_fail++; + } } - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0)); + + if (test_skip) + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 0)); + else if (test_fail) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fail)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0)); } diff --git a/test_pool/pcie/test_p017.c b/test_pool/pcie/test_p017.c index bdf5b975..f7181ecf 100644 --- a/test_pool/pcie/test_p017.c +++ b/test_pool/pcie/test_p017.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -49,7 +49,7 @@ static void payload(void) pcie_type = val_pcie_get_pcie_type(dev_bdf); if (pcie_type == PCIE_TYPE_ROOT_PORT) { /* check if root port supports peer to peer */ - if (val_pcie_p2p_support(dev_bdf)) + if (val_pcie_dev_p2p_support(dev_bdf)) continue; valid_cnt++; diff --git a/test_pool/pcie/test_p018.c b/test_pool/pcie/test_p018.c index 170b02e8..c7c555f3 100644 --- a/test_pool/pcie/test_p018.c +++ b/test_pool/pcie/test_p018.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -49,7 +49,7 @@ static void payload(void) pcie_type = val_pcie_get_pcie_type(dev_bdf); if (pcie_type == PCIE_TYPE_DOWNSTREAM) { /* check if switch supports peer to peer */ - if (val_pcie_p2p_support(dev_bdf)) + if (val_pcie_dev_p2p_support(dev_bdf)) continue; valid_cnt++; diff --git a/test_pool/pcie/test_p019.c b/test_pool/pcie/test_p019.c index 57763204..e424f12c 100644 --- a/test_pool/pcie/test_p019.c +++ b/test_pool/pcie/test_p019.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -56,7 +56,7 @@ static void payload(void) continue; /* check if PCIe device supports peer to peer */ - if (val_pcie_p2p_support(dev_bdf)) + if (val_pcie_dev_p2p_support(dev_bdf)) continue; valid_cnt++; diff --git a/test_pool/pcie/test_p045.c b/test_pool/pcie/test_p045.c index f37689bf..15d4991c 100644 --- a/test_pool/pcie/test_p045.c +++ b/test_pool/pcie/test_p045.c @@ -41,6 +41,11 @@ payload(void) uint16_t vendor_id; uint32_t device_id; uint32_t test_skip = 1; + uint32_t test_fail = 0; + uint32_t segment; + uint32_t rp_ecam_base; + uint32_t rp_segment; + pcie_device_bdf_table *bdf_tbl_ptr; tbl_index = 0; @@ -48,40 +53,50 @@ payload(void) bdf_tbl_ptr = val_pcie_bdf_table_ptr(); pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); - while (ecam_index < val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0)) + while (tbl_index < bdf_tbl_ptr->num_entries) { - ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, ecam_index); - val_print(AVS_PRINT_DEBUG, "\n RPs under ECAM Base 0x%x :", ecam_base); + next_bdf: + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); - while (tbl_index < bdf_tbl_ptr->num_entries) + if (dp_type == RP || dp_type == iEP_RP) { - bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + test_skip = 0; + ecam_index = 0; + + val_pcie_read_cfg(bdf, TYPE01_VIDR, ®_value); + device_id = (reg_value >> TYPE01_DIDR_SHIFT) & TYPE01_DIDR_MASK; + vendor_id = (reg_value >> TYPE01_VIDR_SHIFT) & TYPE01_VIDR_MASK; + val_print(AVS_PRINT_DEBUG, "\n BDF: 0x%x ", bdf); + val_print(AVS_PRINT_DEBUG, "Dev ID: 0x%x ", device_id); + val_print(AVS_PRINT_DEBUG, "Vendor ID: 0x%x", vendor_id); + + rp_ecam_base = val_pcie_get_ecam_base(bdf); + rp_segment = PCIE_EXTRACT_BDF_SEG(bdf); - dp_type = val_pcie_device_port_type(bdf); - if (dp_type == RP || dp_type == iEP_RP) + while (ecam_index < val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0)) { - /* If test runs for atleast an endpoint */ - test_skip = 0; + ecam_base = val_pcie_get_info(PCIE_INFO_ECAM, ecam_index); + segment = val_pcie_get_info(PCIE_INFO_SEGMENT, ecam_index); - if (ecam_base == val_pcie_get_ecam_base(bdf)) + if (ecam_base == rp_ecam_base && segment == rp_segment) { - val_pcie_read_cfg(bdf, TYPE01_VIDR, ®_value); - device_id = (reg_value >> TYPE01_DIDR_SHIFT) & TYPE01_DIDR_MASK; - vendor_id = (reg_value >> TYPE01_VIDR_SHIFT) & TYPE01_VIDR_MASK; - - val_print(AVS_PRINT_DEBUG, "\n BDF: 0x%x ", bdf); - val_print(AVS_PRINT_DEBUG, "Dev ID: 0x%x ", device_id); - val_print(AVS_PRINT_DEBUG, "Vendor ID: 0x%x", vendor_id); + val_print(AVS_PRINT_DEBUG, "\n ECAM base 0x%x matches with RPs base address", ecam_base); + goto next_bdf; } + + ecam_index++; } + val_print(AVS_PRINT_ERR, "\n RP BDF 0x%x not under any HB", bdf); + test_fail++; } - - ecam_index++; } if (test_skip == 1) val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (test_fail) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fail)); else val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); } diff --git a/test_pool/pcie/test_p046.c b/test_pool/pcie/test_p046.c new file mode 100644 index 00000000..07d937d0 --- /dev/null +++ b/test_pool/pcie/test_p046.c @@ -0,0 +1,168 @@ +/** @file + * Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 46) +#define TEST_DESC "Check RP Byte Enable Rules " + +static +void +payload(void) +{ + + int8_t i; + uint32_t bdf; + uint32_t dp_type; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t test_skip = 1; + uint32_t ecam_cr, ecam_cr_8, ecam_cr_16, ecam_cr_new; + uint32_t write_value = 0; + uint32_t command_reg_offset; + addr_t ecam_base; + pcie_device_bdf_table *bdf_tbl_ptr; + + tbl_index = 0; + ecam_cr = 0; + ecam_cr_8 = 0; + ecam_cr_16 = 0; + ecam_cr_new = 0; + + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + if ((dp_type == RP) || (dp_type == iEP_RP)) { + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + ecam_base = val_pcie_get_ecam_base(bdf); + command_reg_offset = PCIE_EXTRACT_BDF_BUS(bdf) * PCIE_MAX_DEV * PCIE_MAX_FUNC * PCIE_CFG_SIZE + + PCIE_EXTRACT_BDF_DEV(bdf) * PCIE_MAX_FUNC * PCIE_CFG_SIZE + + PCIE_EXTRACT_BDF_FUNC(bdf) * PCIE_CFG_SIZE + + TYPE01_CR; + + /* Read Command Register of RP with 8 Bit, 16 Bit, 32 Bit and compare it */ + ecam_cr = val_mmio_read(ecam_base + command_reg_offset); + for (i = 3; i >= 0; i--) { + ecam_cr_8 = ecam_cr_8 << 8; + ecam_cr_8 |= val_mmio_read8(ecam_base + command_reg_offset + i); + } + for (i = 1; i >= 0; i--) { + ecam_cr_16 = ecam_cr_16 << 16; + ecam_cr_16 |= val_mmio_read16(ecam_base + command_reg_offset + i*2); + } + + if ((ecam_cr != ecam_cr_8) || (ecam_cr_8 != ecam_cr_16)) + { + val_print(AVS_PRINT_ERR, "\n Byte Enable Read Failed", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Check Read-Write-Read Behaviour for each 8 Bit */ + ecam_cr = val_mmio_read8(ecam_base + command_reg_offset); + + /* Change BME & MSE Bit Value */ + write_value = ecam_cr ^ ((1 << CR_MSE_SHIFT) | (1 << CR_BME_SHIFT)); + val_mmio_write8(ecam_base + command_reg_offset, write_value); + + ecam_cr_new = val_mmio_read8(ecam_base + command_reg_offset); + if (write_value != ecam_cr_new) + { + val_print(AVS_PRINT_ERR, "\n 8 Bit Write Failed", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Restore the value */ + val_mmio_write8(ecam_base + command_reg_offset, ecam_cr); + + /* Check Read-Write-Read Behaviour for each 16 Bit */ + ecam_cr = val_mmio_read16(ecam_base + command_reg_offset); + + /* Change BME & MSE Bit Value */ + write_value = ecam_cr ^ ((1 << CR_MSE_SHIFT) | (1 << CR_BME_SHIFT)); + val_mmio_write16(ecam_base + command_reg_offset, write_value); + + ecam_cr_new = val_mmio_read16(ecam_base + command_reg_offset); + if (write_value != ecam_cr_new) + { + val_print(AVS_PRINT_ERR, "\n 16 Bit Write Failed", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + + /* Restore the value */ + val_mmio_write16(ecam_base + command_reg_offset, ecam_cr); + + /* Check Read-Write-Read Behaviour for 32 Bit */ + ecam_cr = val_mmio_read(ecam_base + command_reg_offset); + + /* Change BME & MSE Bit Value */ + write_value = ecam_cr ^ ((1 << CR_MSE_SHIFT) | (1 << CR_BME_SHIFT)); + val_mmio_write(ecam_base + command_reg_offset, write_value); + + ecam_cr_new = val_mmio_read(ecam_base + command_reg_offset); + if (write_value != ecam_cr_new) + { + val_print(AVS_PRINT_ERR, "\n 32 Bit Write Failed", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + + /* Restore the value */ + val_mmio_write(ecam_base + command_reg_offset, ecam_cr); + + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p046_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p047.c b/test_pool/pcie/test_p047.c new file mode 100644 index 00000000..0fde1636 --- /dev/null +++ b/test_pool/pcie/test_p047.c @@ -0,0 +1,114 @@ +/** @file + * Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 47) +#define TEST_DESC "Check Config Txn for RP in HB " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t Status; + uint32_t dp_type; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t fail_cnt; + uint32_t test_skip = 1; + uint32_t ecam_cc; + uint32_t pciio_proto_cc; + addr_t ecam_base; + pcie_device_bdf_table *bdf_tbl_ptr; + + fail_cnt = 0; + tbl_index = 0; + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + /* + * Check that Host Bridge Consumes the Configuration + * request intended for RootPort Configuration space. + * Access RootPort Config Space using ECAM Method. + */ + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + if ((dp_type == RP) || (dp_type == iEP_RP)) { + /* Read Vendor ID of RP with ECAM based mechanism, and compare it with the */ + ecam_base = val_pcie_get_ecam_base(bdf); + + /* Read Function's Class Code through ECAM method */ + ecam_cc = val_mmio_read(ecam_base + + PCIE_EXTRACT_BDF_BUS(bdf) * PCIE_MAX_DEV * PCIE_MAX_FUNC * PCIE_CFG_SIZE + + PCIE_EXTRACT_BDF_DEV(bdf) * PCIE_MAX_FUNC * PCIE_CFG_SIZE + + PCIE_EXTRACT_BDF_FUNC(bdf) * PCIE_CFG_SIZE + + TYPE01_RIDR); + + /* Read Function's Class Code through Pciio Protocol method */ + Status = val_pcie_io_read_cfg(bdf, TYPE01_RIDR, &pciio_proto_cc); + if (Status == PCIE_NO_MAPPING) { + val_print(AVS_PRINT_ERR, "\n Reading Class code using PciIo protocol failed ", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + if (ecam_cc != pciio_proto_cc) + { + val_print(AVS_PRINT_ERR, "\n Config Txn Error : 0x%x ", bdf); + fail_cnt++; + } + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (fail_cnt) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p047_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p048.c b/test_pool/pcie/test_p048.c new file mode 100644 index 00000000..0142955f --- /dev/null +++ b/test_pool/pcie/test_p048.c @@ -0,0 +1,152 @@ +/** @file + * Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 48) +#define TEST_DESC "Check RootPort NP Memory Access " + +#define KNOWN_DATA 0xABABABAB + +static void *branch_to_test; + +static +void +esr(uint64_t interrupt_type, void *context) +{ + uint32_t pe_index; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Update the ELR to return to test specified address */ + val_pe_update_elr(context, (uint64_t)branch_to_test); + + val_print(AVS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t dp_type; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t read_value; + uint32_t test_skip = 1; + uint64_t mem_base; + pcie_device_bdf_table *bdf_tbl_ptr; + + tbl_index = 0; + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Install sync and async handlers to handle exceptions.*/ + val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + branch_to_test = &&exception_return; + + /* Since this is a memory space access test. + * Enable BME & MSE for all the BDFs. + */ + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + /* Enable Bus Master Enable */ + val_pcie_enable_bme(bdf); + /* Enable Memory Space Access */ + val_pcie_enable_msa(bdf); + } + + tbl_index = 0; + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + if ((dp_type == RP) || (dp_type == iEP_RP)) { + /* Part 1: + * Check When Address is within the Range of Non-Prefetchable + * Memory Range. + */ + /* Clearing UR in Device Status Register */ + val_pcie_clear_urd(bdf); + + /* Read Function's NP Memory Base Limit Register */ + val_pcie_read_cfg(bdf, TYPE1_NP_MEM, &read_value); + + mem_base = (read_value & MEM_BA_MASK) << MEM_BA_SHIFT; + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + /* Write known value to an address which is in range + * Base + 0x10 will always be in the range. + * Read the same + */ + *(volatile uint32_t *)(mem_base + MEM_OFFSET_10) = KNOWN_DATA; + read_value = (*(volatile uint32_t *)(mem_base + MEM_OFFSET_10)); + +exception_return: + /* Memory Space might have constraint on RW/RO behaviour + * So not checking for Read-Write Data mismatch. + */ + if (IS_TEST_FAIL(val_get_status(pe_index))) { + val_print(AVS_PRINT_ERR, "\n Failed. Exception on Memory Access For Bdf : 0x%x", bdf); + val_pcie_clear_urd(bdf); + return; + } + + if ((read_value == PCIE_UNKNOWN_RESPONSE) || val_pcie_is_urd(bdf)) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + val_pcie_clear_urd(bdf); + return; + } + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p048_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p049.c b/test_pool/pcie/test_p049.c new file mode 100644 index 00000000..fb65735a --- /dev/null +++ b/test_pool/pcie/test_p049.c @@ -0,0 +1,171 @@ +/** @file + * Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 49) +#define TEST_DESC "Check RootPort P Memory Access " + +#define KNOWN_DATA 0xABABABAB + +static void *branch_to_test; + +static +void +esr(uint64_t interrupt_type, void *context) +{ + uint32_t pe_index; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Update the ELR to return to test specified address */ + val_pe_update_elr(context, (uint64_t)branch_to_test); + + val_print(AVS_PRINT_INFO, "\n Received exception of type: %d", interrupt_type); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); +} + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t dp_type; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t read_value; + uint32_t test_skip = 1; + uint64_t mem_base = 0, mem_base_upper = 0; + uint64_t mem_lim = 0, mem_lim_upper = 0; + pcie_device_bdf_table *bdf_tbl_ptr; + + tbl_index = 0; + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Install sync and async handlers to handle exceptions.*/ + val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); + val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); + branch_to_test = &&exception_return; + + /* Since this is a memory space access test. + * Enable BME & MSE for all the BDFs. + */ + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + /* Enable Bus Master Enable */ + val_pcie_enable_bme(bdf); + /* Enable Memory Space Access */ + val_pcie_enable_msa(bdf); + } + + tbl_index = 0; + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + if ((dp_type == RP) || (dp_type == iEP_RP)) { + /* Part 1: + * Check When Address is within the Range of Prefetchable + * Memory Range. + */ + /* Clearing UR in Device Status Register */ + val_pcie_clear_urd(bdf); + + /* Read Function's Memory Base Limit Register */ + val_pcie_read_cfg(bdf, TYPE1_P_MEM, &read_value); + if (read_value == 0) + continue; + + mem_base = (read_value & MEM_BA_MASK) << MEM_BA_SHIFT; + mem_lim = (read_value & MEM_LIM_MASK) | MEM_LIM_LOWER_BITS; + + /* If 64 Bit Prefetchable Address */ + if ((read_value & P_MEM_PAC_MASK) == 0x1) { + val_pcie_read_cfg(bdf, TYPE1_P_MEM_BU, &read_value); + mem_base_upper = read_value; + val_pcie_read_cfg(bdf, TYPE1_P_MEM_LU, &read_value); + mem_lim_upper = read_value; + } + + mem_base |= (mem_base_upper << P_MEM_BU_SHIFT); + mem_lim |= (mem_lim_upper << P_MEM_LU_SHIFT); + + /* If Memory Limit is programmed with value less the Base, then Skip.*/ + if (mem_lim < mem_base) + continue; + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + /* Write known value to an address which is in range + * Base + 0x10 will always be in the range. + * Read the same + */ + *(volatile addr_t *)(mem_base + MEM_OFFSET_10) = KNOWN_DATA; + read_value = (*(volatile addr_t *)(mem_base + MEM_OFFSET_10)); + +exception_return: + /* Memory Space might have constraint on RW/RO behaviour + * So not checking for Read-Write Data mismatch. + */ + if (IS_TEST_FAIL(val_get_status(pe_index))) { + val_print(AVS_PRINT_ERR, "\n Failed. Exception on Memory Access For Bdf : 0x%x", bdf); + val_pcie_clear_urd(bdf); + return; + } + + if ((read_value == PCIE_UNKNOWN_RESPONSE) || val_pcie_is_urd(bdf)) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + val_pcie_clear_urd(bdf); + return; + } + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p049_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p050.c b/test_pool/pcie/test_p050.c new file mode 100644 index 00000000..08371bbd --- /dev/null +++ b/test_pool/pcie/test_p050.c @@ -0,0 +1,115 @@ +/** @file + * Copyright (c) 2020 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 50) +#define TEST_DESC "Check L-Intr SPI Level-Sensitive " + +static +void +payload(void) +{ + uint32_t status; + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t reg_value; + uint32_t test_skip = 1; + uint32_t intr_pin, intr_line; + PERIPHERAL_IRQ_MAP *intr_map; + pcie_device_bdf_table *bdf_tbl_ptr; + INTR_TRIGGER_INFO_TYPE_e trigger_type; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Allocate memory for interrupt mappings */ + intr_map = val_memory_alloc(sizeof(PERIPHERAL_IRQ_MAP)); + if (!intr_map) { + val_print (AVS_PRINT_ERR, "\n Memory allocation error", 0); + val_set_status(pe_index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 01)); + return; + } + + tbl_index = 0; + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + + /* Read Interrupt Line Register */ + val_pcie_read_cfg(bdf, TYPE01_ILR, ®_value); + + intr_pin = (reg_value >> TYPE01_IPR_SHIFT) & TYPE01_IPR_MASK; + if ((intr_pin == 0) || (intr_pin > 0x4)) + continue; + + status = val_pci_get_legacy_irq_map(bdf, intr_map); + if (status) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + intr_line = intr_map->legacy_irq_map[intr_pin-1].irq_list[0]; + + /* Read GICD_ICFGR register to Check for Level/Edge Sensitive. */ + status = val_gic_get_intr_trigger_type(intr_line, &trigger_type); + if (status) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 03)); + return; + } + + if (trigger_type != INTR_TRIGGER_INFO_LEVEL_HIGH) { + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 04)); + return; + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p050_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p051.c b/test_pool/pcie/test_p051.c new file mode 100644 index 00000000..25e9f317 --- /dev/null +++ b/test_pool/pcie/test_p051.c @@ -0,0 +1,204 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 51) +#define TEST_DESC "Check Sec Bus Reset For iEP_RP " + +uint32_t +get_iep_bdf_under_rp (uint32_t rp_bdf) +{ + uint32_t reg_value; + uint32_t sec_bus; + uint32_t dev_num; + uint32_t seg; + uint32_t dev_bdf; + uint32_t dp_type; + + /* Read Secondary Bus from Config Space */ + val_pcie_read_cfg(rp_bdf, TYPE1_PBN, ®_value); + sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK); + + /* Find iEP_EP device type under iEP_RP */ + for (dev_num = 0; dev_num < PCIE_MAX_DEV; dev_num++) { + seg = PCIE_EXTRACT_BDF_SEG(rp_bdf); + + /* Create bdf for Dev 0 to 31 below the iEP_RP */ + dev_bdf = PCIE_CREATE_BDF(seg, sec_bus, dev_num, 0); + + val_pcie_read_cfg(dev_bdf, TYPE01_VIDR, ®_value); + if (reg_value == PCIE_UNKNOWN_RESPONSE) + continue; + + dp_type = val_pcie_device_port_type(dev_bdf); + if (dp_type == iEP_EP) + return dev_bdf; + } + + /* Could not find iEP */ + return 0x0; +} + +uint32_t +is_sbr_failed (uint32_t bdf) +{ + uint32_t reg_value; + uint32_t index; + uint32_t check_failed; + + check_failed = 0; + /* Check BAR base address is cleared */ + for (index = 0; index < TYPE0_MAX_BARS; index++) { + + val_pcie_read_cfg(bdf, TYPE01_BAR + (index * BAR_BASE_SHIFT), ®_value); + if ((reg_value >> BAR_BASE_SHIFT) != 0) { + val_print(AVS_PRINT_ERR, "\n BAR%d base addr not cleared", index); + check_failed++; + } + } + + /* Check the Bus Master Enable bit & Memory Space Enable + * bit is cleared + */ + val_pcie_read_cfg(bdf, TYPE01_CR, ®_value); + if ((((reg_value >> CR_BME_SHIFT) & CR_BME_MASK) != 0) || + (((reg_value >> CR_MSE_SHIFT) & CR_MSE_MASK) != 0)) + { + val_print(AVS_PRINT_ERR, "\n BME/MSE not cleared", 0); + check_failed++; + } + + return check_failed; +} + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t iep_bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t reg_value; + uint32_t iep_rp_found; + uint32_t test_fails; + void *cfg_space_buf; + addr_t cfg_space_addr; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + tbl_index = 0; + test_fails = 0; + iep_rp_found = 0; + cfg_space_buf = NULL; + + /* Check for all the function present in bdf table */ + while (tbl_index < bdf_tbl_ptr->num_entries) + { + bdf = bdf_tbl_ptr->device[tbl_index++].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is iEP_RP */ + if (dp_type == iEP_RP) + { + iep_rp_found = 1; + + /* Get BDF for iEP_EP under iEP_RP */ + iep_bdf = get_iep_bdf_under_rp(bdf); + if (iep_bdf == 0x0) { + val_print(AVS_PRINT_ERR, "\n Could Not Find iEP_EP under iEP_RP.", 0); + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Allocate 4KB of space for saving function configuration space */ + /* If memory allocation fail, fail the test */ + cfg_space_buf = val_memory_alloc(PCIE_CFG_SIZE); + if (cfg_space_buf == NULL) + { + val_print(AVS_PRINT_ERR, "\n Memory allocation failed.", 0); + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Get configuration space address for iEP_EP */ + cfg_space_addr = val_pcie_get_bdf_config_addr(iep_bdf); + val_print(AVS_PRINT_INFO, "\n iEP_EP BDF 0x%x : ", iep_bdf); + val_print(AVS_PRINT_INFO, "Config space addr 0x%x", cfg_space_addr); + + /* Save the iEP_EP config space to restore after Secondary Bus Reset */ + val_memcpy(cfg_space_buf, (void *)cfg_space_addr, PCIE_CFG_SIZE); + + /* Set Secondary Bus Reset Bit in Bridge Control + * Register of iEP_RP + */ + val_pcie_read_cfg(bdf, TYPE01_ILR, ®_value); + reg_value = reg_value | BRIDGE_CTRL_SBR_SET; + val_pcie_write_cfg(bdf,TYPE01_ILR, reg_value); + + /* Wait for Timeout */ + val_time_delay_ms(100 * ONE_MILLISECOND); + + /* Check whether iEP_RP Secondary Bus Reset works fine. */ + if (is_sbr_failed(iep_bdf)) { + test_fails++; + } + + /* Restore iEP_EP Config Space */ + val_memcpy((void *)cfg_space_addr, cfg_space_buf, PCIE_CFG_SIZE); + val_memory_free(cfg_space_buf); + } + } + + /* Skip the test if no iEP_RP found */ + if (iep_rp_found == 0) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p051_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p052.c b/test_pool/pcie/test_p052.c new file mode 100644 index 00000000..cf87298d --- /dev/null +++ b/test_pool/pcie/test_p052.c @@ -0,0 +1,103 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 52) +#define TEST_DESC "Check ATS Support Rule " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base; + uint32_t test_skip; + uint32_t test_fails; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + test_skip = 1; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Skip this Check for Host Bridge */ + if (val_pcie_is_host_bridge(bdf)) + continue; + + /* Check entry is integrated endpoint or rciep */ + if ((dp_type == iEP_EP) || (dp_type == RCiEP)) + { + /* Check if Address Translation Cache is Present in this device. */ + /* If ATC Not present, skip the test.*/ + if (!val_pcie_is_cache_present(bdf)) + continue; + + test_skip = 0; + + /* If ATC Present, Check ATS Capability should be present. */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS) + { + val_print(AVS_PRINT_ERR, "\n ATS Capability Not Present, Bdf : 0x%x", bdf); + test_fails++; + } + } + } + + if (test_skip) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p052_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p053.c b/test_pool/pcie/test_p053.c new file mode 100644 index 00000000..0712e584 --- /dev/null +++ b/test_pool/pcie/test_p053.c @@ -0,0 +1,143 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 53) +#define TEST_DESC "Check RootPort P2P Support " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base = 0; + uint32_t test_fails; + uint32_t test_skip = 1; + uint32_t acs_data; + uint32_t data; + uint32_t curr_bdf_failed = 0; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Check If PCIe Hierarchy supports P2P */ + if (val_pcie_p2p_support()) + { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is RP */ + if (dp_type == RP) + { + /* Test runs for atleast an endpoint */ + test_skip = 0; + + /* Read the ACS Capability */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); + test_fails++; + continue; + } + + val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, &acs_data); + + /* Extract ACS source validation bit */ + data = VAL_EXTRACT_BITS(acs_data, 0, 0); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Source validation not supported, Bdf : 0x%x", bdf); + curr_bdf_failed++; + } + /* Extract ACS translation blocking bit */ + data = VAL_EXTRACT_BITS(acs_data, 1, 1); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Translation blocking not supported, Bdf : 0x%x", bdf); + curr_bdf_failed++; + } + /* Extract ACS P2P request redirect bit */ + data = VAL_EXTRACT_BITS(acs_data, 2, 2); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n P2P request redirect not supported, Bdf : 0x%x", bdf); + curr_bdf_failed++; + } + /* Extract ACS P2P completion redirect bit */ + data = VAL_EXTRACT_BITS(acs_data, 3, 3); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n P2P completion redirect not supported, Bdf : 0x%x", bdf); + curr_bdf_failed++; + } + /* Extract ACS upstream forwarding bit */ + data = VAL_EXTRACT_BITS(acs_data, 4, 4); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Upstream forwarding not supported, Bdf : 0x%x", bdf); + curr_bdf_failed++; + } + + if(curr_bdf_failed > 0) { + val_print(AVS_PRINT_ERR, "\n ACS Capability Check Failed, Bdf : 0x%x", bdf); + curr_bdf_failed = 0; + test_fails++; + } + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p053_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p054.c b/test_pool/pcie/test_p054.c new file mode 100644 index 00000000..4f5c3840 --- /dev/null +++ b/test_pool/pcie/test_p054.c @@ -0,0 +1,107 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 54) +#define TEST_DESC "Check RP Adv Error Report Support " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base = 0; + uint32_t test_fails; + uint32_t test_skip = 1; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Check If PCIe Hierarchy supports P2P */ + if (val_pcie_p2p_support()) + { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is RP */ + if (dp_type == RP) + { + /* Test runs for atleast an endpoint */ + test_skip = 0; + + /* It ACS Not Supported, Fail. */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); + test_fails++; + continue; + } + + /* If AER Not Supported, Fail. */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS) { + val_print(AVS_PRINT_DEBUG, "\n AER Capability not supported, Bdf : 0x%x", bdf); + test_fails++; + } + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p054_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p055.c b/test_pool/pcie/test_p055.c new file mode 100644 index 00000000..faea79fe --- /dev/null +++ b/test_pool/pcie/test_p055.c @@ -0,0 +1,115 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 55) +#define TEST_DESC "Check Direct Translated P2P Supp " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base = 0; + uint32_t test_fails; + uint32_t test_skip = 1; + uint32_t acs_data; + uint32_t data; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is RP */ + if (dp_type == RP) + { + /* Check If RP supports P2P with other RP's. */ + if (val_pcie_dev_p2p_support(bdf)) + continue; + + /* It ATS Not supported, Skip the BDF. */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS) { + continue; + } + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + val_print(AVS_PRINT_DEBUG, "\n For BDF : 0x%x", bdf); + + /* Read the ACS Capability */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) { + val_print(AVS_PRINT_ERR, "\n ACS Capability not supported, Bdf : 0x%x", bdf); + test_fails++; + continue; + } + val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, &acs_data); + + /* Extract ACS directed translated p2p bit */ + data = VAL_EXTRACT_BITS(acs_data, 6, 6); + if (data == 0) { + val_print(AVS_PRINT_ERR, "\n Directed Translated P2P not supported, Bdf : 0x%x", bdf); + test_fails++; + } + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p055_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p056.c b/test_pool/pcie/test_p056.c new file mode 100644 index 00000000..286eed9a --- /dev/null +++ b/test_pool/pcie/test_p056.c @@ -0,0 +1,164 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 56) +#define TEST_DESC "Check iEP-RootPort P2P Support " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base = 0; + uint32_t test_fails; + uint32_t test_skip = 1; + uint32_t acs_data; + uint32_t data; + uint32_t iep_rp_bdf; + uint32_t curr_bdf_failed = 0; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + + /* Check If PCIe Hierarchy supports P2P */ + if (val_pcie_p2p_support()) + { + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is iEP_EP */ + if (dp_type == iEP_EP) + { + /* Check If iEP_EP supports P2P with others. */ + if (val_pcie_dev_p2p_support(bdf)) + continue; + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + /* Find iEP_RP for this iEP_EP */ + if (val_pcie_get_rootport(bdf, &iep_rp_bdf)) + { + val_print(AVS_PRINT_ERR, "\n Root Port Not found for iEP_EP 0x%x", bdf); + test_fails++; + continue; + } + + /* Read the ACS Capability */ + if (val_pcie_find_capability(iep_rp_bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) + { + val_print(AVS_PRINT_ERR, "\n ACS Capability not supported, Bdf : 0x%x", iep_rp_bdf); + test_fails++; + continue; + } + + val_pcie_read_cfg(iep_rp_bdf, cap_base + ACSCR_OFFSET, &acs_data); + + /* Extract ACS source validation bit */ + data = VAL_EXTRACT_BITS(acs_data, 0, 0); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Source validation not supported, Bdf : 0x%x", iep_rp_bdf); + curr_bdf_failed++; + } + /* Extract ACS translation blocking bit */ + data = VAL_EXTRACT_BITS(acs_data, 1, 1); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Translation blocking not supported, Bdf : 0x%x", iep_rp_bdf); + curr_bdf_failed++; + } + /* Extract ACS P2P request redirect bit */ + data = VAL_EXTRACT_BITS(acs_data, 2, 2); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n P2P request redirect not supported, Bdf : 0x%x", iep_rp_bdf); + curr_bdf_failed++; + } + /* Extract ACS P2P completion redirect bit */ + data = VAL_EXTRACT_BITS(acs_data, 3, 3); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n P2P completion redirect not supported, Bdf : 0x%x", iep_rp_bdf); + curr_bdf_failed++; + } + /* Extract ACS upstream forwarding bit */ + data = VAL_EXTRACT_BITS(acs_data, 4, 4); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Upstream forwarding not supported, Bdf : 0x%x", iep_rp_bdf); + curr_bdf_failed++; + } + + /* If iEP_RP supports ACS then it should have AER Capability */ + if (val_pcie_find_capability(iep_rp_bdf, PCIE_ECAP, ECID_AER, &cap_base) != PCIE_SUCCESS) + { + val_print(AVS_PRINT_DEBUG, "\n AER Capability not supported, Bdf : 0x%x", iep_rp_bdf); + curr_bdf_failed++; + } + + if(curr_bdf_failed > 0) { + val_print(AVS_PRINT_ERR, "\n ACS Capability Check Failed, Bdf : 0x%x", iep_rp_bdf); + curr_bdf_failed = 0; + test_fails++; + } + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p056_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pcie/test_p057.c b/test_pool/pcie/test_p057.c new file mode 100644 index 00000000..43a90d05 --- /dev/null +++ b/test_pool/pcie/test_p057.c @@ -0,0 +1,134 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_pcie.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/sbsa_avs_memory.h" + +#define TEST_NUM (AVS_PCIE_TEST_NUM_BASE + 57) +#define TEST_DESC "Check RCiEP, iEP_EP P2P Supp " + +static +void +payload(void) +{ + + uint32_t bdf; + uint32_t pe_index; + uint32_t tbl_index; + uint32_t dp_type; + uint32_t cap_base = 0; + uint32_t test_fails; + uint32_t test_skip = 1; + uint32_t acs_data; + uint32_t data; + uint8_t p2p_support_flag=0; + pcie_device_bdf_table *bdf_tbl_ptr; + + pe_index = val_pe_get_index_mpid(val_pe_get_mpid()); + bdf_tbl_ptr = val_pcie_bdf_table_ptr(); + + test_fails = 0; + + /* Check for all the function present in bdf table */ + for (tbl_index = 0; tbl_index < bdf_tbl_ptr->num_entries; tbl_index++) + { + bdf = bdf_tbl_ptr->device[tbl_index].bdf; + dp_type = val_pcie_device_port_type(bdf); + + /* Check entry is RCiEP or iEP end point */ + if ((dp_type == RCiEP) || (dp_type == iEP_EP)) + { + /* Check if the EP Supports Multifunction */ + if(!val_pcie_multifunction_support(bdf)) + continue; + + /* Check If Endpoint supports P2P with other Functions. */ + if (val_pcie_dev_p2p_support(bdf)) + continue; + + /* If ATS Not supported, Skip the BDF. */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ATS, &cap_base) != PCIE_SUCCESS) + continue; + + /* If test runs for atleast an endpoint */ + test_skip = 0; + + /* Read the ACS Capability */ + if (val_pcie_find_capability(bdf, PCIE_ECAP, ECID_ACS, &cap_base) != PCIE_SUCCESS) + { + test_fails++; + continue; + } + val_pcie_read_cfg(bdf, cap_base + ACSCR_OFFSET, &acs_data); + + /* Extract ACS p2p Request Redirect bit */ + data = VAL_EXTRACT_BITS(acs_data, 2, 2); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Request Redirect P2P not supported", 0); + p2p_support_flag++; + } + /* Extract ACS p2p Completion Redirect bit */ + data = VAL_EXTRACT_BITS(acs_data, 3, 3); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Completion Redirect P2P not supported", 0); + p2p_support_flag++; + } + /* Extract ACS p2p Direct Translated bit */ + data = VAL_EXTRACT_BITS(acs_data, 6, 6); + if (data == 0) { + val_print(AVS_PRINT_DEBUG, "\n Direct Translated P2P not supported", 0); + p2p_support_flag++; + } + if (p2p_support_flag > 0) { + val_print(AVS_PRINT_ERR, "\n P2P not supported for bdf: %d", bdf); + p2p_support_flag = 0; + test_fails++; + } + } + } + + if (test_skip == 1) + val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + else if (test_fails) + val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, test_fails)); + else + val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t +p057_entry(uint32_t num_pe) +{ + + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c004.c b/test_pool/pe/test_c004.c index 4ea91269..1b002f9c 100755 --- a/test_pool/pe/test_c004.c +++ b/test_pool/pe/test_c004.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -19,7 +19,7 @@ #include "val/include/sbsa_avs_pe.h" #define TEST_NUM (AVS_PE_TEST_NUM_BASE + 04) -#define TEST_DESC "Check MMU Granule sizes " +#define TEST_DESC "Check PE Granule Support " static void @@ -30,13 +30,32 @@ payload() data = val_pe_reg_read(ID_AA64MMFR0_EL1); - if ((data & 0xFF000000) == 0) //bits 31:24 must be 000 - val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); - else - val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); - - return; - + /* PEs must support 4k, 64k granule for Stage 1 & Stage 2. + * 1. Implementation before v8.5 + * ID_AA64MMFR0_EL1 [43:36] should be RES0. + * Check For TGran4[31:28] == 0 & TGran64[27:24] == 0. + * 2. Implementation After v8.5 + * ID_AA64MMFR0_EL1 [43:36] should not be 0. + * Check For TGran4[31:28] == 0 & TGran64[27:24] == 0. + * Check For TGran4_2[43:40] == 0x2 & TGran64_2[39:36] == 0x2. + */ + + if (VAL_EXTRACT_BITS(data, 36, 43) == 0) { + /* Implementation before Arm v8.5 */ + if (VAL_EXTRACT_BITS(data, 24, 31) == 0) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + + } else { + /* Implementation after Arm v8.5 */ + if ((VAL_EXTRACT_BITS(data, 24, 31) == 0) && + (VAL_EXTRACT_BITS(data, 36, 43) == 0x22)) + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + + } } uint32_t diff --git a/test_pool/pe/test_c029.c b/test_pool/pe/test_c029.c new file mode 100755 index 00000000..1e3a8062 --- /dev/null +++ b/test_pool/pe/test_c029.c @@ -0,0 +1,63 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 29) +#define TEST_DESC "Check Speculation Restriction " + +static void payload() +{ + uint64_t data_csv2 = 0; + uint64_t data_csv3 = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64PFR0_EL1.CSV2[59:56] = 0b0010 Speculative use of Out of Ctxt Branch Targets */ + /* ID_AA64PFR0_EL1.CSV3[63:60] = 0b0001 Speculative use of Faulting data */ + data_csv2 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 56, 59); + data_csv3 = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 60, 63); + + if (data_csv2 != 2) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else if (data_csv3 != 1) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c029_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c030.c b/test_pool/pe/test_c030.c new file mode 100755 index 00000000..12b7e43e --- /dev/null +++ b/test_pool/pe/test_c030.c @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 30) +#define TEST_DESC "Check Speculative Str Bypass Safe " + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64PFR1_EL1.SSBS[7:4] = 0b0010 */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 4, 7); + + if (data != 2) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c030_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c031.c b/test_pool/pe/test_c031.c new file mode 100755 index 00000000..0af1c921 --- /dev/null +++ b/test_pool/pe/test_c031.c @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 31) +#define TEST_DESC "Check PEs Implement SB Barrier " + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64ISAR1_EL1.SB[39:36] = 0b0001 For SB Speculation Barrier */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 36, 39); + + if (data != 1) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c031_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c032.c b/test_pool/pe/test_c032.c new file mode 100755 index 00000000..b46de5e1 --- /dev/null +++ b/test_pool/pe/test_c032.c @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 32) +#define TEST_DESC "Check PE Impl CFP,DVP,CPP RCTX " + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64ISAR1_EL1.SPECRES[43:40] = 0b0001 For CFP, DVP, CPP RCTX Instructions */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64ISAR1_EL1), 40, 43); + + if (data != 1) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c032_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c033.c b/test_pool/pe/test_c033.c new file mode 100644 index 00000000..58ad0250 --- /dev/null +++ b/test_pool/pe/test_c033.c @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 33) +#define TEST_DESC "Check Branch Target Support " + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64PFR1_EL1.BT[3:0] = 0b0001 For Branch Target Identification Support */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR1_EL1), 0, 3); + + if (data != 1) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c033_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c034.c b/test_pool/pe/test_c034.c new file mode 100644 index 00000000..2f2023be --- /dev/null +++ b/test_pool/pe/test_c034.c @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 34) +#define TEST_DESC "Check Protect Against Timing Fault" + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64MMFR2_EL1.E0PD[63:60] = 0b0001 For Support for Protect Against Timing Fault */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 60, 63); + + if (data != 1) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c034_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c035.c b/test_pool/pe/test_c035.c new file mode 100644 index 00000000..4ca80193 --- /dev/null +++ b/test_pool/pe/test_c035.c @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 35) +#define TEST_DESC "Check Enhanced Virtualization Trap" + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* ID_AA64MMFR2_EL1.EVT[59:56] = 0b0010 - Support for Enhanced Virtualization Trap */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR2_EL1), 56, 59); + + if (data != 2) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c035_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c036.c b/test_pool/pe/test_c036.c new file mode 100644 index 00000000..51847765 --- /dev/null +++ b/test_pool/pe/test_c036.c @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 36) +#define TEST_DESC "Check PMU Version Support " + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64DFR0_EL1.PMUVer[11:8] = 0b0110 For Support for PMU v8.5 Support */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 8, 11); + + if (data != 6) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c036_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c037.c b/test_pool/pe/test_c037.c new file mode 100644 index 00000000..bc36fe82 --- /dev/null +++ b/test_pool/pe/test_c037.c @@ -0,0 +1,68 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 37) +#define TEST_DESC "Check SPE if implemented " + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64PFR0_EL1.SVE[35:32] = 0b0001 for SVE */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64PFR0_EL1), 32, 35); + + if (data == 0) { + /* SVE Not Implemented Skip the test */ + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + /* Read ID_AA64DFR0_EL1.PMSVer[35:32] = 0b0010 for v8.3-SPE */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64DFR0_EL1), 32, 35); + + if (data != 2) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t c037_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/pe/test_c038.c b/test_pool/pe/test_c038.c new file mode 100644 index 00000000..944a399e --- /dev/null +++ b/test_pool/pe/test_c038.c @@ -0,0 +1,58 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/sbsa_avs_pe.h" +#include "val/include/val_interface.h" + +#define TEST_NUM (AVS_PE_TEST_NUM_BASE + 38) +#define TEST_DESC "Check AccessFlag DirtyState Update" + +static void payload() +{ + uint64_t data = 0; + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + + if (g_sbsa_level < 6) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + /* Read ID_AA64MMFR1_EL1.HAFDBS[3:0] = 0b0010 For Hardware update supported */ + data = VAL_EXTRACT_BITS(val_pe_reg_read(ID_AA64MMFR1_EL1), 0, 3); + + if (data != 2) + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + else + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); +} + +uint32_t c038_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; +} diff --git a/test_pool/peripherals/test_m001.c b/test_pool/peripherals/test_m001.c old mode 100644 new mode 100755 index 48584449..a8536ae1 --- a/test_pool/peripherals/test_m001.c +++ b/test_pool/peripherals/test_m001.c @@ -25,6 +25,7 @@ #define TEST_DESC "Memory Access to Un-Populated addr" #define LOOP_VAR 3 /* Number of Addresses to check */ +#define STEP_SIZE 0x1000000 /* Step size to increment address */ static void *branch_to_test; @@ -57,26 +58,18 @@ payload() uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); val_pe_install_esr(EXCEPT_AARCH64_SYNCHRONOUS_EXCEPTIONS, esr); - val_pe_install_esr(EXCEPT_AARCH64_SERROR, esr); - val_pe_install_esr(EXCEPT_AARCH64_IRQ, esr); - val_pe_install_esr(EXCEPT_AARCH64_FIQ, esr); /* If we don't find a single un-populated address, mark this test as skipped */ val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); - while (loop_var) { - /* Get the base address of unpopulated region */ - status = val_memory_get_unpopulated_addr(&addr, instance); - if (status == EFI_NO_MAPPING) { - val_print(AVS_PRINT_INFO, "\n All instances of unpopulated memory were obtained", 0); - return; - } - - if (status) { - val_print(AVS_PRINT_ERR, "\n Error in obtaining unpopulated memory for instance 0x%d", instance); - return; - } + /* Get the base address of unpopulated region */ + status = val_memory_get_unpopulated_addr(&addr, instance); + if (status) { + val_print(AVS_PRINT_ERR, "\n Error in obtaining unpopulated memory for instance 0x%d", instance); + return; + } + while (loop_var > 0) { if (val_memory_get_info(addr, &attr) == MEM_TYPE_NOT_POPULATED) { /* default value of FAIL, Pass is set in the exception handler */ val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); @@ -92,8 +85,8 @@ payload() } } - - instance++; + addr += STEP_SIZE; + loop_var--; } } diff --git a/test_pool/timer_wd/test_w002.c b/test_pool/timer_wd/test_w002.c index f8f9ef0e..238be5e1 100755 --- a/test_pool/timer_wd/test_w002.c +++ b/test_pool/timer_wd/test_w002.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018,2020 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/test_pool/timer_wd/test_w003.c b/test_pool/timer_wd/test_w003.c new file mode 100644 index 00000000..50a760b6 --- /dev/null +++ b/test_pool/timer_wd/test_w003.c @@ -0,0 +1,98 @@ +/** @file + * Copyright (c) 2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "val/include/sbsa_avs_val.h" +#include "val/include/val_interface.h" + +#include "val/include/sbsa_avs_wd.h" + +#define TEST_NUM (AVS_WD_TEST_NUM_BASE + 3) +#define TEST_DESC "Check NS Watchdog Revision " + +static +void +payload() +{ + + uint64_t ctrl_base; + uint64_t wd_num = val_wd_get_info(0, WD_INFO_COUNT); + uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid()); + uint32_t data, ns_wdg = 0; + + if (g_sbsa_level < 5) { + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01)); + return; + } + + val_print(AVS_PRINT_DEBUG, "\n Found %d watchdogs in ACPI table ", wd_num); + + if (wd_num == 0) { + val_print(AVS_PRINT_WARN, "\n No Watchdogs reported %d ", wd_num); + val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01)); + return; + } + + do { + wd_num--; //array index starts from 0, so subtract 1 from count + + if (val_wd_get_info(wd_num, WD_INFO_ISSECURE)) + continue; //Skip Secure watchdog + + ns_wdg++; + ctrl_base = val_wd_get_info(wd_num, WD_INFO_CTRL_BASE); + val_print(AVS_PRINT_INFO, "\n Watchdog CTRL base is %x ", ctrl_base); + + /* W_IIDR.Architecture Revision [19:16] = 0x1 for Watchdog Rev 1 */ + data = VAL_EXTRACT_BITS(val_mmio_read(ctrl_base + WD_IIDR_OFFSET), 16, 19); + + if(data != 1) { + val_print(AVS_PRINT_WARN, "\n Recommended Watchdog Rev 1 Not Found", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02)); + return; + } + + } while(wd_num); + + if(!ns_wdg) { + val_print(AVS_PRINT_WARN, "\n No non-secure Watchdogs reported", 0); + val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 03)); + return; + } + + val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01)); + +} + +uint32_t +w003_entry(uint32_t num_pe) +{ + uint32_t status = AVS_STATUS_FAIL; + + num_pe = 1; //This test is run on single processor + + status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level); + /* This check is when user is forcing us to skip this test */ + if (status != AVS_STATUS_SKIP) + val_run_test_payload(TEST_NUM, num_pe, payload, 0); + + /* get the result from all PE and check for failure */ + status = val_check_for_error(TEST_NUM, num_pe); + val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM)); + + return status; + +} diff --git a/uefi_app/SbsaAvs.h b/uefi_app/SbsaAvs.h index 31fab210..65a940b4 100755 --- a/uefi_app/SbsaAvs.h +++ b/uefi_app/SbsaAvs.h @@ -20,11 +20,11 @@ - #define SBSA_ACS_MAJOR_VER 2 - #define SBSA_ACS_MINOR_VER 5 + #define SBSA_ACS_MAJOR_VER 3 + #define SBSA_ACS_MINOR_VER 0 #define G_SBSA_LEVEL 4 - #define SBSA_MAX_LEVEL_SUPPORTED 5 + #define SBSA_MAX_LEVEL_SUPPORTED 6 #define G_PRINT_LEVEL AVS_PRINT_TEST #define PE_INFO_TBL_SZ 8192 /*Supports maximum 400 PEs*/ diff --git a/uefi_app/SbsaAvs.inf b/uefi_app/SbsaAvs.inf index 2a9d1474..f8b24866 100644 --- a/uefi_app/SbsaAvs.inf +++ b/uefi_app/SbsaAvs.inf @@ -62,6 +62,16 @@ ../test_pool/pe/test_c026.c ../test_pool/pe/test_c027.c ../test_pool/pe/test_c028.c + ../test_pool/pe/test_c029.c + ../test_pool/pe/test_c030.c + ../test_pool/pe/test_c031.c + ../test_pool/pe/test_c032.c + ../test_pool/pe/test_c033.c + ../test_pool/pe/test_c034.c + ../test_pool/pe/test_c035.c + ../test_pool/pe/test_c036.c + ../test_pool/pe/test_c037.c + ../test_pool/pe/test_c038.c ../test_pool/gic/test_g001.c ../test_pool/gic/test_g002.c ../test_pool/gic/test_g003.c @@ -76,8 +86,10 @@ ../test_pool/timer_wd/test_t008.c ../test_pool/timer_wd/test_w001.c ../test_pool/timer_wd/test_w002.c + ../test_pool/timer_wd/test_w003.c ../test_pool/pcie/test_p001.c ../test_pool/pcie/test_p002.c + ../test_pool/pcie/test_p003.c ../test_pool/pcie/test_p020.c ../test_pool/pcie/test_p021.c ../test_pool/pcie/test_p022.c @@ -104,12 +116,34 @@ ../test_pool/pcie/test_p043.c ../test_pool/pcie/test_p044.c ../test_pool/pcie/test_p045.c + ../test_pool/pcie/test_p046.c + ../test_pool/pcie/test_p047.c + ../test_pool/pcie/test_p048.c + ../test_pool/pcie/test_p049.c + ../test_pool/pcie/test_p050.c + ../test_pool/pcie/test_p051.c + ../test_pool/pcie/test_p052.c + ../test_pool/pcie/test_p053.c + ../test_pool/pcie/test_p054.c + ../test_pool/pcie/test_p055.c + ../test_pool/pcie/test_p056.c + ../test_pool/pcie/test_p057.c ../test_pool/io_virt/test_i001.c ../test_pool/io_virt/test_i002.c ../test_pool/io_virt/test_i003.c ../test_pool/io_virt/test_i004.c ../test_pool/io_virt/test_i005.c ../test_pool/io_virt/test_i006.c + ../test_pool/io_virt/test_i007.c + ../test_pool/io_virt/test_i008.c + ../test_pool/io_virt/test_i009.c + ../test_pool/io_virt/test_i010.c + ../test_pool/io_virt/test_i011.c + ../test_pool/io_virt/test_i012.c + ../test_pool/io_virt/test_i013.c + ../test_pool/io_virt/test_i014.c + ../test_pool/io_virt/test_i015.c + ../test_pool/io_virt/test_i016.c ../test_pool/power_wakeup/test_u001.c ../test_pool/power_wakeup/test_u002.c ../test_pool/peripherals/test_d001.c @@ -127,6 +161,11 @@ ../test_pool/exerciser/test_e008.c ../test_pool/exerciser/test_e009.c ../test_pool/exerciser/test_e010.c + ../test_pool/exerciser/test_e011.c + ../test_pool/exerciser/test_e012.c + ../test_pool/exerciser/test_e013.c + ../test_pool/exerciser/test_e014.c + ../test_pool/exerciser/test_e015.c [Packages] StdLib/StdLib.dec diff --git a/uefi_app/SbsaAvsMain.c b/uefi_app/SbsaAvsMain.c index 806da0eb..091b3bff 100644 --- a/uefi_app/SbsaAvsMain.c +++ b/uefi_app/SbsaAvsMain.c @@ -107,6 +107,16 @@ createGicInfoTable ( } +EFI_STATUS +configureGicIts ( +) +{ + EFI_STATUS Status; + + Status = val_gic_its_configure(); + + return Status; +} EFI_STATUS createTimerInfoTable( @@ -245,7 +255,7 @@ HelpMsg ( "-v Verbosity of the Prints\n" " 1 shows all prints, 5 shows Errors\n" "-l Level of compliance to be tested for\n" - " As per SBSA spec, 0 to 3\n" + " As per SBSA spec, 0 to 6\n" "-f Name of the log file to record the test results in\n" "-s Enable the execution of secure tests\n" "-skip Test(s) to be skipped\n" @@ -412,6 +422,16 @@ ShellAppMainsbsa ( if (Status) return Status; + /* + * Configure Gic Redistributor and ITS to support + * Generation of LPIs. + */ + Status = configureGicIts(); + if (Status) { + Print(L" GIC ITS Initialization Failed.\n"); + Print(L" LPI Interrupt related test may not pass.\n"); + } + createTimerInfoTable(); createWatchdogInfoTable(); createPcieVirtInfoTable(); diff --git a/uefi_app/SbsaAvsNist.inf b/uefi_app/SbsaAvsNist.inf index 1cf15b04..c33d5190 100644 --- a/uefi_app/SbsaAvsNist.inf +++ b/uefi_app/SbsaAvsNist.inf @@ -62,6 +62,16 @@ ../test_pool/pe/test_c026.c ../test_pool/pe/test_c027.c ../test_pool/pe/test_c028.c + ../test_pool/pe/test_c029.c + ../test_pool/pe/test_c030.c + ../test_pool/pe/test_c031.c + ../test_pool/pe/test_c032.c + ../test_pool/pe/test_c033.c + ../test_pool/pe/test_c034.c + ../test_pool/pe/test_c035.c + ../test_pool/pe/test_c036.c + ../test_pool/pe/test_c037.c + ../test_pool/pe/test_c038.c ../test_pool/gic/test_g001.c ../test_pool/gic/test_g002.c ../test_pool/gic/test_g003.c @@ -76,8 +86,10 @@ ../test_pool/timer_wd/test_t008.c ../test_pool/timer_wd/test_w001.c ../test_pool/timer_wd/test_w002.c + ../test_pool/timer_wd/test_w003.c ../test_pool/pcie/test_p001.c ../test_pool/pcie/test_p002.c + ../test_pool/pcie/test_p003.c ../test_pool/pcie/test_p020.c ../test_pool/pcie/test_p021.c ../test_pool/pcie/test_p022.c @@ -104,12 +116,34 @@ ../test_pool/pcie/test_p043.c ../test_pool/pcie/test_p044.c ../test_pool/pcie/test_p045.c + ../test_pool/pcie/test_p046.c + ../test_pool/pcie/test_p047.c + ../test_pool/pcie/test_p048.c + ../test_pool/pcie/test_p049.c + ../test_pool/pcie/test_p050.c + ../test_pool/pcie/test_p051.c + ../test_pool/pcie/test_p052.c + ../test_pool/pcie/test_p053.c + ../test_pool/pcie/test_p054.c + ../test_pool/pcie/test_p055.c + ../test_pool/pcie/test_p056.c + ../test_pool/pcie/test_p057.c ../test_pool/io_virt/test_i001.c ../test_pool/io_virt/test_i002.c ../test_pool/io_virt/test_i003.c ../test_pool/io_virt/test_i004.c ../test_pool/io_virt/test_i005.c ../test_pool/io_virt/test_i006.c + ../test_pool/io_virt/test_i007.c + ../test_pool/io_virt/test_i008.c + ../test_pool/io_virt/test_i009.c + ../test_pool/io_virt/test_i010.c + ../test_pool/io_virt/test_i011.c + ../test_pool/io_virt/test_i012.c + ../test_pool/io_virt/test_i013.c + ../test_pool/io_virt/test_i014.c + ../test_pool/io_virt/test_i015.c + ../test_pool/io_virt/test_i016.c ../test_pool/power_wakeup/test_u001.c ../test_pool/power_wakeup/test_u002.c ../test_pool/peripherals/test_d001.c @@ -127,6 +161,11 @@ ../test_pool/exerciser/test_e008.c ../test_pool/exerciser/test_e009.c ../test_pool/exerciser/test_e010.c + ../test_pool/exerciser/test_e011.c + ../test_pool/exerciser/test_e012.c + ../test_pool/exerciser/test_e013.c + ../test_pool/exerciser/test_e014.c + ../test_pool/exerciser/test_e015.c ../test_pool/nist_sts/test_n001.c [Packages] diff --git a/val/Makefile b/val/Makefile index 17b77fe4..2b456723 100644 --- a/val/Makefile +++ b/val/Makefile @@ -1,5 +1,5 @@ ## @file - # Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + # Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -27,7 +27,8 @@ obj-m += sbsa_acs_val.o sbsa_acs_val-objs += $(VAL_SRC)/avs_status.o $(VAL_SRC)/avs_memory.o \ $(VAL_SRC)/avs_peripherals.o $(VAL_SRC)/avs_dma.o $(VAL_SRC)/avs_smmu.o \ $(VAL_SRC)/avs_test_infra.o $(VAL_SRC)/avs_pcie.o $(VAL_SRC)/avs_pe_infra.o \ - $(VAL_SRC)/avs_iovirt.o $(VAL_SRC)/avs_gic_support.o $(VAL_SRC)/avs_exerciser.o + $(VAL_SRC)/avs_iovirt.o $(VAL_SRC)/avs_gic_support.o \ + $(ACS_DIR)/sys_arch_src/smmu_v3/smmu_v3.o ccflags-y=-I$(PWD)/$(ACS_DIR)/include -I$(PWD)/$(ACS_DIR)/ -DTARGET_LINUX -Wall -Werror diff --git a/val/SbsaValLib.inf b/val/SbsaValLib.inf index 956a9a5d..33752df4 100644 --- a/val/SbsaValLib.inf +++ b/val/SbsaValLib.inf @@ -45,6 +45,8 @@ src/avs_secure.c src/avs_memory.c src/avs_exerciser.c + src/avs_pgt.c + sys_arch_src/smmu_v3/smmu_v3.c [Packages] MdePkg/MdePkg.dec diff --git a/val/SbsaValNistLib.inf b/val/SbsaValNistLib.inf index 2fc26eb6..78fd806e 100644 --- a/val/SbsaValNistLib.inf +++ b/val/SbsaValNistLib.inf @@ -46,6 +46,8 @@ src/avs_memory.c src/avs_exerciser.c src/avs_nist.c + src/avs_pgt.c + sys_arch_src/smmu_v3/smmu_v3.c [Packages] StdLib/StdLib.dec diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index b963549a..e2183ba1 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -73,6 +73,17 @@ typedef struct { PE_INFO_ENTRY pe_info[]; }PE_INFO_TABLE; +typedef struct { + uint32_t ps:3; + uint32_t tg:2; + uint32_t sh:2; + uint32_t orgn:2; + uint32_t irgn:2; + uint32_t tsz:6; + uint32_t sl:2; + uint32_t tg_size_log2:5; +}PE_TCR_BF; + void pal_pe_create_info_table(PE_INFO_TABLE *pe_info_table); /** @@ -129,6 +140,7 @@ typedef enum { typedef struct { uint32_t type; uint64_t base; + uint32_t its_id; /* This its_id is only used in case of ITS Type entry */ }GIC_INFO_ENTRY; /** @@ -145,8 +157,10 @@ void pal_gic_end_of_interrupt(uint32_t int_id); uint32_t pal_gic_request_irq(unsigned int irq_num, unsigned int mapped_irq_num, void *isr); void pal_gic_free_irq(unsigned int irq_num, unsigned int mapped_irq_num); uint32_t pal_gic_set_intr_trigger(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e trigger_type); -uint32_t pal_gic_request_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index); -void pal_gic_free_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index); +uint32_t pal_gic_its_configure(void); +uint32_t pal_gic_request_msi(uint32_t its_id, uint32_t DevID, uint32_t IntID, uint32_t msi_index, uint32_t *msi_addr, uint32_t *msi_data); +void pal_gic_free_msi(uint32_t its_id, uint32_t DevID, uint32_t IntID, uint32_t msi_index); +uint32_t pal_gic_get_max_lpi_id(void); /** Timer tests related definitions **/ @@ -249,7 +263,7 @@ uint32_t pal_pci_cfg_read(uint32_t bus, uint32_t dev, uint32_t func, int offset, uint64_t pal_pcie_get_mcfg_ecam(void); void pal_pcie_create_info_table(PCIE_INFO_TABLE *PcieTable); -uint32_t pal_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data); +uint32_t pal_pcie_io_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data); uint32_t pal_pcie_get_bdf_wrapper(uint32_t class_code, uint32_t start_bdf); void *pal_pci_bdf_to_dev(uint32_t bdf); void pal_pci_read_config_byte(uint32_t bdf, uint8_t offset, uint8_t *val); @@ -257,9 +271,12 @@ void pal_pci_write_config_byte(uint32_t bdf, uint8_t offset, uint8_t val); void pal_pcie_read_ext_cap_word(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn, uint32_t ext_cap_id, uint8_t offset, uint16_t *val); uint32_t pal_pcie_get_pcie_type(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn); -uint32_t pal_pcie_p2p_support(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn); +uint32_t pal_pcie_p2p_support(void); +uint32_t pal_pcie_dev_p2p_support(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn); uint32_t pal_pcie_multifunction_support(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn); +uint32_t pal_pcie_is_cache_present(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn); +void pal_pcie_io_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data); /** @brief Instance of SMMU INFO block **/ @@ -352,6 +369,30 @@ typedef struct { SMMU_INFO_BLOCK smmu_block[]; ///< Array of Information blocks - instantiated for each SMMU Controller }SMMU_INFO_TABLE; +typedef struct { + uint32_t smmu_index; + uint32_t streamid; + uint32_t substreamid; + uint32_t ssid_bits; + uint32_t stage2; +} smmu_master_attributes_t; + +typedef struct { + uint64_t pgt_base; + uint32_t ias; + uint32_t oas; + uint64_t mair; + uint32_t stage; + PE_TCR_BF tcr; +} pgt_descriptor_t; + +typedef struct { + uint64_t physical_address; + uint64_t virtual_address; + uint64_t length; + uint64_t attributes; +} memory_region_descriptor_t; + void pal_smmu_create_info_table(SMMU_INFO_TABLE *smmu_info_table); uint32_t pal_smmu_check_device_iova(void *port, uint64_t dma_addr); void pal_smmu_device_start_monitor_iova(void *port); @@ -526,20 +567,32 @@ void pal_print_raw(uint64_t addr, char8_t *string, uint64_t data); uint32_t pal_strncmp(char8_t *str1, char8_t *str2, uint32_t len); void *pal_memcpy(void *dest_buffer, void *src_buffer, uint32_t len); void *pal_mem_alloc(uint32_t size); -void *pal_mem_alloc_coherent(uint32_t bdf, uint32_t size, void *pa); +void *pal_mem_alloc_cacheable(uint32_t bdf, uint32_t size, void **pa); void pal_mem_free(void *buffer); int pal_mem_compare(void *src, void *dest, uint32_t len); void pal_mem_set(void *buf, uint32_t size, uint8_t value); -void pal_mem_free_coherent(uint32_t bdf, unsigned int size, void *va, void *pa); +void pal_mem_free_cacheable(uint32_t bdf, unsigned int size, void *va, void *pa); void *pal_mem_virt_to_phys(void *va); +void *pal_mem_phys_to_virt(uint64_t pa); uint64_t pal_time_delay_ms(uint64_t time_ms); void pal_mem_allocate_shared(uint32_t num_pe, uint32_t sizeofentry); void pal_mem_free_shared(void); uint64_t pal_mem_get_shared_addr(void); +uint8_t pal_mmio_read8(uint64_t addr); +uint16_t pal_mmio_read16(uint64_t addr); + +uint32_t pal_mem_page_size(void); +void *pal_mem_alloc_pages(uint32_t num_pages); +void pal_mem_free_pages(void *page_base, uint32_t num_pages); + uint32_t pal_mmio_read(uint64_t addr); +uint64_t pal_mmio_read64(uint64_t addr); +void pal_mmio_write8(uint64_t addr, uint8_t data); +void pal_mmio_write16(uint64_t addr, uint16_t data); void pal_mmio_write(uint64_t addr, uint32_t data); +void pal_mmio_write64(uint64_t addr, uint64_t data); void pal_pe_update_elr(void *context, uint64_t offset); uint64_t pal_pe_get_esr(void *context); @@ -582,9 +635,24 @@ typedef enum { DMA_ATTRIBUTES = 0x4, P2P_ATTRIBUTES = 0x5, PASID_ATTRIBUTES = 0x6, - CFG_TXN_ATTRIBUTES = 0x7 + CFG_TXN_ATTRIBUTES = 0x7, + ATS_RES_ATTRIBUTES = 0x8, + TRANSACTION_TYPE = 0x9, + NUM_TRANSACTIONS = 0xA } EXERCISER_PARAM_TYPE; +typedef enum { + TXN_REQ_ID = 0x0, + TXN_ADDR_TYPE = 0x1, +} EXERCISER_TXN_ATTR; + +typedef enum { + AT_UNTRANSLATED = 0x0, + AT_TRANS_REQ = 0x1, + AT_TRANSLATED = 0x2, + AT_RESERVED = 0x3 +} EXERCISER_TXN_ADDR_TYPE; + typedef enum { EXERCISER_RESET = 0x1, EXERCISER_ON = 0x2, @@ -601,10 +669,11 @@ typedef enum { CLEAR_INTR = 0x6, PASID_TLP_START = 0x7, PASID_TLP_STOP = 0x8, - NO_SNOOP_CLEAR_TLP_START = 0x9, - NO_SNOOP_CLEAR_TLP_STOP = 0xa, - START_TXN_MONITOR = 0xb, - STOP_TXN_MONITOR = 0xc + TXN_NO_SNOOP_ENABLE = 0x9, + TXN_NO_SNOOP_DISABLE = 0xa, + START_TXN_MONITOR = 0xb, + STOP_TXN_MONITOR = 0xc, + ATS_TXN_REQ = 0xd } EXERCISER_OPS; typedef enum { diff --git a/val/include/sbsa_avs_common.h b/val/include/sbsa_avs_common.h index 5be65600..74a54c1b 100644 --- a/val/include/sbsa_avs_common.h +++ b/val/include/sbsa_avs_common.h @@ -87,12 +87,30 @@ #define IS_TEST_SKIP(value) (((value >> STATE_BIT) & (STATE_MASK)) == TEST_SKIP_VAL) #define IS_TEST_FAIL_SKIP(value) ((IS_TEST_FAIL(value)) || (IS_TEST_SKIP(value))) +uint8_t +val_mmio_read8(addr_t addr); + +uint16_t +val_mmio_read16(addr_t addr); + uint32_t val_mmio_read(addr_t addr); +uint64_t +val_mmio_read64(addr_t addr); + +void +val_mmio_write8(addr_t addr, uint8_t data); + +void +val_mmio_write16(addr_t addr, uint16_t data); + void val_mmio_write(addr_t addr, uint32_t data); +void +val_mmio_write64(addr_t addr, uint64_t data); + uint32_t val_initialize_test(uint32_t test_num, char8_t * desc, uint32_t num_pe, uint32_t level); diff --git a/val/include/sbsa_avs_exerciser.h b/val/include/sbsa_avs_exerciser.h index ca899438..0bbab143 100644 --- a/val/include/sbsa_avs_exerciser.h +++ b/val/include/sbsa_avs_exerciser.h @@ -62,5 +62,10 @@ uint32_t e007_entry(void); uint32_t e008_entry(void); uint32_t e009_entry(void); uint32_t e010_entry(void); +uint32_t e011_entry(void); +uint32_t e012_entry(void); +uint32_t e013_entry(void); +uint32_t e014_entry(void); +uint32_t e015_entry(void); #endif diff --git a/val/include/sbsa_avs_gic.h b/val/include/sbsa_avs_gic.h index ce12cd15..d168a8f6 100644 --- a/val/include/sbsa_avs_gic.h +++ b/val/include/sbsa_avs_gic.h @@ -38,8 +38,12 @@ #define GICD_ISACTIVER0 0x300 #define GICD_ICPENDR0 0x280 #define GICD_ICACTIVER0 0x380 +#define GICD_ICFGR 0xC00 #define GICD_IROUTER 0x6000 +#define GICD_ICFGR_INTR_STRIDE 16 /* (32/2) Interrupt per Register */ +#define GICD_ICFGR_INTR_CONFIG1(intid) ((1+int_id*2) % 32) /* Bit Config[2x+1] for config type level/edge */ + uint32_t g001_entry(uint32_t num_pe); uint32_t diff --git a/val/include/sbsa_avs_gic_support.h b/val/include/sbsa_avs_gic_support.h index 5493d389..43a97bdf 100644 --- a/val/include/sbsa_avs_gic_support.h +++ b/val/include/sbsa_avs_gic_support.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,6 +18,8 @@ #ifndef __GIC_SYS_REGS_H__ #define __GIC_SYS_REGS_H__ +#define LPI_MIN_ID 8192 + typedef enum { ICH_HCR_EL2 = 0, ICH_MISR_EL2, diff --git a/val/include/sbsa_avs_iovirt.h b/val/include/sbsa_avs_iovirt.h index 8b1c4e80..75384673 100644 --- a/val/include/sbsa_avs_iovirt.h +++ b/val/include/sbsa_avs_iovirt.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,7 +21,7 @@ uint64_t val_iovirt_get_smmu_info(SMMU_INFO_e type, uint32_t index); uint32_t val_iovirt_check_unique_ctx_intid(uint32_t smmu_index); uint32_t val_iovirt_unique_rid_strid_map(uint32_t rc_index); -int val_iovirt_get_device_id(uint32_t rid, uint32_t segment, uint32_t *device_id, uint32_t *stream_id); +int val_iovirt_get_device_info(uint32_t rid, uint32_t segment, uint32_t *device_id, uint32_t *stream_id, uint32_t *its_id); uint64_t val_iovirt_get_pcie_rc_info(PCIE_RC_INFO_e type, uint32_t index); #endif diff --git a/val/include/sbsa_avs_memory.h b/val/include/sbsa_avs_memory.h index f8ad3761..4f4e2b6b 100644 --- a/val/include/sbsa_avs_memory.h +++ b/val/include/sbsa_avs_memory.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -22,11 +22,15 @@ addr_t val_memory_ioremap(void *addr, uint32_t size, uint64_t attr); void val_memory_unmap(void *ptr); void *val_memory_alloc(uint32_t size); -void *val_memory_alloc_coherent(uint32_t bdf, uint32_t size, void *pa); +void *val_memory_alloc_cacheable(uint32_t bdf, uint32_t size, void **pa); void val_memory_free(void *addr); int val_memory_compare(void *src, void *dest, uint32_t len); void val_memory_set(void *buf, uint32_t size, uint8_t value); -void val_memory_free_coherent(uint32_t bdf, uint32_t size, void *va, void *pa); +void val_memory_free_cacheable(uint32_t bdf, uint32_t size, void *va, void *pa); void *val_memory_virt_to_phys(void *va); +void *val_memory_phys_to_virt(uint64_t pa); +uint32_t val_memory_page_size(void); +void *val_memory_alloc_pages(uint32_t num_pages); +void val_memory_free_pages(void *page_base, uint32_t num_pages); #endif // __SBSA_AVS_PERIPHERAL_H__ diff --git a/val/include/sbsa_avs_pcie.h b/val/include/sbsa_avs_pcie.h index 18d033f1..31ea0e1d 100644 --- a/val/include/sbsa_avs_pcie.h +++ b/val/include/sbsa_avs_pcie.h @@ -25,8 +25,14 @@ #define PCIE_EXTRACT_BDF_DEV(bdf) ((bdf >> 8) & 0xFF) #define PCIE_EXTRACT_BDF_FUNC(bdf) (bdf & 0xFF) +#define PCIE_CREATE_BDF_PACKED(bdf) PCIE_EXTRACT_BDF_FUNC(bdf) | \ + (PCIE_EXTRACT_BDF_DEV(bdf) << 3) | \ + (PCIE_EXTRACT_BDF_BUS(bdf) << 8) + #define PCIE_CREATE_BDF(seg, bus, dev, func) ((seg << 24) | ((bus & 0xFF) << 16) | ((dev & 0xFF) << 8) | func) +#define GET_DEVICE_ID(bus, dev, func) ((bus << 8) | (dev << 3) | func) + #define PCIE_MAX_BUS 256 #define PCIE_MAX_DEV 32 #define PCIE_MAX_FUNC 8 @@ -55,6 +61,8 @@ #define MAX_BITFIELD_ENTRIES 100 #define ERR_STRING_SIZE 64 +#define MEM_OFFSET_10 0x10 + /* Allows storage of 2048 valid BDFs */ #define PCIE_DEVICE_BDF_TABLE_SZ 8192 @@ -136,6 +144,7 @@ typedef struct { } pcie_device_bdf_table; void val_pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data); +void val_pcie_io_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data); uint32_t val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data); uint32_t val_get_msi_vectors (uint32_t bdf, PERIPHERAL_VECTOR_LIST **mvector); uint64_t val_pcie_get_bdf_config_addr(uint32_t bdf); @@ -183,6 +192,9 @@ val_pcie_get_rp_transaction_frwd_support(uint32_t bdf); uint32_t val_pcie_get_atomicop_requester_capable(uint32_t bdf); +uint32_t +val_pcie_is_cache_present(uint32_t bdf); + uint32_t p001_entry(uint32_t num_pe); @@ -317,4 +329,41 @@ p044_entry(uint32_t num_pe); uint32_t p045_entry(uint32_t num_pe); + +uint32_t +p046_entry(uint32_t num_pe); + +uint32_t +p047_entry(uint32_t num_pe); + +uint32_t +p048_entry(uint32_t num_pe); + +uint32_t +p049_entry(uint32_t num_pe); + +uint32_t +p050_entry(uint32_t num_pe); + +uint32_t +p051_entry(uint32_t num_pe); + +uint32_t +p052_entry(uint32_t num_pe); + +uint32_t +p053_entry(uint32_t num_pe); + +uint32_t +p054_entry(uint32_t num_pe); + +uint32_t +p055_entry(uint32_t num_pe); + +uint32_t +p056_entry(uint32_t num_pe); + +uint32_t +p057_entry(uint32_t num_pe); + #endif diff --git a/val/include/sbsa_avs_pcie_spec.h b/val/include/sbsa_avs_pcie_spec.h index bd29e00c..61a2f64f 100644 --- a/val/include/sbsa_avs_pcie_spec.h +++ b/val/include/sbsa_avs_pcie_spec.h @@ -38,6 +38,10 @@ #define TYPE01_CPR_MASK 0xff #define TYPE01_HTR_SHIFT 16 #define TYPE01_HTR_MASK 0xff +#define TYPE01_IPR_SHIFT 8 +#define TYPE01_IPR_MASK 0xFF +#define TYPE01_ILR_SHIFT 0 +#define TYPE01_ILR_MASK 0xFF #define TYPE0_HEADER 0 #define TYPE1_HEADER 1 @@ -64,6 +68,14 @@ #define CR_FBTE_MASK 0x1 #define CR_ID_MASK 0x1 +/* Status Register */ +#define SR_STA_SHIFT 27 +#define SR_STA_MASK 0x1 + +/* Secondary Status Register */ +#define SSR_STA_SHIFT 27 +#define SSR_STA_MASK 0x1 + /* Class Code Masks */ #define CC_SUB_MASK 0xFF /* Sub Class */ #define CC_BASE_MASK 0xFF /* Base Class */ @@ -85,6 +97,8 @@ /* Header type reg shifts and masks */ #define HTR_HL_SHIFT 0x0 #define HTR_HL_MASK 0x3f +#define HTR_MFD_SHIFT 7 +#define HTR_MFD_MASK 0x1 /* BAR register shifts */ #define BAR_MIT_SHIFT 0 @@ -102,7 +116,25 @@ #define TYPE1_MAX_BARS 2 /* Type 1 Cfg reg offsets */ -#define TYPE1_PBN 0x18 +#define TYPE1_PBN 0x18 +#define TYPE1_SEC_STA 0x1C +#define TYPE1_NP_MEM 0x20 +#define TYPE1_P_MEM 0x24 +#define TYPE1_P_MEM_BU 0x28 /* Prefetchable Base Upper Offset */ +#define TYPE1_P_MEM_LU 0x2C /* Prefetchable Limit Upper Offset */ + +/* Type 1 Bridge Control Register */ +#define BRIDGE_CTRL_SBR_SET 0x400000 + +/* Memory Base Reg Shifts */ +#define MEM_BA_SHIFT 16 +#define MEM_BA_MASK 0xFFF0 +#define MEM_LIM_LOWER_BITS ((1 << 20) - 1) +#define MEM_LIM_MASK 0xFFF00000 + +#define P_MEM_PAC_MASK 0xF +#define P_MEM_BU_SHIFT 32 /* Base Upper Shift */ +#define P_MEM_LU_SHIFT 32 /* Limit Upper Shift */ /* Bus Number reg shifts */ #define SECBN_SHIFT 8 @@ -127,12 +159,15 @@ #define PCIE_CAP_START 0x40 #define PCIE_CAP_END 0xFC #define PCIE_ECAP_START 0x100 +#define PCIE_ECAP_END 0xFFC /* Capability Structure IDs */ #define CID_PCIECS 0x10 #define CID_MSI 0x05 #define CID_MSIX 0x11 #define CID_PMC 0x01 +#define ECID_AER 0x0001 +#define ECID_ACS 0x000D #define ECID_ARICS 0x000E #define ECID_ATS 0x000F #define ECID_PRI 0x0013 @@ -141,10 +176,17 @@ #define CIDR_OFFSET 0 #define PCIECR_OFFSET 2 #define DCAPR_OFFSET 4 +#define ACSCR_OFFSET 4 #define DCTLR_OFFSET 8 #define DCAP2R_OFFSET 24 #define DCTL2R_OFFSET 28 +/* ACS Capability Register */ +#define ACS_CTRL_SVE_SHIFT 16 +#define ACS_CTRL_TBE_SHIFT 17 +#define ACS_CTRL_RRE_SHIFT 18 +#define ACS_CTRL_UFE_SHIFT 20 + /* PCIe capabilities reg shifts and masks */ #define PCIECR_DPT_SHIFT 4 #define PCIECR_DPT_MASK 0xf @@ -233,4 +275,16 @@ #define iEP_RP (1 << 0b1011) #define PCIe_ALL (iEP_RP | iEP_EP | RP | EP | RCEC | RCiEP) +/* MSI-X Capabilities */ +#define MSI_X_ENABLE_SHIFT 31 + +#define MSI_X_TOR_OFFSET 0x4 + +#define MSI_X_MSG_TBL_ADDR_OFFSET 0x0 +#define MSI_X_MSG_TBL_DATA_OFFSET 0x8 +#define MSI_X_MSG_TBL_MVC_OFFSET 0xC + +#define MSI_X_TABLE_BIR_MASK 0x7 +#define MSI_X_ENTRY_SIZE 16 /* Size of Single MSI Entry in MSI Table */ + #endif diff --git a/val/include/sbsa_avs_pe.h b/val/include/sbsa_avs_pe.h index e2c285a9..c53203be 100644 --- a/val/include/sbsa_avs_pe.h +++ b/val/include/sbsa_avs_pe.h @@ -34,6 +34,38 @@ // AArch64 Exception Level #define AARCH64_EL2 0x8 #define AARCH64_EL1 0x4 +#define AARCH64_EL_MASK (0x3ull << 2) + +#define AARCH64_HCR_E2H_MASK (0x1ull << 34) +#define AARCH64_TTBR_ADDR_MASK (((0x1ull << 47) - 1) << 1) +#define SBSA_TCR_TG1_SHIFT 30 +#define SBSA_TCR_SH1_SHIFT 28 +#define SBSA_TCR_ORGN1_SHIFT 26 +#define SBSA_TCR_IRGN1_SHIFT 24 +#define SBSA_TCR_T1SZ_SHIFT 16 + +#define SBSA_TCR_TG1_MASK (0x3ull << SBSA_TCR_TG1_SHIFT) +#define SBSA_TCR_SH1_MASK (0x3ull << SBSA_TCR_SH1_SHIFT) +#define SBSA_TCR_ORGN1_MASK (0x3ull << SBSA_TCR_ORGN1_SHIFT) +#define SBSA_TCR_IRGN1_MASK (0x3ull << SBSA_TCR_IRGN1_SHIFT) +#define SBSA_TCR_T1SZ_MASK (0x3full << SBSA_TCR_T1SZ_SHIFT) + +#define SBSA_TCR_TG0_SHIFT 14 +#define SBSA_TCR_SH0_SHIFT 12 +#define SBSA_TCR_ORGN0_SHIFT 10 +#define SBSA_TCR_IRGN0_SHIFT 8 +#define SBSA_TCR_T0SZ_SHIFT 0 + +#define SBSA_TCR_TG0_MASK (0x3ull << SBSA_TCR_TG0_SHIFT) +#define SBSA_TCR_SH0_MASK (0x3ull << SBSA_TCR_SH0_SHIFT) +#define SBSA_TCR_ORGN0_MASK (0x3ull << SBSA_TCR_ORGN0_SHIFT) +#define SBSA_TCR_IRGN0_MASK (0x3ull << SBSA_TCR_IRGN0_SHIFT) +#define SBSA_TCR_T0SZ_MASK (0x3full << SBSA_TCR_T0SZ_SHIFT) + +#define SBSA_TCR_IPS_SHIFT 32 +#define SBSA_TCR_IPS_MASK (0x7ull << SBSA_TCR_IPS_SHIFT) +#define SBSA_TCR_PS_SHIFT 16 +#define SBSA_TCR_PS_MASK (0x7ull << SBSA_TCR_PS_SHIFT) typedef enum { MPIDR_EL1 = 1, @@ -98,16 +130,20 @@ typedef enum { PMBLIMITR_EL1, ESR_EL2, FAR_EL2, - RDVL + RDVL, + MAIR_ELx, + TCR_ELx, + TTBR_ELx }SBSA_AVS_PE_REGS; - uint64_t ArmReadMpidr(void); uint64_t ArmReadIdPfr0(void); uint64_t ArmReadIdPfr1(void); +uint64_t ArmReadHcr(void); + uint64_t AA64ReadMmfr0(void); uint64_t AA64ReadMmfr1(void); @@ -220,6 +256,22 @@ uint64_t AA64ReadErr2fr(void); uint64_t AA64ReadErr3fr(void); +uint64_t AA64ReadMair1(void); + +uint64_t AA64ReadMair2(void); + +uint64_t AA64ReadTcr1(void); + +uint64_t AA64ReadTcr2(void); + +uint64_t AA64ReadTtbr0El1(void); + +uint64_t AA64ReadTtbr0El2(void); + +uint64_t AA64ReadTtbr1El1(void); + +uint64_t AA64ReadTtbr1El2(void); + void AA64WritePmsirr(uint64_t write_data); void AA64WritePmscr2(uint64_t write_data); @@ -290,6 +342,16 @@ uint32_t c025_entry(uint32_t num_pe); uint32_t c026_entry(uint32_t num_pe); uint32_t c027_entry(uint32_t num_pe); uint32_t c028_entry(uint32_t num_pe); +uint32_t c029_entry(uint32_t num_pe); +uint32_t c030_entry(uint32_t num_pe); +uint32_t c031_entry(uint32_t num_pe); +uint32_t c032_entry(uint32_t num_pe); +uint32_t c033_entry(uint32_t num_pe); +uint32_t c034_entry(uint32_t num_pe); +uint32_t c035_entry(uint32_t num_pe); +uint32_t c036_entry(uint32_t num_pe); +uint32_t c037_entry(uint32_t num_pe); +uint32_t c038_entry(uint32_t num_pe); #endif diff --git a/val/include/sbsa_avs_pgt.h b/val/include/sbsa_avs_pgt.h new file mode 100644 index 00000000..a5b3975c --- /dev/null +++ b/val/include/sbsa_avs_pgt.h @@ -0,0 +1,47 @@ +/** @file + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#ifndef __SBSA_AVS_PGT_H__ +#define __SBSA_AVS_PGT_H__ + +#define PGT_STAGE1 1 +#define PGT_STAGE2 2 + +#define PGT_ENTRY_TABLE_MASK (0x1 << 1) +#define PGT_ENTRY_VALID_MASK 0x1 +#define PGT_ENTRY_PAGE_MASK (0x1 << 1) +#define PGT_ENTRY_BLOCK_MASK (0x0 << 1) + +#define IS_PGT_ENTRY_PAGE(val) (val & 0x2) +#define IS_PGT_ENTRY_BLOCK(val) !(val & 0x2) + +#define PGT_DESC_SIZE 8 +#define PGT_DESC_ATTR_UPPER_MASK ((0x1ull << 12) - 1) << 52 +#define PGT_DESC_ATTR_LOWER_MASK ((0x1ull << 10) - 1) << 2 +#define PGT_DESC_ATTRIBUTES_MASK (PGT_DESC_ATTR_UPPER_MASK | PGT_DESC_ATTR_LOWER_MASK) +#define PGT_DESC_ATTRIBUTES(val) (val & PGT_DESC_ATTRIBUTES_MASK) + +#define PGT_STAGE1_AP_RO (0x3ull << 6) +#define PGT_STAGE1_AP_RW (0x1ull << 6) +#define PGT_STAGE2_AP_RO (0x1ull << 6) +#define PGT_STAGE2_AP_RW (0x3ull << 6) + +uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t *pgt_desc); +void val_pgt_destroy(pgt_descriptor_t pgt_desc); +uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_address, uint64_t *attributes); + +#endif diff --git a/val/include/sbsa_avs_smmu.h b/val/include/sbsa_avs_smmu.h index c9766c6d..3e9bda8e 100644 --- a/val/include/sbsa_avs_smmu.h +++ b/val/include/sbsa_avs_smmu.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -26,10 +26,15 @@ #define SMMUv3_IDR0 0x00 #define SMMUv3_IDR1 0x04 +#define SMMUv3_IDR2 0x08 +#define SMMUv3_IDR3 0x0C #define SMMUv3_IDR5 0x14 #define SMMUv3_IIDR 0x18 #define SMMUv3_AIDR 0x1C +uint64_t +val_smmu_ssid_bits(uint32_t smmu_index); + uint32_t val_smmu_read_cfg(uint32_t offset, uint32_t index); @@ -42,12 +47,28 @@ val_smmu_max_pasids(uint32_t smmu_index); uint32_t val_smmu_create_pasid_entry(uint32_t smmu_index, uint32_t pasid); +uint32_t +val_smmu_enable(uint32_t smmu_index); + uint32_t val_smmu_disable(uint32_t smmu_index); uint64_t val_smmu_pa2iova(uint32_t smmu_index, uint64_t pa); +uint32_t +val_smmu_init(void); + +void +val_smmu_stop(void); + +uint64_t +val_smmu_map(smmu_master_attributes_t master, + pgt_descriptor_t pgt_desc + ); + +void +val_smmu_unmap(smmu_master_attributes_t master); uint32_t i001_entry(uint32_t num_pe); @@ -61,5 +82,25 @@ uint32_t i005_entry(uint32_t num_pe); uint32_t i006_entry(uint32_t num_pe); +uint32_t +i007_entry(uint32_t num_pe); +uint32_t +i008_entry(uint32_t num_pe); +uint32_t +i009_entry(uint32_t num_pe); +uint32_t +i010_entry(uint32_t num_pe); +uint32_t +i011_entry(uint32_t num_pe); +uint32_t +i012_entry(uint32_t num_pe); +uint32_t +i013_entry(uint32_t num_pe); +uint32_t +i014_entry(uint32_t num_pe); +uint32_t +i015_entry(uint32_t num_pe); +uint32_t +i016_entry(uint32_t num_pe); #endif diff --git a/val/include/sbsa_avs_val.h b/val/include/sbsa_avs_val.h index 053d6270..3bf0891f 100755 --- a/val/include/sbsa_avs_val.h +++ b/val/include/sbsa_avs_val.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,6 +36,12 @@ val_pe_reg_read(uint32_t reg_id); void val_pe_reg_write(uint32_t reg_id, uint64_t write_data); +uint32_t +val_pe_reg_read_tcr(uint32_t ttbr1, PE_TCR_BF *tcr); + +uint32_t +val_pe_reg_read_ttbr(uint32_t ttbr1, uint64_t *ttbr_ptr); + uint8_t val_is_el3_enabled(void); diff --git a/val/include/sbsa_avs_wd.h b/val/include/sbsa_avs_wd.h index ddaff27f..05ca727c 100644 --- a/val/include/sbsa_avs_wd.h +++ b/val/include/sbsa_avs_wd.h @@ -1,7 +1,7 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - + * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at @@ -15,8 +15,10 @@ * limitations under the License. **/ -#ifndef __SBSA_AVS_WD_H__ -#define __SBSA_AVS_WD_H__ +#ifndef __SBSA_AVS_WD_H +#define __SBSA_AVS_WD_H + +#define WD_IIDR_OFFSET 0xFCC uint32_t w001_entry(uint32_t num_pe); @@ -24,4 +26,7 @@ w001_entry(uint32_t num_pe); uint32_t w002_entry(uint32_t num_pe); -#endif // __SBSA_AVS_WD_H__ +uint32_t +w003_entry(uint32_t num_pe); + +#endif // __SBSA_AVS_WD_H diff --git a/val/include/val_interface.h b/val/include/val_interface.h index ff9724fa..476fbe16 100644 --- a/val/include/val_interface.h +++ b/val/include/val_interface.h @@ -90,6 +90,8 @@ void val_gic_cpuif_init(void); uint32_t val_gic_request_irq(uint32_t irq_num, uint32_t mapped_irq_num, void *isr); void val_gic_free_irq(uint32_t irq_num, uint32_t mapped_irq_num); void val_gic_set_intr_trigger(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e trigger_type); +uint32_t val_gic_get_intr_trigger_type(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e *trigger_type); +uint32_t val_gic_its_configure(void); uint32_t val_gic_request_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index); void val_gic_free_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index); @@ -157,7 +159,8 @@ uint32_t val_pcie_is_devicedma_64bit(uint32_t bdf); uint32_t val_pcie_scan_bridge_devices_and_check_memtype(uint32_t bdf); void val_pcie_read_ext_cap_word(uint32_t bdf, uint32_t ext_cap_id, uint8_t offset, uint16_t *val); uint32_t val_pcie_get_pcie_type(uint32_t bdf); -uint32_t val_pcie_p2p_support(uint32_t bdf); +uint32_t val_pcie_p2p_support(void); +uint32_t val_pcie_dev_p2p_support(uint32_t bdf); uint32_t val_pcie_multifunction_support(uint32_t bdf); uint32_t val_pcie_is_onchip_peripheral(uint32_t bdf); uint32_t val_pcie_device_port_type(uint32_t bdf); @@ -178,13 +181,19 @@ uint32_t val_pcie_get_downstream_function(uint32_t bdf, uint32_t *dsf_bdf); uint32_t val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf); uint8_t val_pcie_parent_is_rootport(uint32_t dsf_bdf, uint32_t *rp_bdf); uint8_t val_pcie_is_host_bridge(uint32_t bdf); +void val_pcie_clear_device_status_error(uint32_t bdf); +uint32_t val_pcie_is_device_status_error(uint32_t bdf); +uint32_t val_pcie_is_sig_target_abort(uint32_t bdf); /* IO-VIRT APIs */ typedef enum { SMMU_NUM_CTRL = 1, SMMU_CTRL_BASE, SMMU_CTRL_ARCH_MAJOR_REV, - SMMU_IOVIRT_BLOCK + SMMU_IOVIRT_BLOCK, + SMMU_SSID_BITS, + SMMU_IN_ADDR_SIZE, + SMMU_OUT_ADDR_SIZE }SMMU_INFO_e; typedef enum { diff --git a/val/src/AArch64/PeRegSysSupport.S b/val/src/AArch64/PeRegSysSupport.S index 09b445e8..22dea3bf 100644 --- a/val/src/AArch64/PeRegSysSupport.S +++ b/val/src/AArch64/PeRegSysSupport.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -110,6 +110,14 @@ GCC_ASM_EXPORT (AA64ReadSp) GCC_ASM_EXPORT (AA64WriteSp) GCC_ASM_EXPORT (AA64ReadFar2) GCC_ASM_EXPORT (ArmRdvl) +GCC_ASM_EXPORT (AA64ReadMair1) +GCC_ASM_EXPORT (AA64ReadMair2) +GCC_ASM_EXPORT (AA64ReadTcr1) +GCC_ASM_EXPORT (AA64ReadTcr2) +GCC_ASM_EXPORT (AA64ReadTtbr0El1) +GCC_ASM_EXPORT (AA64ReadTtbr0El2) +GCC_ASM_EXPORT (AA64ReadTtbr1El1) +GCC_ASM_EXPORT (AA64ReadTtbr1El2) ASM_PFX(ArmReadMpidr): mrs x0, mpidr_el1 // read EL1 MPIDR @@ -401,6 +409,38 @@ ASM_PFX(AA64ReadFar2): mrs x0, far_el2 ret +ASM_PFX(AA64ReadMair1): + mrs x0, mair_el1 // read EL1 MAIR + ret + +ASM_PFX(AA64ReadMair2): + mrs x0, mair_el2 // read EL2 MAIR + ret + +ASM_PFX(AA64ReadTcr1): + mrs x0, tcr_el1 // read EL1 TCR + ret + +ASM_PFX(AA64ReadTcr2): + mrs x0, tcr_el2 // read EL2 TCR + ret + +ASM_PFX(AA64ReadTtbr0El2): + mrs x0, ttbr0_el2 // read EL2 TTBR0 + ret + +ASM_PFX(AA64ReadTtbr1El2): + mrs x0, ttbr1_el2 // read EL2 TTBR1 + ret + +ASM_PFX(AA64ReadTtbr0El1): + mrs x0, ttbr0_el1 // read EL1 TTBR0 + ret + +ASM_PFX(AA64ReadTtbr1El1): + mrs x0, ttbr1_el1 // read EL1 TTBR1 + ret + ASM_PFX(ArmRdvl): //RDVL x0, #8 // TODO once instruction supports Read Vector Length .inst 0x04BF5100 diff --git a/val/src/avs_exerciser.c b/val/src/avs_exerciser.c index 8581f1f4..4123f065 100644 --- a/val/src/avs_exerciser.c +++ b/val/src/avs_exerciser.c @@ -18,6 +18,7 @@ #include "include/sbsa_avs_val.h" #include "include/sbsa_avs_exerciser.h" #include "include/sbsa_avs_pcie.h" +#include "include/sbsa_avs_smmu.h" EXERCISER_INFO_TABLE g_exercier_info_table; /** @@ -188,7 +189,6 @@ uint32_t val_exerciser_init(uint32_t instance) uint32_t val_exerciser_ops(EXERCISER_OPS ops, uint64_t param, uint32_t instance) { return pal_exerciser_ops(ops, param, g_exercier_info_table.e_info[instance].bdf); - } /** @@ -242,16 +242,21 @@ val_exerciser_execute_tests(uint32_t level) return AVS_STATUS_SKIP; } - status = e001_entry(); - status |= e002_entry(); - status |= e003_entry(); - status |= e004_entry(); - status |= e005_entry(); - status |= e006_entry(); - status |= e007_entry(); - status |= e008_entry(); - status |= e009_entry(); - status |= e010_entry(); + status = e001_entry(); + status |= e002_entry(); + status |= e003_entry(); + status |= e004_entry(); + status |= e005_entry(); + status |= e006_entry(); + status |= e007_entry(); + status |= e008_entry(); + status |= e009_entry(); + status |= e010_entry(); + status |= e011_entry(); + status |= e012_entry(); + status |= e013_entry(); + status |= e014_entry(); + status |= e015_entry(); if (status != AVS_STATUS_PASS) { val_print(AVS_PRINT_ERR, "\n One or more Exerciser tests have failed.... \n", status); diff --git a/val/src/avs_gic.c b/val/src/avs_gic.c index 3d04415c..76205e47 100644 --- a/val/src/avs_gic.c +++ b/val/src/avs_gic.c @@ -20,14 +20,6 @@ #include "include/sbsa_avs_gic_support.h" #include "include/sbsa_avs_common.h" -#define GICD_ISENABLER 0x100 -#define GICD_ICENABLER 0x180 -#define GICD_ISPENDR 0x200 -#define GICD_ISACTIVER0 0x300 -#define GICD_ICPENDR0 0x280 -#define GICD_ICACTIVER0 0x380 -#define GICD_IROUTER 0x6000 - GIC_INFO_TABLE *g_gic_info_table; /** @@ -266,6 +258,37 @@ void val_gic_cpuif_init(void) val_gic_reg_write(ICC_PMR_EL1, 0xff); } +/** + @brief This function will Get the trigger type Edge/Level + 1. Caller - Test Suite + 2. Prerequisite - val_gic_create_info_table + @param int_id Interrupt ID + @return Status +**/ +uint32_t val_gic_get_intr_trigger_type(uint32_t int_id, INTR_TRIGGER_INFO_TYPE_e *trigger_type) +{ + uint32_t reg_value; + uint32_t reg_offset; + uint32_t config_bit_shift; + + if (int_id > val_get_max_intid()) { + val_print(AVS_PRINT_ERR, "\n Invalid Interrupt ID number 0x%x ", int_id); + return AVS_STATUS_ERR; + } + + reg_offset = int_id / GICD_ICFGR_INTR_STRIDE; + config_bit_shift = GICD_ICFGR_INTR_CONFIG1(int_id); + + reg_value = val_mmio_read(val_get_gicd_base() + GICD_ICFGR + (4 * reg_offset)); + + if ((reg_value & (1 << config_bit_shift)) == 0) + *trigger_type = INTR_TRIGGER_INFO_LEVEL_HIGH; + else + *trigger_type = INTR_TRIGGER_INFO_EDGE_RISING; + + return 0; +} + /** @brief This function will Set the trigger type Edge/Level based on the GTDT table 1. Caller - Test Suite diff --git a/val/src/avs_gic_support.c b/val/src/avs_gic_support.c index 4fd1b30d..8d8dda2c 100644 --- a/val/src/avs_gic_support.c +++ b/val/src/avs_gic_support.c @@ -19,6 +19,8 @@ #include "include/sbsa_avs_gic.h" #include "include/sbsa_avs_gic_support.h" #include "include/sbsa_avs_common.h" +#include "include/sbsa_avs_pcie.h" +#include "include/sbsa_avs_iovirt.h" #ifndef TARGET_LINUX @@ -78,6 +80,21 @@ val_gic_reg_write(uint32_t reg_id, uint64_t write_data) } #endif +uint32_t +val_gic_is_valid_lpi(uint32_t int_id) +{ + uint32_t max_lpi_id = 0; + + max_lpi_id = pal_gic_get_max_lpi_id(); + + if ((int_id < LPI_MIN_ID) || (int_id > max_lpi_id)) { + /* Not Vaild LPI */ + return 0; + } + + return 1; /* Valid LPI */ +} + /** @brief This function is installs the ISR pointed by the function pointer the input Interrupt ID. @@ -95,8 +112,8 @@ val_gic_install_isr(uint32_t int_id, void (*isr)(void)) uint32_t reg_offset = int_id / 32; uint32_t reg_shift = int_id % 32; - if ((int_id > val_get_max_intid()) || (int_id == 0)) { - val_print(AVS_PRINT_ERR, "\n Invalid Interrupt ID number %d ", int_id); + if (((int_id > val_get_max_intid()) && (!val_gic_is_valid_lpi(int_id))) || (int_id == 0)) { + val_print(AVS_PRINT_ERR, "\n Invalid Interrupt ID number 0x%x ", int_id); return AVS_STATUS_ERR; } #endif @@ -104,7 +121,7 @@ val_gic_install_isr(uint32_t int_id, void (*isr)(void)) ret_val = pal_gic_install_isr(int_id, isr); #ifndef TARGET_LINUX - if (int_id > 31) { + if (int_id > 31 && int_id < 1024) { /**** UEFI GIC code is not enabling interrupt in the Distributor ***/ /**** So, do this here as a fail-safe. Remove if PAL guarantees this ***/ val_mmio_write(val_get_gicd_base() + GICD_ISENABLER + (4 * reg_offset), 1 << reg_shift); @@ -152,6 +169,69 @@ uint32_t val_gic_end_of_interrupt(uint32_t int_id) return 0; } +uint32_t val_gic_its_configure() +{ + uint32_t status; + + status = pal_gic_its_configure(); + + return status; +} + +void clear_msi_x_table(uint32_t bdf, uint32_t msi_index) +{ + + uint32_t msi_cap_offset, msi_table_bar_index; + uint32_t table_offset_reg, table_address; + uint32_t read_value; + + /* Get MSI Capability Offset */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset); + + /* Disable MSI-X in MSI-X Capability */ + val_pcie_read_cfg(bdf, msi_cap_offset, &read_value); + val_pcie_write_cfg(bdf, msi_cap_offset, (read_value & ((1ul << MSI_X_ENABLE_SHIFT) - 1))); + + /* Read MSI-X Table Address from the BAR Register */ + val_pcie_read_cfg(bdf, msi_cap_offset + MSI_X_TOR_OFFSET, &table_offset_reg); + msi_table_bar_index = table_offset_reg & MSI_X_TABLE_BIR_MASK; + val_pcie_read_cfg(bdf, TYPE01_BAR + msi_table_bar_index*4, &table_address); + + /* Clear MSI Table */ + val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_ADDR_OFFSET, 0); + val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_DATA_OFFSET, 0); + val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_MVC_OFFSET, 0x1); +} + +void fill_msi_x_table(uint32_t bdf, uint32_t msi_index, uint32_t msi_addr, uint32_t msi_data) +{ + + uint32_t msi_cap_offset, msi_table_bar_index; + uint32_t table_offset_reg, table_address, command_data; + uint32_t read_value; + + /* Enable Memory Space, Bus Master */ + val_pcie_read_cfg(bdf, TYPE01_CR, &command_data); + val_pcie_write_cfg(bdf, TYPE01_CR, (command_data | (1 << CR_MSE_SHIFT) | (1 << CR_BME_SHIFT))); + + /* Get MSI Capability Offset */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_MSIX, &msi_cap_offset); + + /* Enable MSI-X in MSI-X Capability */ + val_pcie_read_cfg(bdf, msi_cap_offset, &read_value); + val_pcie_write_cfg(bdf, msi_cap_offset, read_value | (1 << MSI_X_ENABLE_SHIFT)); + + /* Read MSI-X Table Address from the BAR Register */ + val_pcie_read_cfg(bdf, msi_cap_offset + MSI_X_TOR_OFFSET, &table_offset_reg); + msi_table_bar_index = table_offset_reg & MSI_X_TABLE_BIR_MASK; + val_pcie_read_cfg(bdf, TYPE01_BAR + msi_table_bar_index*4, &table_address); + + /* Fill MSI Table with msi_addr, msi_data */ + val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_ADDR_OFFSET, msi_addr); + val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_DATA_OFFSET, msi_data); + val_mmio_write(table_address + msi_index*MSI_X_ENTRY_SIZE + MSI_X_MSG_TBL_MVC_OFFSET, 0x0); +} + /** @brief This function clear the MSI related mappings. @@ -163,7 +243,23 @@ uint32_t val_gic_end_of_interrupt(uint32_t int_id) **/ void val_gic_free_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index) { - pal_gic_free_msi(bdf, IntID, msi_index); + uint32_t status; + uint32_t device_id, stream_id, its_id; + uint32_t req_id; + uint32_t bus = PCIE_EXTRACT_BDF_BUS(bdf); + uint32_t dev = PCIE_EXTRACT_BDF_DEV(bdf); + uint32_t func = PCIE_EXTRACT_BDF_FUNC(bdf); + + req_id = GET_DEVICE_ID(bus, dev, func); + + status = val_iovirt_get_device_info(req_id, PCIE_EXTRACT_BDF_SEG(bdf), &device_id, &stream_id, &its_id); + if (status) { /* Use Requester-Id if val_iovirt_get_device_info fails.*/ + device_id = req_id; + } + + pal_gic_free_msi(its_id, device_id, IntID, msi_index); + + clear_msi_x_table(bdf, msi_index); } /** @@ -177,5 +273,28 @@ void val_gic_free_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index) **/ uint32_t val_gic_request_msi(uint32_t bdf, uint32_t IntID, uint32_t msi_index) { - return pal_gic_request_msi(bdf, IntID, msi_index); + uint32_t status; + uint32_t msi_addr, msi_data; + uint32_t device_id, stream_id, its_id; + uint32_t req_id; + uint32_t bus = PCIE_EXTRACT_BDF_BUS(bdf); + uint32_t dev = PCIE_EXTRACT_BDF_DEV(bdf); + uint32_t func = PCIE_EXTRACT_BDF_FUNC(bdf); + + req_id = GET_DEVICE_ID(bus, dev, func); + + status = val_iovirt_get_device_info(req_id, PCIE_EXTRACT_BDF_SEG(bdf), &device_id, &stream_id, &its_id); + if (status) { /* Use Requester-Id if val_iovirt_get_device_info fails.*/ + device_id = req_id; + } + + status = pal_gic_request_msi(its_id, device_id, IntID, msi_index, &msi_addr, &msi_data); + if (status) { + /* MSI Assignment Failed. */ + return status; + } + + fill_msi_x_table(bdf, msi_index, msi_addr, msi_data); + + return status; } diff --git a/val/src/avs_iovirt.c b/val/src/avs_iovirt.c index 57b7a236..2c3a6ff5 100644 --- a/val/src/avs_iovirt.c +++ b/val/src/avs_iovirt.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -18,6 +18,7 @@ #include "include/sbsa_avs_val.h" #include "include/sbsa_avs_common.h" #include "include/sbsa_avs_iovirt.h" +#include "include/sbsa_avs_smmu.h" IOVIRT_INFO_TABLE *g_iovirt_info_table; @@ -150,14 +151,18 @@ val_iovirt_unique_rid_strid_map(uint32_t rc_index) @param segment pci_segment_number @param *device_id Pointer to device id @param *stream_id Pointer to stream id + @param *its_id Pointer to its id @return status **/ int -val_iovirt_get_device_id(uint32_t rid, uint32_t segment, uint32_t *device_id, uint32_t *stream_id) +val_iovirt_get_device_info(uint32_t rid, uint32_t segment, uint32_t *device_id, + uint32_t *stream_id, uint32_t *its_id) { uint32_t i, j, id = 0; - uint32_t str_id, oref; + uint32_t sid, did, oref; + uint32_t itsid = 0; + uint32_t mapping_found; IOVIRT_BLOCK *block; NODE_DATA_MAP *map; if (g_iovirt_info_table == NULL) @@ -165,64 +170,86 @@ val_iovirt_get_device_id(uint32_t rid, uint32_t segment, uint32_t *device_id, ui val_print(AVS_PRINT_ERR, "GET_DEVICE_ID: iovirt info table is not created \n", 0); return AVS_STATUS_ERR; } - if(!device_id) { + if (!device_id) { val_print(AVS_PRINT_ERR, "GET_DEVICE_ID: Invalid parameters\n", 0); return AVS_STATUS_ERR; } - if(!stream_id) - stream_id = &str_id; /* Search for root complex block with same segment number, and in whose id */ /* mapping range 'rid' falls. Calculate the output id */ block = &g_iovirt_info_table->blocks[0]; - for(i = 0; i < g_iovirt_info_table->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) + mapping_found = 0; + for (i = 0; i < g_iovirt_info_table->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block)) { - if(block->type != IOVIRT_NODE_PCI_ROOT_COMPLEX) - continue; - if(block->data.rc.segment != segment) - continue; - for(j = 0, map = &block->data_map[0]; j < block->num_data_map; j++, map++) + if (block->type == IOVIRT_NODE_PCI_ROOT_COMPLEX + && block->data.rc.segment == segment) { - if(rid >= (*map).map.input_base && rid <= ((*map).map.input_base + (*map).map.id_count)) + for (j = 0, map = &block->data_map[0]; j < block->num_data_map; j++, map++) { - id = (rid - (*map).map.input_base) + (*map).map.output_base; - oref = (*map).map.output_ref; - break; + if(rid >= (*map).map.input_base + && rid <= ((*map).map.input_base + (*map).map.id_count)) + { + id = (rid - (*map).map.input_base) + (*map).map.output_base; + oref = (*map).map.output_ref; + mapping_found = 1; + } } - } - if(id) break; + } } - if(!id) { - val_print(AVS_PRINT_ERR, "GET_DEVICE_ID: Requestor ID mapping not found\n", 0); + if (!mapping_found) { + val_print(AVS_PRINT_ERR, + "GET_DEVICE_ID: Requestor ID to Stream ID/Device ID mapping not found\n", 0); return AVS_STATUS_ERR; } /* If output reference node is to ITS group, 'id' is device id */ block = (IOVIRT_BLOCK*)((uint8_t*)g_iovirt_info_table + oref); if(block->type == IOVIRT_NODE_ITS_GROUP) { - *device_id = id; - *stream_id = 0; - return 0; + did = id; + sid = ~((uint32_t)0); + itsid = block->data_map[0].id[0]; } /* If output reference is to SMMU block, 'id' is stream id */ /* Go through id mappings of this block and find corresponding device id */ - if(block->type == IOVIRT_NODE_SMMU || block->type == IOVIRT_NODE_SMMU_V3) + else if(block->type == IOVIRT_NODE_SMMU || block->type == IOVIRT_NODE_SMMU_V3) { - *stream_id = id; + sid = id; id = 0; + mapping_found = 0; for(i = 0, map = &block->data_map[0]; i < block->num_data_map; i++, map++) { - if(*stream_id >= (*map).map.input_base && *stream_id <= ((*map).map.input_base + + if(sid >= (*map).map.input_base && sid <= ((*map).map.input_base + (*map).map.id_count)) { - *device_id = (*stream_id - (*map).map.input_base) + (*map).map.output_base; - return 0; + did = (sid - (*map).map.input_base) + (*map).map.output_base; + oref = (*map).map.output_ref; + mapping_found = 1; + break; } } + /* If output reference node is to ITS group */ + block = (IOVIRT_BLOCK*)((uint8_t*)g_iovirt_info_table + oref); + if(block->type == IOVIRT_NODE_ITS_GROUP) + itsid = block->data_map[0].id[0]; } - val_print(AVS_PRINT_ERR, "GET_DEVICE_ID: Device ID mapping not found\n", 0); - return AVS_STATUS_ERR; + else + { + val_print(AVS_PRINT_ERR, "GET_DEVICE_ID: Invalid mapping for RC in IORT\n", 0); + return AVS_STATUS_ERR; + } + if (!mapping_found) + { + val_print(AVS_PRINT_ERR, "GET_DEVICE_ID: Stream ID to Device ID mapping not found\n", 0); + return AVS_STATUS_ERR; + } + + if (its_id) + *its_id = itsid; + if (stream_id) + *stream_id = sid; + *device_id = did; + return 0; } /** @@ -250,6 +277,19 @@ val_iovirt_create_info_table(uint64_t *iovirt_info_table) val_print(AVS_PRINT_TEST, " SMMU_INFO: Number of SMMU CTRL : %x \n", val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0)); + +#ifndef TARGET_LINUX + uint32_t num_smmu; + uint32_t instance; + + val_smmu_init(); + + /* Disable All SMMU's */ + num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0); + for (instance = 0; instance < num_smmu; ++instance) + val_smmu_disable(instance); +#endif + } uint32_t @@ -262,6 +302,7 @@ val_iovirt_check_unique_ctx_intid(uint32_t smmu_index) void val_iovirt_free_info_table() { + val_smmu_stop(); pal_mem_free((void *)g_iovirt_info_table); } diff --git a/val/src/avs_memory.c b/val/src/avs_memory.c index 6cbdc4a7..304cee5e 100644 --- a/val/src/avs_memory.c +++ b/val/src/avs_memory.c @@ -187,9 +187,9 @@ val_memory_alloc(uint32_t size) } void * -val_memory_alloc_coherent(uint32_t bdf, uint32_t size, void *pa) +val_memory_alloc_cacheable(uint32_t bdf, uint32_t size, void **pa) { - return pal_mem_alloc_coherent(bdf, size, pa); + return pal_mem_alloc_cacheable(bdf, size, pa); } void @@ -211,9 +211,9 @@ val_memory_set(void *buf, uint32_t size, uint8_t value) } void -val_memory_free_coherent(uint32_t bdf, uint32_t size, void *va, void *pa) +val_memory_free_cacheable(uint32_t bdf, uint32_t size, void *va, void *pa) { - pal_mem_free_coherent(bdf, size, va, pa); + pal_mem_free_cacheable(bdf, size, va, pa); } void * @@ -222,8 +222,31 @@ val_memory_virt_to_phys(void *va) return pal_mem_virt_to_phys(va); } +void * +val_memory_phys_to_virt(uint64_t pa) +{ + return pal_mem_phys_to_virt(pa); +} + uint64_t val_memory_get_unpopulated_addr(addr_t *addr, uint32_t instance) { return pal_memory_get_unpopulated_addr(addr, instance); } + +uint32_t val_memory_page_size(void) +{ + return pal_mem_page_size(); +} + +void * +val_memory_alloc_pages(uint32_t num_pages) +{ + return pal_mem_alloc_pages(num_pages); +} + +void +val_memory_free_pages(void *addr, uint32_t num_pages) +{ + pal_mem_free_pages(addr, num_pages); +} diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c index 35afcd57..0af555f3 100644 --- a/val/src/avs_pcie.c +++ b/val/src/avs_pcie.c @@ -102,7 +102,7 @@ val_pcie_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data) uint32_t val_pcie_io_read_cfg(uint32_t bdf, uint32_t offset, uint32_t *data) { - return pal_pcie_read_cfg(bdf, offset, data); + return pal_pcie_io_read_cfg(bdf, offset, data); } /** @@ -162,6 +162,23 @@ val_pcie_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data) pal_mmio_write(ecam_base + cfg_addr + offset, data); } +/** + @brief Write 32bit data to PCIe config space pointed by Bus, + Device, Function and offset using UEFI PciIoProtocol interface + 1. Caller - Test Suite + 2. Prerequisite - val_pcie_create_info_table + @param bdf - concatenated Bus(8-bits), device(8-bits) & function(8-bits) + @param offset - Register offset within a device PCIe config space + @param data - 32-bit data write to the config space + + @return success/failure +**/ +void +val_pcie_io_write_cfg(uint32_t bdf, uint32_t offset, uint32_t data) +{ + return pal_pcie_io_write_cfg(bdf, offset, data); +} + /** @brief This API returns function config space addr. 1. Caller - Test Suite @@ -263,6 +280,7 @@ val_pcie_execute_tests(uint32_t enable_pcie, uint32_t level, uint32_t num_pe) } status |= p002_entry(num_pe); + status |= p003_entry(num_pe); #ifdef TARGET_LINUX status |= p004_entry(num_pe); status |= p005_entry(num_pe); @@ -323,6 +341,18 @@ val_pcie_execute_tests(uint32_t enable_pcie, uint32_t level, uint32_t num_pe) status |= p043_entry(num_pe); status |= p044_entry(num_pe); status |= p045_entry(num_pe); + status |= p046_entry(num_pe); + status |= p047_entry(num_pe); + status |= p048_entry(num_pe); + status |= p049_entry(num_pe); + status |= p050_entry(num_pe); + status |= p051_entry(num_pe); + status |= p052_entry(num_pe); + status |= p053_entry(num_pe); + status |= p054_entry(num_pe); + status |= p055_entry(num_pe); + status |= p056_entry(num_pe); + status |= p057_entry(num_pe); } #endif @@ -719,15 +749,26 @@ val_pcie_get_device_type(uint32_t bdf) } /** - @brief This API checks the PCIe device P2P support + @brief This API checks the PCIe Hierarchy P2P support + 1. Caller - Test Suite + @return 1 - P2P feature not supported 0 - P2P feature supported +**/ +uint32_t +val_pcie_p2p_support() +{ + return pal_pcie_p2p_support(); +} + +/** + @brief This API checks the PCIe Root port supports P2P with other RP's 1. Caller - Test Suite @param bdf - PCIe BUS/Device/Function @return 1 - P2P feature not supported 0 - P2P feature supported **/ uint32_t -val_pcie_p2p_support(uint32_t bdf) +val_pcie_dev_p2p_support(uint32_t bdf) { - return pal_pcie_p2p_support(PCIE_EXTRACT_BDF_SEG (bdf), + return pal_pcie_dev_p2p_support(PCIE_EXTRACT_BDF_SEG (bdf), PCIE_EXTRACT_BDF_BUS (bdf), PCIE_EXTRACT_BDF_DEV (bdf), PCIE_EXTRACT_BDF_FUNC (bdf)); @@ -737,15 +778,16 @@ val_pcie_p2p_support(uint32_t bdf) @brief This API checks the PCIe device multifunction support 1. Caller - Test Suite @param bdf - PCIe BUS/Device/Function - @return 1 - Multifunction not supported 0 - Multifunction supported + @return 0 - Multifunction not supported 1 - Multifunction supported **/ uint32_t val_pcie_multifunction_support(uint32_t bdf) { - return pal_pcie_multifunction_support(PCIE_EXTRACT_BDF_SEG (bdf), - PCIE_EXTRACT_BDF_BUS (bdf), - PCIE_EXTRACT_BDF_DEV (bdf), - PCIE_EXTRACT_BDF_FUNC (bdf)); + uint32_t reg_data; + val_pcie_read_cfg(bdf, TYPE01_CLSR, ®_data); + reg_data = ((reg_data >> TYPE01_HTR_SHIFT) & TYPE01_HTR_MASK); + + return ((reg_data >> HTR_MFD_SHIFT) & HTR_MFD_MASK); } /** @@ -1207,6 +1249,81 @@ val_pcie_is_urd(uint32_t bdf) return 0; } +/** + @brief Clears Error detected bit in Device Status Register + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return None +**/ +void +val_pcie_clear_device_status_error(uint32_t bdf) +{ + + uint32_t pciecs_base; + uint32_t reg_value; + + /* + * Get the PCI Express Capability structure offset and use that + * offset to write 1b to clear CED, NFED, FED, URD bit in Device Status register + */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_read_cfg(bdf, pciecs_base + DCTLR_OFFSET, ®_value); + reg_value = reg_value | (0xF << DCTLR_DSR_SHIFT); + val_pcie_write_cfg(bdf, pciecs_base + DCTLR_OFFSET, reg_value); + +} + +/** + @brief Check Error detected bit in Device Status Register + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return 1 if Error is detected, 0 if No Error +**/ +uint32_t +val_pcie_is_device_status_error(uint32_t bdf) +{ + + uint32_t pciecs_base; + uint32_t reg_value; + + /* + * Get the PCI Express Capability structure offset and use that + * offset to check CED, NFED, FED, URD bit in Device Status register + */ + val_pcie_find_capability(bdf, PCIE_CAP, CID_PCIECS, &pciecs_base); + val_pcie_read_cfg(bdf, pciecs_base + DCTLR_OFFSET, ®_value); + + if (reg_value & (0xF << DCTLR_DSR_SHIFT)) + return 1; + + return 0; +} + +/** + @brief Check Signaled Target Abort bit in Status/Secondary Status Register + in Root Port + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return 1 if STA Bit Set, 0 if Not Set +**/ +uint32_t +val_pcie_is_sig_target_abort(uint32_t bdf) +{ + + uint32_t status_val; + uint32_t sec_status_val; + + /* Read Status Register at 0x4 Offset */ + val_pcie_read_cfg(bdf, TYPE01_CR, &status_val); + /* Read Secondary Status Register at 0x1C Offset */ + val_pcie_read_cfg(bdf, TYPE1_SEC_STA, &sec_status_val); + + if (((status_val >> SR_STA_SHIFT) & SR_STA_MASK) || + ((sec_status_val >> SSR_STA_SHIFT) & SSR_STA_MASK)) + return 1; + + return 0; +} + /** @brief Disable error reporting of the PCIe Function to the upstream @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF @@ -1660,8 +1777,9 @@ val_pcie_get_rootport(uint32_t bdf, uint32_t *rp_bdf) val_pcie_read_cfg(*rp_bdf, TYPE1_PBN, ®_value); sec_bus = ((reg_value >> SECBN_SHIFT) & SECBN_MASK); sub_bus = ((reg_value >> SUBBN_SHIFT) & SUBBN_MASK); + dp_type = val_pcie_device_port_type(*rp_bdf); - if ((val_pcie_device_port_type(*rp_bdf) == RP) && + if (((dp_type == RP) || (dp_type = iEP_RP)) && (sec_bus <= PCIE_EXTRACT_BDF_BUS(bdf)) && (sub_bus >= PCIE_EXTRACT_BDF_BUS(bdf))) return 0; @@ -1729,3 +1847,18 @@ val_pcie_is_host_bridge(uint32_t bdf) return 0; } + +/** + @brief Returns whether a PCIe Function has an Address Translation Cache + + @param bdf - Segment/Bus/Dev/Func in the format of PCIE_CREATE_BDF + @return Returns 0 - if Function doesn't have Addr Translation Cache else 1. +**/ +uint32_t +val_pcie_is_cache_present(uint32_t bdf) +{ + return pal_pcie_is_cache_present(PCIE_EXTRACT_BDF_SEG (bdf), + PCIE_EXTRACT_BDF_BUS (bdf), + PCIE_EXTRACT_BDF_DEV (bdf), + PCIE_EXTRACT_BDF_FUNC (bdf)); +} diff --git a/val/src/avs_pe.c b/val/src/avs_pe.c index b9f86bca..7a542922 100644 --- a/val/src/avs_pe.c +++ b/val/src/avs_pe.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -91,6 +91,19 @@ val_pe_execute_tests(uint32_t level, uint32_t num_pe) status |= c027_entry(num_pe); } + if (level > 5) { + status |= c029_entry(num_pe); + status |= c030_entry(num_pe); + status |= c031_entry(num_pe); + status |= c032_entry(num_pe); + status |= c033_entry(num_pe); + status |= c034_entry(num_pe); + status |= c035_entry(num_pe); + status |= c036_entry(num_pe); + status |= c037_entry(num_pe); + status |= c038_entry(num_pe); + } + if (status != AVS_STATUS_PASS) val_print(AVS_PRINT_TEST, "\n *** One or more PE tests have failed... *** \n", 0); else @@ -220,12 +233,21 @@ val_pe_reg_read(uint32_t reg_id) return AA64ReadFar2(); case RDVL: return ArmRdvl(); + case MAIR_ELx: + if (AA64ReadCurrentEL() == AARCH64_EL1) + return AA64ReadMair1(); + if (AA64ReadCurrentEL() == AARCH64_EL2) + return AA64ReadMair2(); + case TCR_ELx: + if (AA64ReadCurrentEL() == AARCH64_EL1) + return AA64ReadTcr1(); + if (AA64ReadCurrentEL() == AARCH64_EL2) + return AA64ReadTcr2(); default: val_report_status(val_pe_get_index_mpid(val_pe_get_mpid()), RESULT_FAIL(g_sbsa_level, 0, 0x78)); } return 0x0; - } /** @@ -372,3 +394,65 @@ val_pe_spe_disable(void) { DisableSpe(); } + +uint32_t val_pe_reg_read_tcr(uint32_t ttbr1, PE_TCR_BF *tcr) +{ + uint64_t val = val_pe_reg_read(TCR_ELx); + uint32_t el = AA64ReadCurrentEL() & AARCH64_EL_MASK; + uint8_t tg_ttbr0[3] = {12 /*4KB*/, 16 /*64KB*/, 14 /*16KB*/}; + uint8_t tg_ttbr1[4] = {0 /* N/A */, 14 /*16KB*/, 12 /*4KB*/, 16 /* 64KB*/}; + uint64_t e2h; + + if ((tcr == NULL) || + (el != AARCH64_EL1 && el != AARCH64_EL2)) + return AVS_STATUS_ERR; + + if (el == AARCH64_EL2) + e2h = ArmReadHcr() & AARCH64_HCR_E2H_MASK; + + if (el == AARCH64_EL1 || (el == AARCH64_EL2 && e2h)) + { + tcr->ps = (val & SBSA_TCR_IPS_MASK) >> SBSA_TCR_IPS_SHIFT; + if (ttbr1) { + tcr->tg = (val & SBSA_TCR_TG1_MASK) >> SBSA_TCR_TG1_SHIFT; + if (tcr->tg == 0 || tcr->tg > 3) + return AVS_STATUS_ERR; + tcr->tg_size_log2 = tg_ttbr1[tcr->tg]; + tcr->sh = (val & SBSA_TCR_SH1_MASK) >> SBSA_TCR_SH1_SHIFT; + tcr->orgn = (val & SBSA_TCR_ORGN1_MASK) >> SBSA_TCR_ORGN1_SHIFT; + tcr->irgn = (val & SBSA_TCR_IRGN1_MASK) >> SBSA_TCR_IRGN1_SHIFT; + tcr->tsz = (val & SBSA_TCR_T1SZ_MASK) >> SBSA_TCR_T1SZ_SHIFT; + return 0; + } + } + else if (!ttbr1) + tcr->ps = (val & SBSA_TCR_PS_MASK) >> SBSA_TCR_PS_SHIFT; + else + return AVS_STATUS_ERR; + + tcr->tg = (val & SBSA_TCR_TG0_MASK) >> SBSA_TCR_TG0_SHIFT; + if (tcr->tg > 2) + return AVS_STATUS_ERR; + tcr->tg_size_log2 = tg_ttbr0[tcr->tg]; + tcr->sh = (val & SBSA_TCR_SH0_MASK) >> SBSA_TCR_SH0_SHIFT; + tcr->orgn = (val & SBSA_TCR_ORGN0_MASK) >> SBSA_TCR_ORGN0_SHIFT; + tcr->irgn = (val & SBSA_TCR_IRGN0_MASK) >> SBSA_TCR_IRGN0_SHIFT; + tcr->tsz = (val & SBSA_TCR_T0SZ_MASK) >> SBSA_TCR_T0SZ_SHIFT; + return 0; +} + +uint32_t val_pe_reg_read_ttbr(uint32_t ttbr1, uint64_t *ttbr_ptr) +{ + uint32_t el = AA64ReadCurrentEL() & AARCH64_EL_MASK; + typedef uint64_t (*ReadTtbr_t)(); + ReadTtbr_t ReadTtbr[2][2] = {{AA64ReadTtbr0El1, AA64ReadTtbr0El2}, + {AA64ReadTtbr1El1, AA64ReadTtbr1El2}}; + + if ((ttbr_ptr == NULL) || + (el != AARCH64_EL1 && el != AARCH64_EL2) || + ttbr1 > 1) + return AVS_STATUS_ERR; + + *ttbr_ptr = ReadTtbr[ttbr1][(el >> 2) - 1](); + return 0; +} diff --git a/val/src/avs_pgt.c b/val/src/avs_pgt.c new file mode 100644 index 00000000..23faa50d --- /dev/null +++ b/val/src/avs_pgt.c @@ -0,0 +1,321 @@ +/** @file + * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * SPDX-License-Identifier : Apache-2.0 + + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **/ + +#include "include/sbsa_avs_val.h" +#include "include/sbsa_avs_common.h" + +#include "include/sbsa_avs_pgt.h" +#include "include/sbsa_avs_memory.h" + +#define get_min(a, b) ((a) < (b))?(a):(b) + +#define PGT_DEBUG_LEVEL AVS_PRINT_INFO + +static uint32_t page_size; +static uint32_t bits_per_level; +static uint64_t pgt_addr_mask; + +typedef struct +{ + uint64_t *tt_base; + uint64_t input_base; + uint64_t input_top; + uint64_t output_base; + uint32_t level; + uint32_t size_log2; + uint32_t nbits; +} tt_descriptor_t; + +uint32_t fill_translation_table(tt_descriptor_t tt_desc, memory_region_descriptor_t *mem_desc) +{ + uint64_t block_size = 0x1ull << tt_desc.size_log2; + uint64_t input_address, output_address, table_index, *tt_base_next_level, *table_desc; + tt_descriptor_t tt_desc_next_level; + + val_print(PGT_DEBUG_LEVEL, "\n tt_desc.level: %d ", tt_desc.level); + val_print(PGT_DEBUG_LEVEL, "\n tt_desc.input_base: 0x%llx ", tt_desc.input_base); + val_print(PGT_DEBUG_LEVEL, "\n tt_desc.input_top: 0x%llx ", tt_desc.input_top); + val_print(PGT_DEBUG_LEVEL, "\n tt_desc.output_base: 0x%llx ", tt_desc.output_base); + val_print(PGT_DEBUG_LEVEL, "\n tt_desc.size_log2: %d ", tt_desc.size_log2); + val_print(PGT_DEBUG_LEVEL, "\n tt_desc.nbits: %d ", tt_desc.nbits); + + for (input_address = tt_desc.input_base, output_address = tt_desc.output_base; + input_address < tt_desc.input_top; + input_address += block_size, output_address += block_size) + { + table_index = input_address >> tt_desc.size_log2 & ((0x1ull << tt_desc.nbits) - 1); + table_desc = &tt_desc.tt_base[table_index]; + + val_print(PGT_DEBUG_LEVEL, "\n table_index = %d ", table_index); + + if (tt_desc.level == 3) + { + //Create level 3 page descriptor entry + *table_desc = PGT_ENTRY_PAGE_MASK | PGT_ENTRY_VALID_MASK; + *table_desc |= (output_address & ~(page_size - 1)); + *table_desc |= mem_desc->attributes; + val_print(PGT_DEBUG_LEVEL, "\n page_descriptor = 0x%llx ", *table_desc); + continue; + } + + //Are input and output addresses eligible for being described via block descriptor? + if ((input_address & (block_size - 1)) == 0 && + (output_address & (block_size - 1)) == 0 && + tt_desc.input_top >= (input_address + block_size - 1)) { + //Create a block descriptor entry + *table_desc = PGT_ENTRY_BLOCK_MASK | PGT_ENTRY_VALID_MASK; + *table_desc |= (output_address & ~(block_size - 1)); + *table_desc |= mem_desc->attributes; + val_print(PGT_DEBUG_LEVEL, "\n block_descriptor = 0x%llx ", *table_desc); + continue; + } + /* + If there's no descriptor populated at current index of this page_table, or + If there's a block descriptor, allocate new page, else use the already populated address. + Block descriptor info will be overwritten in case its there. + */ + if (*table_desc == 0 || IS_PGT_ENTRY_BLOCK(*table_desc)) + { + tt_base_next_level = val_memory_alloc_pages(1); + if (tt_base_next_level == NULL) + { + val_print(AVS_PRINT_ERR, "\n fill_translation_table: page allocation failed ", 0); + return AVS_STATUS_ERR; + } + val_memory_set(tt_base_next_level, page_size, 0); + } + else + tt_base_next_level = val_memory_phys_to_virt(*table_desc & pgt_addr_mask); + + tt_desc_next_level.tt_base = tt_base_next_level; + tt_desc_next_level.input_base = input_address; + tt_desc_next_level.input_top = get_min(tt_desc.input_top, (input_address + block_size - 1)); + tt_desc_next_level.output_base = output_address; + tt_desc_next_level.level = tt_desc.level + 1; + tt_desc_next_level.size_log2 = tt_desc.size_log2 - bits_per_level; + tt_desc_next_level.nbits = bits_per_level; + + if (fill_translation_table(tt_desc_next_level, mem_desc)) + { + val_memory_free_pages(tt_base_next_level, 1); + return AVS_STATUS_ERR; + } + + *table_desc = PGT_ENTRY_TABLE_MASK | PGT_ENTRY_VALID_MASK; + *table_desc |= (uint64_t)val_memory_virt_to_phys(tt_base_next_level) & ~(page_size - 1); + val_print(PGT_DEBUG_LEVEL, "\n table_descriptor = 0x%llx ", *table_desc); + } + return 0; +} + +uint32_t log2_page_size(uint64_t size) +{ + int bit = 0; + while (size != 0) + { + if (size & 1) + return bit; + size >>= 1; + ++bit; + } + return 0; +} + +/** + @brief Create stage 1 or stage 2 page table, with given memory addresses and attributes + @param mem_desc - Array of memory addresses and attributes needed for page table creation. + @param pgt_desc - Data structure for output page table base and input translation attributes. + @return status +**/ +uint32_t val_pgt_create(memory_region_descriptor_t *mem_desc, pgt_descriptor_t *pgt_desc) +{ + uint64_t *tt_base; + tt_descriptor_t tt_desc; + uint32_t num_pgt_levels, page_size_log2; + memory_region_descriptor_t *mem_desc_iter; + + page_size = val_memory_page_size(); + page_size_log2 = log2_page_size(page_size); + bits_per_level = page_size_log2 - 3; + num_pgt_levels = (pgt_desc->ias - page_size_log2 + bits_per_level - 1)/bits_per_level; + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_create: nbits_per_level = %d ", bits_per_level); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_create: page_size_log2 = %d ", page_size_log2); + + tt_base = (uint64_t*) val_memory_alloc_pages(1); + if (tt_base == NULL) + { + val_print(AVS_PRINT_ERR, "\n val_pgt_create: page allocation failed ", 0); + return AVS_STATUS_ERR; + } + val_memory_set(tt_base, page_size, 0); + tt_desc.tt_base = tt_base; + pgt_addr_mask = ((0x1ull << (48 - page_size_log2)) - 1) << page_size_log2; + + for (mem_desc_iter = mem_desc; mem_desc_iter->length != 0; ++mem_desc_iter) + { + val_print(PGT_DEBUG_LEVEL, " val_pgt_create: input addr = 0x%x ", mem_desc->virtual_address); + val_print(PGT_DEBUG_LEVEL, " val_pgt_create: output addr = 0x%x ", mem_desc->physical_address); + val_print(PGT_DEBUG_LEVEL, " val_pgt_create: length = 0x%x\n ", mem_desc->length); + if ((mem_desc->virtual_address & (uint64_t)(page_size - 1)) != 0 || + (mem_desc->physical_address & (uint64_t)(page_size - 1)) != 0) + { + val_print(AVS_PRINT_ERR, "\n val_pgt_create: address alignment error ", 0); + return AVS_STATUS_ERR; + } + + if (mem_desc->physical_address >= (0x1ull << pgt_desc->oas)) + { + val_print(AVS_PRINT_ERR, "\n val_pgt_create: output address size error ", 0); + return AVS_STATUS_ERR; + } + + if (mem_desc->virtual_address >= (0x1ull << pgt_desc->ias)) + { + val_print(AVS_PRINT_WARN, "\n val_pgt_create: input address size error, truncating to %d-bits ", pgt_desc->ias); + mem_desc->virtual_address &= ((0x1ull << pgt_desc->ias) - 1); + } + + if ((pgt_desc->tcr.tg_size_log2) != page_size_log2) + { + val_print(AVS_PRINT_ERR, "\n val_pgt_create: input page_size 0x%x not supported ", (0x1 << pgt_desc->tcr.tg_size_log2)); + return AVS_STATUS_ERR; + } + + tt_desc.input_base = mem_desc->virtual_address & ((0x1ull << pgt_desc->ias) - 1); + tt_desc.input_top = tt_desc.input_base + mem_desc->length - 1; + tt_desc.output_base = mem_desc->physical_address & ((0x1ull << pgt_desc->oas) - 1); + tt_desc.level = 4 - num_pgt_levels; + tt_desc.size_log2 = (num_pgt_levels - 1) * bits_per_level + page_size_log2; + tt_desc.nbits = pgt_desc->ias - tt_desc.size_log2; + + if (fill_translation_table(tt_desc, mem_desc)) + { + val_memory_free_pages(tt_base, 1); + return AVS_STATUS_ERR; + } + } + + pgt_desc->pgt_base = (uint64_t)val_memory_virt_to_phys(tt_base); + + return 0; +} + +/** + @brief Get attributes of a page corresponding to a given virtual address. + @param pgt_desc - page table base and translation attributes. + @param virtual_address - virtual address of memory region base whose attribute is to be read. + @param attributes - output attributes + @return status +**/ +uint64_t val_pgt_get_attributes(pgt_descriptor_t pgt_desc, uint64_t virtual_address, uint64_t *attributes) +{ + uint32_t ias, index, num_pgt_levels, this_level; + uint32_t bits_at_this_level, bits_remaining; + uint64_t val64, tt_base_phys, *tt_base_virt; + uint32_t page_size_log2 = pgt_desc.tcr.tg_size_log2; + + if (attributes == NULL) + return AVS_STATUS_ERR; + + if (!pgt_desc.pgt_base) + return AVS_STATUS_ERR; + + ias = 64 - pgt_desc.tcr.tsz; + + bits_per_level = page_size_log2 - 3; + num_pgt_levels = (ias - page_size_log2 + bits_per_level - 1)/bits_per_level; + this_level = 4 - num_pgt_levels; + bits_remaining = (num_pgt_levels - 1) * bits_per_level + page_size_log2; + bits_at_this_level = ias - bits_remaining; + tt_base_phys = pgt_desc.pgt_base; + + while (1) { + index = (virtual_address >> bits_remaining) & ((0x1u << bits_at_this_level) - 1); + tt_base_virt = (uint64_t*)val_memory_phys_to_virt(tt_base_phys); + val64 = tt_base_virt[index]; + + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: this_level = %d ", this_level); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: index = %d ", index); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: bits_remaining = %d ", bits_remaining); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: tt_base_virt = %x ", (uint64_t)tt_base_virt); + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_get_attributes: val64 = %x ", val64); + if (this_level == 3) + { + if (!IS_PGT_ENTRY_PAGE(val64)) + return AVS_STATUS_ERR; + *attributes = PGT_DESC_ATTRIBUTES(val64); + return 0; + } + if (IS_PGT_ENTRY_BLOCK(val64)) { + *attributes = PGT_DESC_ATTRIBUTES(val64); + return 0; + } + tt_base_phys = val64 & (((0x1ull << (ias - page_size_log2)) - 1) << page_size_log2); + ++this_level; + bits_remaining -= bits_at_this_level; + bits_at_this_level = bits_per_level; + } +} + +static void free_translation_table(uint64_t *tt_base, uint32_t bits_at_this_level, uint32_t this_level) +{ + uint32_t index; + uint64_t *tt_base_next_virt; + + if (this_level == 3) + return; + for (index = 0; index < (0x1ul << bits_at_this_level); ++index) + { + if (tt_base[index] != 0) + { + if (IS_PGT_ENTRY_BLOCK(tt_base[index])) + continue; + tt_base_next_virt = val_memory_phys_to_virt((tt_base[index] & pgt_addr_mask)); + if (tt_base_next_virt == NULL) + continue; + free_translation_table(tt_base_next_virt, bits_per_level, this_level+1); + val_print(PGT_DEBUG_LEVEL, "\n free_translation_table: tt_base_next_virt = %llx ", (uint64_t)tt_base_next_virt); + val_memory_free_pages(tt_base_next_virt, 1); + } + } +} + +/** + @brief Free all page tables in the page table hierarchy starting from the base page table. + @param pgt_desc - page table base and translation attributes. + @return void +**/ +void val_pgt_destroy(pgt_descriptor_t pgt_desc) +{ + uint32_t page_size_log2, num_pgt_levels; + uint64_t *pgt_base_virt = val_memory_phys_to_virt(pgt_desc.pgt_base); + + if (!pgt_desc.pgt_base) + return; + + val_print(PGT_DEBUG_LEVEL, "\n val_pgt_destroy: pgt_base = %llx ", pgt_desc.pgt_base); + page_size = val_memory_page_size(); + page_size_log2 = log2_page_size(page_size); + bits_per_level = page_size_log2 - 3; + pgt_addr_mask = ((0x1ull << (pgt_desc.ias - page_size_log2)) - 1) << page_size_log2; + num_pgt_levels = (pgt_desc.ias - page_size_log2 + bits_per_level - 1)/bits_per_level; + + free_translation_table(pgt_base_virt, + pgt_desc.ias - ((num_pgt_levels - 1) * bits_per_level + page_size_log2), + 4 - num_pgt_levels); + val_memory_free_pages(pgt_base_virt, 1); +} diff --git a/val/src/avs_smmu.c b/val/src/avs_smmu.c index 33c8c177..d17fcb1c 100644 --- a/val/src/avs_smmu.c +++ b/val/src/avs_smmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -56,8 +56,7 @@ uint32_t val_smmu_execute_tests(uint32_t level, uint32_t num_pe) { uint32_t status, i; - - + uint32_t status_version_chk; for (i=0 ; i 5) { + if (status_version_chk != AVS_STATUS_PASS) { + val_print(AVS_PRINT_ERR, "\n SMMU Version Not Compliant, Skipping Remaining SMMU Tests...\n", 0); + } else { + status |= i008_entry(num_pe); + status |= i009_entry(num_pe); + status |= i010_entry(num_pe); + status |= i011_entry(num_pe); + status |= i012_entry(num_pe); + status |= i013_entry(num_pe); + status |= i014_entry(num_pe); + status |= i015_entry(num_pe); + status |= i016_entry(num_pe); + } + } + if (status != AVS_STATUS_PASS) { val_print(AVS_PRINT_ERR, "\n One or more SMMU tests have failed... \n", status); } @@ -81,14 +99,6 @@ val_smmu_execute_tests(uint32_t level, uint32_t num_pe) } #endif - -uint64_t -val_smmu_get_info(SMMU_INFO_e type, uint32_t index) -{ - return val_iovirt_get_smmu_info(type, index); -} - - uint32_t val_smmu_start_monitor_dev(uint32_t ctrl_index) { @@ -191,15 +201,6 @@ val_smmu_create_pasid_entry(uint32_t smmu_index, uint32_t pasid) return pal_smmu_create_pasid_entry(smmu_base, pasid); } -uint32_t -val_smmu_disable(uint32_t smmu_index) -{ - uint64_t smmu_base; - - smmu_base = val_smmu_get_info(SMMU_CTRL_BASE, smmu_index); - return pal_smmu_disable(smmu_base); -} - uint64_t val_smmu_pa2iova(uint32_t smmu_index, uint64_t pa) { diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c index 37c908ee..6af8de36 100644 --- a/val/src/avs_test_infra.c +++ b/val/src/avs_test_infra.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -62,6 +62,40 @@ val_print_raw(uint32_t level, char8_t *string, uint64_t data) } +/** + @brief This API calls PAL layer to read from a Memory address + and return 8-bit data. + 1. Caller - Test Suite + 2. Prerequisite - None. + + @param addr 64-bit address + + @return 8-bits of data + **/ +uint8_t +val_mmio_read8(addr_t addr) +{ + return pal_mmio_read8(addr); + +} + +/** + @brief This API calls PAL layer to read from a Memory address + and return 16-bit data. + 1. Caller - Test Suite + 2. Prerequisite - None. + + @param addr 64-bit address + + @return 16-bits of data + **/ +uint16_t +val_mmio_read16(addr_t addr) +{ + return pal_mmio_read16(addr); + +} + /** @brief This API calls PAL layer to read from a Memory address and return 32-bit data. @@ -79,6 +113,59 @@ val_mmio_read(addr_t addr) } +/** + @brief This API calls PAL layer to read from a Memory address + and return 64-bit data. + 1. Caller - Test Suite + 2. Prerequisite - None. + + @param addr 64-bit address + + @return 64-bits of data + **/ +uint64_t +val_mmio_read64(addr_t addr) +{ + return pal_mmio_read64(addr); + +} + +/** + @brief This function will call PAL layer to write 8-bit data to + a Memory address. + 1. Caller - Test Suite + 2. Prerequisite - None. + + @param addr 64-bit address + @param data 8-bit data + + @return None + **/ +void +val_mmio_write8(addr_t addr, uint8_t data) +{ + + pal_mmio_write8(addr, data); +} + +/** + @brief This function will call PAL layer to write 16-bit data to + a Memory address. + 1. Caller - Test Suite + 2. Prerequisite - None. + + @param addr 64-bit address + @param data 16-bit data + + @return None + **/ +void +val_mmio_write16(addr_t addr, uint16_t data) +{ + + pal_mmio_write16(addr, data); +} + /** @brief This function will call PAL layer to write 32-bit data to a Memory address. @@ -96,6 +183,23 @@ val_mmio_write(addr_t addr, uint32_t data) pal_mmio_write(addr, data); } +/** + @brief This function will call PAL layer to write 64-bit data to + a Memory address. + 1. Caller - Test Suite + 2. Prerequisite - None. + + @param addr 64-bit address + @param data 64-bit data + + @return None + **/ +void +val_mmio_write64(addr_t addr, uint64_t data) +{ + + pal_mmio_write64(addr, data); +} /** @brief This API prinst the test number, description and diff --git a/val/src/avs_wd.c b/val/src/avs_wd.c index ccf955a7..63b29590 100644 --- a/val/src/avs_wd.c +++ b/val/src/avs_wd.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2020, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -46,6 +46,7 @@ val_wd_execute_tests(uint32_t level, uint32_t num_pe) status = w001_entry(num_pe); status |= w002_entry(num_pe); + status |= w003_entry(num_pe); if (status != 0) val_print(AVS_PRINT_TEST, "\n ***One or more tests have failed... *** \n", 0); diff --git a/val/sys_arch_src/smmu_v3/smmu_reg.h b/val/sys_arch_src/smmu_v3/smmu_reg.h new file mode 100644 index 00000000..c9f05776 --- /dev/null +++ b/val/sys_arch_src/smmu_v3/smmu_reg.h @@ -0,0 +1,185 @@ +/* + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SMMU_REG_H__ +#define __SMMU_REG_H__ + +#define BITFIELD_DECL(type, name, msb, lsb) \ + const uint32_t name##_SHIFT = lsb; \ + const type name##_MASK = ((((type)0x1) << (msb - lsb +1)) - 1); + +#define BITFIELD_GET(name, val) ((val >> name##_SHIFT) & name##_MASK) +#define BITFIELD_SET(name, val) ((val & name##_MASK) << name##_SHIFT) + +#define BYTES_PER_DWORD 8 + +BITFIELD_DECL(uint32_t, IDR0_ST_LEVEL, 28, 27) +#define SMMU_IDR0_OFFSET 0x0 +#define IDR0_ST_LEVEL_2LVL 1 +#define IDR0_CD2L (1 << 19) +#define IDR0_HYP (1 << 9) +#define IDR0_COHACC (1 << 4) + +BITFIELD_DECL(uint32_t, IDR0_TTF, 3, 2) +#define IDR0_TTF_AARCH64 2 +#define IDR0_TTF_AARCH32_64 3 +#define IDR0_S1P (1 << 1) +#define IDR0_S2P (1 << 0) + +#define SMMU_IDR1_OFFSET 0x4 +#define IDR1_TABLES_PRESET (1 << 30) +#define IDR1_QUEUES_PRESET (1 << 29) +#define IDR1_REL (1 << 28) +BITFIELD_DECL(uint32_t, IDR1_CMDQS, 25, 21) +BITFIELD_DECL(uint32_t, IDR1_SSIDSIZE, 10, 6) +BITFIELD_DECL(uint32_t, IDR1_SIDSIZE, 5, 0) + + +#define SMMU_IDR5_OFFSET 0x14 +BITFIELD_DECL(uint32_t, IDR5_OAS, 2, 0) +#define SMMU_OAS_MAX_IDX 7 +uint32_t smmu_oas[SMMU_OAS_MAX_IDX] = {32, 36, 40, 42, 44, 48, 52}; + +#define SMMU_CR0_OFFSET 0x20 +#define CR0_CMDQEN (1 << 3) +#define CR0_SMMUEN (1 << 0) + +#define SMMU_CR0ACK_OFFSET 0x24 + +#define SMMU_CR1_OFFSET 0x28 +BITFIELD_DECL(uint32_t, CR1_TABLE_SH, 11, 10) +BITFIELD_DECL(uint32_t, CR1_TABLE_OC, 9, 8) +BITFIELD_DECL(uint32_t, CR1_TABLE_IC, 7, 6) +BITFIELD_DECL(uint32_t, CR1_QUEUE_SH, 5, 4) +BITFIELD_DECL(uint32_t, CR1_QUEUE_OC, 3, 2) +BITFIELD_DECL(uint32_t, CR1_QUEUE_IC, 1, 0) +#define CR1_CACHE_NC 0 +#define CR1_CACHE_WB 1 +#define CR1_CACHE_WT 2 + +#define SMMU_CR2_OFFSET 0x2c +#define SMMU_GERROR_OFFSET 0x60 + +#define SMMU_STRTAB_BASE_OFFSET 0x80 +#define STRTAB_BASE_RA (1UL << 62) +BITFIELD_DECL(uint64_t, STRTAB_BASE_ADDR, 51, 6) + +#define SMMU_STRTAB_BASE_CFG_OFFSET 0x88 +BITFIELD_DECL(uint32_t, STRTAB_BASE_CFG_FMT, 17, 16) +#define STRTAB_BASE_CFG_FMT_LINEAR 0 +#define STRTAB_BASE_CFG_FMT_2LVL 1 +BITFIELD_DECL(uint32_t, STRTAB_BASE_CFG_SPLIT, 10, 6) +BITFIELD_DECL(uint32_t, STRTAB_BASE_CFG_LOG2SIZE, 5, 0) + +#define SMMU_CMDQ_BASE_OFFSET 0x90 +#define SMMU_CMDQ_PROD_OFFSET 0x98 +#define SMMU_CMDQ_CONS_OFFSET 0x9c + +#define SMMU_SH_NSH 0 +#define SMMU_SH_OSH 2 +#define SMMU_SH_ISH 3 +#define SMMU_MEMATTR_DEVICE_nGnRE 0x1 +#define SMMU_MEMATTR_OIWB 0xf + +#define QUEUE_BASE_RWA (1UL << 62) +BITFIELD_DECL(uint64_t, QUEUE_BASE_ADDR, 51, 5) +BITFIELD_DECL(uint64_t, QUEUE_BASE_LOG2SIZE, 4, 0) + +#define STRTAB_L1_SZ_SHIFT 20 +#define STRTAB_SPLIT 8 + +#define STRTAB_L1_DESC_DWORDS 1 +#define STRTAB_L1_DESC_SIZE 8 +BITFIELD_DECL(uint64_t, STRTAB_L1_DESC_SPAN, 4, 0) +BITFIELD_DECL(uint64_t, STRTAB_L1_DESC_L2PTR, 51, 6) + +#define STRTAB_STE_DWORDS 8 +#define STRTAB_STE_0_V (1UL << 0) +BITFIELD_DECL(uint64_t, STRTAB_STE_0_CONFIG, 3, 1) +#define STRTAB_STE_0_CONFIG_ABORT 0 +#define STRTAB_STE_0_CONFIG_BYPASS 4 +#define STRTAB_STE_0_CONFIG_S1_TRANS 5 +#define STRTAB_STE_0_CONFIG_S2_TRANS 6 + +BITFIELD_DECL(uint64_t, STRTAB_STE_0_S1FMT, 5, 4) +#define STRTAB_STE_0_S1FMT_LINEAR 0 +#define STRTAB_STE_0_S1FMT_64K_L2 2 +BITFIELD_DECL(uint64_t, STRTAB_STE_0_S1CONTEXTPTR, 51, 6) +BITFIELD_DECL(uint64_t, STRTAB_STE_0_S1CDMAX, 63, 59) + +#define STRTAB_STE_1_S1DSS_SSID0 0x2 +#define STRTAB_STE_1_S1C_CACHE_NC 0UL +#define STRTAB_STE_1_S1C_CACHE_WBRA 1UL +BITFIELD_DECL(uint64_t, STRTAB_STE_1_S1DSS, 1, 0) +BITFIELD_DECL(uint64_t, STRTAB_STE_1_S1CIR, 3, 2) +BITFIELD_DECL(uint64_t, STRTAB_STE_1_S1COR, 5, 4) +BITFIELD_DECL(uint64_t, STRTAB_STE_1_S1CSH, 7, 6) +BITFIELD_DECL(uint64_t, STRTAB_STE_1_STRW, 31, 30) +#define STRTAB_STE_1_STRW_NSEL1 0UL +#define STRTAB_STE_1_STRW_EL2 2UL +BITFIELD_DECL(uint64_t, STRTAB_STE_1_SHCFG, 45, 44) +#define STRTAB_STE_1_SHCFG_INCOMING 1UL + +BITFIELD_DECL(uint64_t, STRTAB_STE_2_S2VMID, 15, 0) +BITFIELD_DECL(uint64_t, STRTAB_STE_2_VTCR, 50, 32) +BITFIELD_DECL(uint64_t, STRTAB_STE_2_VTCR_S2T0SZ, 5, 0) +BITFIELD_DECL(uint64_t, STRTAB_STE_2_VTCR_S2SL0, 7, 6) +BITFIELD_DECL(uint64_t, STRTAB_STE_2_VTCR_S2IR0, 9, 8) +BITFIELD_DECL(uint64_t, STRTAB_STE_2_VTCR_S2OR0, 11, 10) +BITFIELD_DECL(uint64_t, STRTAB_STE_2_VTCR_S2SH0, 13, 12) +BITFIELD_DECL(uint64_t, STRTAB_STE_2_VTCR_S2TG, 15, 14) +BITFIELD_DECL(uint64_t, STRTAB_STE_2_VTCR_S2PS, 18, 16) + +#define STRTAB_STE_2_S2AA64 (1UL << 51) +#define STRTAB_STE_2_S2PTW (1UL << 54) +#define STRTAB_STE_2_S2R (1UL << 58) + +BITFIELD_DECL(uint64_t, STRTAB_STE_3_S2TTB, 51, 4) + +#define CMDQ_DWORDS_PER_ENT 2 +BITFIELD_DECL(uint64_t, CMDQ_0_OP, 7, 0) +BITFIELD_DECL(uint64_t, CMDQ_CFGI_1_RANGE, 4, 0) +#define CMDQ_CFGI_1_ALL_STES 31 + +#define SMMU_CMDQ_POLL_TIMEOUT 0x100000 + +#define CDTAB_SPLIT 10 +#define CDTAB_L2_ENTRY_COUNT (1 << CDTAB_SPLIT) + +#define CDTAB_L1_DESC_DWORDS 1 +#define CDTAB_L1_DESC_V (1UL << 0) +BITFIELD_DECL(uint64_t, CDTAB_L1_DESC_L2PTR, 51, 12) + +#define CDTAB_CD_DWORDS 8 +BITFIELD_DECL(uint64_t, CDTAB_CD_0_TCR_T0SZ, 5, 0) +BITFIELD_DECL(uint64_t, CDTAB_CD_0_TCR_TG0, 7, 6) +BITFIELD_DECL(uint64_t, CDTAB_CD_0_TCR_IRGN0, 9, 8) +BITFIELD_DECL(uint64_t, CDTAB_CD_0_TCR_ORGN0, 11, 10) +BITFIELD_DECL(uint64_t, CDTAB_CD_0_TCR_SH0, 13, 12) +#define CDTAB_CD_0_TCR_EPD0 (1ULL << 14) +#define CDTAB_CD_0_TCR_EPD1 (1ULL << 30) + +#define CDTAB_CD_0_ENDI (1UL << 15) +#define CDTAB_CD_0_V (1UL << 31) + +BITFIELD_DECL(uint64_t, CDTAB_CD_0_TCR_IPS, 34, 32) +#define CDTAB_CD_0_AA64 (1UL << 41) +#define CDTAB_CD_0_R (1UL << 45) +#define CDTAB_CD_0_A (1UL << 46) +#define CDTAB_CD_0_ASET (1UL << 47) +BITFIELD_DECL(uint64_t, CDTAB_CD_0_ASID, 63, 48) + +BITFIELD_DECL(uint64_t, CDTAB_CD_1_TTB0, 51, 4) + +#endif /*__SMMU_REG_H__ */ \ No newline at end of file diff --git a/val/sys_arch_src/smmu_v3/smmu_v3.c b/val/sys_arch_src/smmu_v3/smmu_v3.c new file mode 100644 index 00000000..736737cf --- /dev/null +++ b/val/sys_arch_src/smmu_v3/smmu_v3.c @@ -0,0 +1,1068 @@ +/* + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include "smmu_v3.h" + +smmu_dev_t *g_smmu; +uint32_t g_num_smmus = 0; + +struct smmu_master_node { + smmu_master_t *master; + struct smmu_master_node *next; +}; + +struct smmu_master_node *g_smmu_master_list_head = NULL; + +static uint64_t align_to_size(uint64_t addr, uint64_t size) +{ + return ((size - (addr & (size-1)) + addr) & ~(size-1)); +} + +static uint32_t smmu_cmdq_inc_prod(smmu_queue_t *q) +{ + return (q->prod + 1) & ((0x1ul << (q->log2nent + 1)) - 1); +} + +static uint32_t smmu_queue_full(smmu_queue_t *q) +{ + uint32_t index_mask = ((0x1ul << q->log2nent) - 1); + uint32_t wrap_mask = (0x1ul << q->log2nent); + return ((q->prod & index_mask) == (q->cons & index_mask)) && + ((q->prod & wrap_mask) != (q->cons & wrap_mask)); +} + +static uint32_t smmu_queue_empty(smmu_queue_t *q) +{ + uint32_t index_mask = ((0x1ul << q->log2nent) - 1); + uint32_t wrap_mask = (0x1ul << q->log2nent); + return ((q->prod & index_mask) == (q->cons & index_mask)) && + ((q->prod & wrap_mask) == (q->cons & wrap_mask)); +} + +static int smmu_cmdq_build_cmd(uint64_t *cmd, uint8_t opcode) +{ + val_memory_set(cmd, CMDQ_DWORDS_PER_ENT << 3, 0); + cmd[0] |= BITFIELD_SET(CMDQ_0_OP, opcode); + + switch (opcode) { + case CMDQ_OP_TLBI_EL2_ALL: + case CMDQ_OP_TLBI_NSNH_ALL: + case CMDQ_OP_CMD_SYNC: + break; + case CMDQ_OP_CFGI_ALL: + cmd[1] |= BITFIELD_SET(CMDQ_CFGI_1_RANGE, CMDQ_CFGI_1_ALL_STES); + break; + default: + val_print(AVS_PRINT_ERR, "\n Unsupported SMMU command 0x%x ", opcode); + return -1; + } + + return 0; +} + +static int smmu_cmdq_write_cmd(smmu_dev_t *smmu, uint64_t *cmd) +{ + uint32_t timeout = SMMU_CMDQ_POLL_TIMEOUT; + int ret = 0, i; + uint64_t *cmd_dst; + smmu_cmd_queue_t *cmdq = &smmu->cmdq; + smmu_queue_t + queue = + { + .log2nent = cmdq->queue.log2nent, + }; + + while (smmu_queue_full(&cmdq->queue) && timeout) { + timeout--; + } + + if (!timeout) { + val_print(AVS_PRINT_ERR, "\n SMMU CMD queue is full ", 0); + return -1; + } + + queue.prod = val_mmio_read((uint64_t)cmdq->prod_reg); + cmd_dst = (uint64_t *)(cmdq->base + ((queue.prod & ((0x1ull << queue.log2nent) - 1)) * (cmdq->entry_size))); + for (i = 0; i < CMDQ_DWORDS_PER_ENT; ++i) + cmd_dst[i] = cmd[i]; + queue.prod = smmu_cmdq_inc_prod(&queue); + val_mmio_write((uint64_t)cmdq->prod_reg, queue.prod); + + return ret; +} + +static int smmu_cmdq_issue_cmd(smmu_dev_t *smmu, + uint8_t opcode) +{ + uint64_t cmd[CMDQ_DWORDS_PER_ENT]; + + if (smmu_cmdq_build_cmd(cmd, opcode)) { + return -1; + } + + return smmu_cmdq_write_cmd(smmu, cmd); +} + +static void smmu_cmdq_poll_until_consumed(smmu_dev_t *smmu) +{ + uint32_t timeout = SMMU_CMDQ_POLL_TIMEOUT; + smmu_cmd_queue_t *cmdq = &smmu->cmdq; + smmu_queue_t queue = { + .log2nent = smmu->cmdq.queue.log2nent, + .prod = val_mmio_read((uint64_t)smmu->cmdq.prod_reg), + .cons = val_mmio_read((uint64_t)smmu->cmdq.cons_reg) + }; + + while (timeout > 0) { + if (smmu_queue_empty(&queue)) + break; + queue.cons = val_mmio_read((uint64_t)cmdq->cons_reg); + } + + if (!timeout) { + val_print(AVS_PRINT_ERR, "\n CMDQ poll timeout at 0x%08x", queue.prod); + val_print(AVS_PRINT_ERR, "\n prod_reg = 0x%08x,", val_mmio_read((uint64_t)smmu->cmdq.prod_reg)); + val_print(AVS_PRINT_ERR, "\n cons_reg = 0x%08x", val_mmio_read((uint64_t)smmu->cmdq.cons_reg)); + val_print(AVS_PRINT_ERR, "\n gerror = 0x%08x ", val_mmio_read(smmu->base + SMMU_GERROR_OFFSET)); + } +} + +static void smmu_strtab_write_ste(smmu_master_t *master, uint64_t *ste) +{ + uint64_t val = STRTAB_STE_0_V; + smmu_stage2_config_t *stage2_cfg = NULL; + smmu_stage1_config_t *stage1_cfg = NULL; + + if (master) { + switch (master->stage) { + case SMMU_STAGE_S1: + stage1_cfg = &master->stage1_config; + break; + case SMMU_STAGE_S2: + stage2_cfg = &master->stage2_config; + break; + default: + return; + } + } + else + { + val |= BITFIELD_SET(STRTAB_STE_0_CONFIG, + STRTAB_STE_0_CONFIG_ABORT); + + ste[0] = val; + ste[1] = BITFIELD_SET(STRTAB_STE_1_SHCFG, + STRTAB_STE_1_SHCFG_INCOMING); + ste[2] = 0; + return; + } + + if (stage2_cfg) { + ste[1] |= BITFIELD_SET(STRTAB_STE_1_STRW, 0x2); + ste[2] = (BITFIELD_SET(STRTAB_STE_2_S2VMID, stage2_cfg->vmid) | + BITFIELD_SET(STRTAB_STE_2_VTCR, stage2_cfg->vtcr) | + STRTAB_STE_2_S2PTW | STRTAB_STE_2_S2AA64 | + STRTAB_STE_2_S2R); + + ste[3] = (stage2_cfg->vttbr & STRTAB_STE_3_S2TTB_MASK); + + val |= BITFIELD_SET(STRTAB_STE_0_CONFIG, STRTAB_STE_0_CONFIG_S2_TRANS); + } + + if (stage1_cfg) { + ste[1] = BITFIELD_SET(STRTAB_STE_1_S1DSS, STRTAB_STE_1_S1DSS_SSID0) | + BITFIELD_SET(STRTAB_STE_1_S1CIR, STRTAB_STE_1_S1C_CACHE_WBRA) | + BITFIELD_SET(STRTAB_STE_1_S1COR, STRTAB_STE_1_S1C_CACHE_WBRA) | + BITFIELD_SET(STRTAB_STE_1_S1CSH, SMMU_SH_ISH); + + val |= (stage1_cfg->cdcfg.cdtab_phys & STRTAB_STE_0_S1CONTEXTPTR_MASK) | + BITFIELD_SET(STRTAB_STE_0_CONFIG, STRTAB_STE_0_CONFIG_S1_TRANS) | + BITFIELD_SET(STRTAB_STE_0_S1CDMAX, stage1_cfg->s1cdmax) | + BITFIELD_SET(STRTAB_STE_0_S1FMT, stage1_cfg->s1fmt); + } + + ste[0] = val; +} + +static uint32_t smmu_strtab_init_linear(smmu_dev_t *smmu) +{ + uint64_t *ste; + uint32_t size, i; + smmu_strtab_config_t *cfg = &smmu->strtab_cfg; + + size = (1 << smmu->sid_bits) * (STRTAB_STE_DWORDS << 3); + cfg->strtab_ptr = val_memory_alloc(2*size); + if (!cfg->strtab_ptr) { + val_print(AVS_PRINT_ERR, "\n Failed to allocate linear stream table. ", 0); + return 0; + } + val_memory_set(cfg->strtab_ptr, 2*size, 0); + + cfg->strtab_phys = align_to_size((uint64_t)val_memory_virt_to_phys(cfg->strtab_ptr), size); + cfg->strtab64 = (uint64_t*)align_to_size((uint64_t)cfg->strtab_ptr, size); + cfg->l1_ent_count = 1 << smmu->sid_bits; + cfg->strtab_base_cfg = BITFIELD_SET(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_LINEAR) | + BITFIELD_SET(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); + + for (ste = cfg->strtab64, i = 0; i < cfg->l1_ent_count; ++i, ste += STRTAB_STE_DWORDS) + smmu_strtab_write_ste(NULL, ste); + return 1; +} + +static uint32_t smmu_cmd_queue_init(smmu_dev_t *smmu) +{ + smmu_cmd_queue_t *cmdq = &smmu->cmdq; + uint64_t cmdq_size = ((1 << cmdq->queue.log2nent) * CMDQ_DWORDS_PER_ENT) << 3; + + cmdq_size = (cmdq_size < 32)?32:cmdq_size; + cmdq->base_ptr = val_memory_alloc (2 * cmdq_size); + if (!cmdq->base_ptr) { + val_print(AVS_PRINT_ERR, "\n Failed to allocate queue struct. ", 0); + return 0; + } + val_memory_set(cmdq->base_ptr, 2*cmdq_size, 0); + + cmdq->base_phys = align_to_size((uint64_t)val_memory_virt_to_phys(cmdq->base_ptr), cmdq_size); + cmdq->base = (uint8_t*)align_to_size((uint64_t)cmdq->base_ptr, cmdq_size); + + cmdq->prod_reg = (uint32_t*)(smmu->base + SMMU_CMDQ_PROD_OFFSET); + cmdq->cons_reg = (uint32_t*)(smmu->base + SMMU_CMDQ_CONS_OFFSET); + cmdq->entry_size = CMDQ_DWORDS_PER_ENT << 3; + + cmdq->queue_base = QUEUE_BASE_RWA | + (cmdq->base_phys & QUEUE_BASE_ADDR_MASK) | + BITFIELD_SET(QUEUE_BASE_LOG2SIZE, cmdq->queue.log2nent); + + cmdq->queue.prod = cmdq->queue.cons = 0; + return 1; +} + +static void smmu_free_strtab(smmu_dev_t *smmu) +{ + uint32_t i; + + smmu_strtab_config_t *cfg = &smmu->strtab_cfg; + if (cfg->strtab_ptr == NULL) + return; + if (smmu->supported.st_level_2lvl && + cfg->l1_desc != NULL) + { + for (i = 0; i < cfg->l1_ent_count; ++i) + { + if (cfg->l1_desc[i].l2ptr != NULL) + val_memory_free(cfg->l1_desc[i].l2ptr); + } + val_memory_free(cfg->l1_desc); + } + val_memory_free(cfg->strtab_ptr); +} + +/* Stream table manipulation functions */ +static void +smmu_strtab_write_level1_desc(uint64_t *dst, smmu_strtab_l1_desc_t *desc) +{ + uint64_t val = 0; + + val |= BITFIELD_SET(STRTAB_L1_DESC_SPAN, desc->span); + val |= desc->l2desc_phys & STRTAB_L1_DESC_L2PTR_MASK; + *dst = val; +} + +static int smmu_strtab_init_level2(smmu_dev_t *smmu, uint32_t sid) +{ + uint64_t size, *ste; + void *strtab; + int i; + smmu_strtab_config_t *cfg = &smmu->strtab_cfg; + smmu_strtab_l1_desc_t *desc = &cfg->l1_desc[sid >> STRTAB_SPLIT]; + + if (desc->l2ptr) + return 1; + + size = (1 << STRTAB_SPLIT) * STRTAB_STE_DWORDS * BYTES_PER_DWORD; + strtab = &cfg->strtab64[(sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS]; + + desc->span = STRTAB_SPLIT + 1; + desc->l2ptr = val_memory_alloc(size*2); + if (!desc->l2ptr) { + val_print(AVS_PRINT_ERR, "\n failed to allocate l2 stream table for SID %u ", sid); + return 0; + } + desc->l2desc_phys = align_to_size((uint64_t)val_memory_virt_to_phys(desc->l2ptr), size); + desc->l2desc64 = (uint64_t*)align_to_size((uint64_t)desc->l2ptr, size); + + val_memory_set(desc->l2desc64, size, 0); + + for (ste = desc->l2desc64, i = 0; i < (1 << STRTAB_SPLIT); ++i, ste += STRTAB_STE_DWORDS) + smmu_strtab_write_ste(NULL, ste); + smmu_strtab_write_level1_desc(strtab, desc); + return 1; +} + +static int smmu_strtab_init_level1(smmu_dev_t *smmu) +{ + int i; + void *strtab; + smmu_strtab_config_t *cfg = &smmu->strtab_cfg; + uint64_t l1_desc_arr_size = sizeof(*cfg->l1_desc) * cfg->l1_ent_count; + + cfg->l1_desc = val_memory_alloc(l1_desc_arr_size); + if (!cfg->l1_desc) { + val_print(AVS_PRINT_ERR, "\n failed to allocate l1 stream table desc ", 0); + return 0; + } + val_memory_set(cfg->l1_desc, l1_desc_arr_size, 0); + + for (strtab = smmu->strtab_cfg.strtab64, i = 0; + i < cfg->l1_ent_count; + strtab += STRTAB_L1_DESC_SIZE, ++i) + smmu_strtab_write_level1_desc(strtab, &cfg->l1_desc[i]); + return 1; +} + +static int smmu_strtab_init_2level(smmu_dev_t *smmu) +{ + uint32_t log2size, l1_tbl_size; + smmu_strtab_config_t *cfg = &smmu->strtab_cfg; + int ret; + + log2size = smmu->sid_bits - STRTAB_SPLIT; + cfg->l1_ent_count = 1 << log2size; + + log2size += STRTAB_SPLIT; + + l1_tbl_size = cfg->l1_ent_count * STRTAB_L1_DESC_SIZE; + cfg->strtab_ptr = val_memory_alloc(2 * l1_tbl_size); + if (!cfg->strtab_ptr) { + val_print(AVS_PRINT_ERR, "\n failed to allocate l1 stream table ", 0); + return 0; + } + + cfg->strtab_phys = align_to_size((uint64_t)val_memory_virt_to_phys(cfg->strtab_ptr), l1_tbl_size); + cfg->strtab64 = (uint64_t*)align_to_size((uint64_t)cfg->strtab_ptr, l1_tbl_size); + cfg->strtab_base_cfg = BITFIELD_SET(STRTAB_BASE_CFG_FMT, STRTAB_BASE_CFG_FMT_2LVL) | + BITFIELD_SET(STRTAB_BASE_CFG_LOG2SIZE, log2size) | + BITFIELD_SET(STRTAB_BASE_CFG_SPLIT, STRTAB_SPLIT); + + ret = smmu_strtab_init_level1(smmu); + if (!ret) { + val_memory_free(cfg->strtab_ptr); + return 0; + } + return 1; +} + +static uint32_t smmu_strtab_init(smmu_dev_t *smmu) +{ + uint64_t data; + int ret; + + if (smmu->supported.st_level_2lvl) + ret = smmu_strtab_init_2level(smmu); + else + ret = smmu_strtab_init_linear(smmu); + + if (!ret) { + val_print(AVS_PRINT_ERR, "\n Stream table init failed ", 0); + return ret; + } + + /* Set the strtab base address */ + data = smmu->strtab_cfg.strtab_phys & STRTAB_BASE_ADDR_MASK; + data |= STRTAB_BASE_RA; + smmu->strtab_cfg.strtab_base = data; + + return 1; +} + +static int smmu_reg_write_sync(smmu_dev_t *smmu, uint32_t val, + unsigned int reg_off, unsigned int ack_off) +{ + uint64_t timeout = 0x1000000; + uint32_t reg; + + val_mmio_write(smmu->base + reg_off, val); + + while (timeout--) { + reg = val_mmio_read(smmu->base + ack_off); + if (reg == val) { + return 0; + } + } + + return 1; +} + +static int smmu_dev_disable(smmu_dev_t *smmu) +{ + int ret; + + ret = smmu_reg_write_sync(smmu, 0, SMMU_CR0_OFFSET, SMMU_CR0ACK_OFFSET); + if (ret) + val_print(AVS_PRINT_ERR, "\n failed to clear cr0 ", 0); + + return ret; +} + +static void smmu_tlbi_cfgi(smmu_dev_t *smmu) +{ + /* Invalidate any cached configuration */ + smmu_cmdq_issue_cmd(smmu, CMDQ_OP_CFGI_ALL); + if (smmu->supported.hyp) { + smmu_cmdq_issue_cmd(smmu, CMDQ_OP_TLBI_EL2_ALL); + } + smmu_cmdq_issue_cmd(smmu, CMDQ_OP_TLBI_NSNH_ALL); + smmu_cmdq_issue_cmd(smmu, CMDQ_OP_CMD_SYNC); + + smmu_cmdq_poll_until_consumed(smmu); +} + +static int smmu_reset(smmu_dev_t *smmu) +{ + int ret; + uint32_t data; + uint32_t en; + + ret = smmu_reg_write_sync(smmu, 0, SMMU_CR0_OFFSET, SMMU_CR0ACK_OFFSET); + if (ret) { + val_print(AVS_PRINT_ERR, "\n failed to clear SMMU_CR0 ", 0); + return ret; + } + + data = BITFIELD_SET(CR1_TABLE_SH, SMMU_SH_ISH) | BITFIELD_SET(CR1_QUEUE_SH, SMMU_SH_ISH) | + BITFIELD_SET(CR1_TABLE_IC, CR1_CACHE_WB) | BITFIELD_SET(CR1_QUEUE_IC, CR1_CACHE_WB) | + BITFIELD_SET(CR1_TABLE_OC, CR1_CACHE_WB) | BITFIELD_SET(CR1_QUEUE_OC, CR1_CACHE_WB); + val_mmio_write(smmu->base + SMMU_CR1_OFFSET, data); + + val_mmio_write(smmu->base + SMMU_CR2_OFFSET, 0); + + val_mmio_write64(smmu->base + SMMU_STRTAB_BASE_OFFSET, smmu->strtab_cfg.strtab_base); + val_mmio_write(smmu->base + SMMU_STRTAB_BASE_CFG_OFFSET, + smmu->strtab_cfg.strtab_base_cfg); + + val_mmio_write64(smmu->base + SMMU_CMDQ_BASE_OFFSET, smmu->cmdq.queue_base); + val_mmio_write(smmu->base + SMMU_CMDQ_PROD_OFFSET, smmu->cmdq.queue.prod); + val_mmio_write(smmu->base + SMMU_CMDQ_CONS_OFFSET, smmu->cmdq.queue.cons); + + en = CR0_CMDQEN; + ret = smmu_reg_write_sync(smmu, en, SMMU_CR0_OFFSET, + SMMU_CR0ACK_OFFSET); + if (ret) { + val_print(AVS_PRINT_ERR, "\n failed to enable command queue ", 0); + return ret; + } + + smmu_tlbi_cfgi(smmu); + + en |= CR0_SMMUEN; + ret = smmu_reg_write_sync(smmu, en, SMMU_CR0_OFFSET, + SMMU_CR0ACK_OFFSET); + if (ret) { + val_print(AVS_PRINT_ERR, "\n failed to enable SMMU ", 0); + return ret; + } + + return 1; +} + +uint32_t smmu_set_state(uint32_t smmu_index, uint32_t en) +{ + smmu_dev_t *smmu; + uint32_t cr0_val; + int ret; + + if (smmu_index >= g_num_smmus) + { + val_print(AVS_PRINT_ERR, "\n smmu_set_state: invalid smmu index ", 0); + return 1; + } + + smmu = &g_smmu[smmu_index]; + if (smmu->base == 0) + { + val_print(AVS_PRINT_ERR, "\n smmu_set_state: smmu unsupported ", 0); + return 1; + } + + cr0_val = val_mmio_read(smmu->base + SMMU_CR0_OFFSET); + + if (en) + cr0_val |= (uint32_t)CR0_SMMUEN; + else + cr0_val &= ~((uint32_t)CR0_SMMUEN); + + ret = smmu_reg_write_sync(smmu, cr0_val, SMMU_CR0_OFFSET, + SMMU_CR0ACK_OFFSET); + if (ret) + { + val_print(AVS_PRINT_ERR, "\n smmu_set_state: failed to set SMMU state ", 0); + return ret; + } + return 0; +} + +/** + @brief Disable SMMU translations + @param smmu_index - Index of SMMU in global SMMU table. + @return status +**/ +uint32_t +val_smmu_disable(uint32_t smmu_index) +{ + return smmu_set_state(smmu_index, 0); +} + +/** + @brief Enable SMMU translations + @param smmu_index - Index of SMMU in global SMMU table. + @return status +**/ +uint32_t +val_smmu_enable(uint32_t smmu_index) +{ + return smmu_set_state(smmu_index, 1); +} + +static uint32_t smmu_probe(smmu_dev_t *smmu) +{ + uint32_t data; + data = val_mmio_read(smmu->base + SMMU_IDR0_OFFSET); + + if (BITFIELD_GET(IDR0_ST_LEVEL, data) == IDR0_ST_LEVEL_2LVL) + smmu->supported.st_level_2lvl = 1; + + if (data & IDR0_CD2L) + smmu->supported.cd2l = 1; + + if (data & IDR0_HYP) + smmu->supported.hyp = 1; + + if (data & IDR0_S1P) + smmu->supported.s1p = 1; + + if (data & IDR0_S2P) + smmu->supported.s2p = 1; + + if (!(data & (IDR0_S1P | IDR0_S2P))) { + val_print(AVS_PRINT_ERR, "\n no translation support! ", 0); + return 0; + } + + switch (BITFIELD_GET(IDR0_TTF, data)) { + case IDR0_TTF_AARCH32_64: + smmu->ias = 40; + case IDR0_TTF_AARCH64: + break; + default: + val_print(AVS_PRINT_ERR, "\n AArch64 table format not supported! ", 0); + return 0; + } + + data = val_mmio_read(smmu->base + SMMU_IDR1_OFFSET); + if (data & (IDR1_TABLES_PRESET | IDR1_QUEUES_PRESET)) { + val_print(AVS_PRINT_ERR, "\n fixed table base address not supported ", 0); + return 0; + } + + smmu->cmdq.queue.log2nent = BITFIELD_GET(IDR1_CMDQS, data); + + /* SID/SSID sizes */ + smmu->sid_bits = BITFIELD_GET(IDR1_SIDSIZE, data); + smmu->ssid_bits = BITFIELD_GET(IDR1_SSIDSIZE, data); + + val_print(AVS_PRINT_INFO, "ssid_bits = %d\n", smmu->ssid_bits); + val_print(AVS_PRINT_INFO, "sid_bits = %d\n", smmu->sid_bits); + + if (smmu->sid_bits <= STRTAB_SPLIT) + smmu->supported.st_level_2lvl = 0; + + /* IDR5 */ + data = val_mmio_read(smmu->base + SMMU_IDR5_OFFSET); + + if (BITFIELD_GET(IDR5_OAS, data) >= SMMU_OAS_MAX_IDX) { + val_print(AVS_PRINT_ERR, "\n Unknown output address size ", 0); + return 0; + } + smmu->oas = smmu_oas[BITFIELD_GET(IDR5_OAS, data)]; + smmu->ias = get_max(smmu->ias, smmu->oas); + + val_print(AVS_PRINT_INFO, "ias %d-bit ", smmu->ias); + val_print(AVS_PRINT_INFO, "oas %d-bit ", smmu->oas); + + return 1; +} + +static uint64_t *smmu_strtab_get_ste_for_sid(smmu_dev_t *smmu, uint32_t sid) +{ + smmu_strtab_config_t *cfg = &smmu->strtab_cfg; + smmu_strtab_l1_desc_t *l1_desc; + + if (!smmu->supported.st_level_2lvl) + return &cfg->strtab64[sid * STRTAB_STE_DWORDS]; + + l1_desc = &cfg->l1_desc[((sid >> STRTAB_SPLIT) * STRTAB_L1_DESC_DWORDS)]; + return &l1_desc->l2desc64[((sid & ((1 << STRTAB_SPLIT) - 1)) * STRTAB_STE_DWORDS)]; +} + +static void dump_strtab(uint64_t *ste) +{ + int i; + + for (i = 0; i < 8; i++) { + val_print(AVS_PRINT_INFO, "ste[%d] = ", i); + val_print(AVS_PRINT_INFO, "%p\n", ste[i]); + } +} + +static void dump_cdtab(uint64_t *ctx_desc) +{ + int i; + + for (i = 0; i < 8; i++) { + val_print(AVS_PRINT_INFO, "ctx_desc[%d] = ", i); + val_print(AVS_PRINT_INFO, "%llx\n", ctx_desc[i]); + } +} + +static void smmu_cdtab_write_l1_desc(uint64_t *dst, + smmu_cdtab_l1_ctx_desc_t *l1_desc) +{ + uint64_t val = (l1_desc->l2desc_phys & CDTAB_L1_DESC_L2PTR_MASK) | + CDTAB_L1_DESC_V; + + *dst = val; +} + +static int smmu_cdtab_alloc_leaf_table(smmu_cdtab_l1_ctx_desc_t *l1_desc) +{ + uint64_t size = CDTAB_L2_ENTRY_COUNT * (CDTAB_CD_DWORDS << 3); + + l1_desc->l2ptr = val_memory_alloc(size*2); + if (!l1_desc->l2ptr) { + val_print(AVS_PRINT_ERR, "\n failed to allocate context descriptor table ", 0); + return 1; + } + l1_desc->l2desc_phys = align_to_size((uint64_t)val_memory_virt_to_phys(l1_desc->l2ptr), size); + l1_desc->l2desc64 = (uint64_t*)align_to_size((uint64_t)l1_desc->l2ptr, size); + return 0; +} + +static uint64_t *smmu_cdtab_get_ctx_desc(smmu_master_t *master) +{ + smmu_cdtab_config_t *cdcfg = &master->stage1_config.cdcfg; + smmu_cdtab_l1_ctx_desc_t *l1_desc; + uint64_t *l1ptr; + uint32_t idx; + + if (master->stage1_config.s1fmt == STRTAB_STE_0_S1FMT_LINEAR) + return cdcfg->cdtab64 + master->ssid * CDTAB_CD_DWORDS; + + idx = master->ssid >> CDTAB_SPLIT; + l1_desc = &cdcfg->l1_desc[idx]; + if (!l1_desc->l2ptr) { + if (smmu_cdtab_alloc_leaf_table(l1_desc)) + return NULL; + + l1ptr = cdcfg->cdtab64 + idx * CDTAB_L1_DESC_DWORDS; + smmu_cdtab_write_l1_desc(l1ptr, l1_desc); + } + idx = master->ssid & (CDTAB_L2_ENTRY_COUNT - 1); + return l1_desc->l2desc64 + idx * CDTAB_CD_DWORDS; +} + +static int smmu_cdtab_write_ctx_desc(smmu_master_t *master, + int ssid, smmu_cdtab_ctx_desc_t *cd) +{ + uint64_t val; + uint64_t *cdptr; + + if (ssid >= (1 << master->stage1_config.s1cdmax)) + { + val_print(AVS_PRINT_ERR, "\n smmu_cdtab_write_ctx_desc: ssid out of range ", 0); + return 0; + } + + cdptr = smmu_cdtab_get_ctx_desc(master); + if (!cdptr) + { + val_print(AVS_PRINT_ERR, "\n smmu_cdtab_write_ctx_desc: cdptr is NULL ", 0); + return 0; + } + + cdptr[1] = cd->ttbr & CDTAB_CD_1_TTB0_MASK; + cdptr[2] = 0; + cdptr[3] = cd->mair; + + val = cd->tcr | + CDTAB_CD_0_R | CDTAB_CD_0_A | CDTAB_CD_0_ASET | + CDTAB_CD_0_AA64 | + BITFIELD_SET(CDTAB_CD_0_ASID, cd->asid) | + CDTAB_CD_0_V; + + cdptr[0] = val; + dump_cdtab(cdptr); + + return 1; +} + +static void smmu_cdtab_free(smmu_master_t *master) +{ + uint64_t max_contexts; + uint32_t i; + uint32_t num_l1_ents; + smmu_stage1_config_t *cfg = &master->stage1_config; + smmu_cdtab_config_t *cdcfg = &cfg->cdcfg; + max_contexts = 1 << cfg->s1cdmax; + + if (master->smmu->supported.cd2l && + max_contexts > CDTAB_L2_ENTRY_COUNT) + { + num_l1_ents = (max_contexts + CDTAB_L2_ENTRY_COUNT - 1)/CDTAB_L2_ENTRY_COUNT; + for (i = 0; i < num_l1_ents; i++) + { + if (cdcfg->l1_desc[i].l2ptr != NULL) + val_memory_free(cdcfg->l1_desc[i].l2ptr); + + } + val_memory_free(cdcfg->l1_desc); + } + val_memory_free(cdcfg->cdtab_ptr); + cdcfg->cdtab_ptr = NULL; +} + +static int smmu_cdtab_alloc(smmu_master_t *master) +{ + uint64_t l1_tbl_size; + uint64_t cdmax; + smmu_stage1_config_t *cfg = &master->stage1_config; + smmu_cdtab_config_t *cdcfg = &cfg->cdcfg; + + cdmax = 1 << cfg->s1cdmax; + + if (master->smmu->supported.cd2l && cdmax > CDTAB_L2_ENTRY_COUNT) + { + cfg->s1fmt = STRTAB_STE_0_S1FMT_64K_L2; + cdcfg->l1_ent_count = (cdmax + CDTAB_L2_ENTRY_COUNT - 1)/CDTAB_L2_ENTRY_COUNT; + + cdcfg->l1_desc = val_memory_alloc(cdcfg->l1_ent_count * sizeof(*cdcfg->l1_desc)); + if (!cdcfg->l1_desc) + return 0; + + val_memory_set(cdcfg->l1_desc, cdcfg->l1_ent_count * sizeof(*cdcfg->l1_desc), 0); + l1_tbl_size = cdcfg->l1_ent_count * (CDTAB_L1_DESC_DWORDS << 3); + } else { + cfg->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; + cdcfg->l1_ent_count = cdmax; + l1_tbl_size = cdmax * (CDTAB_CD_DWORDS << 3); + } + + cdcfg->cdtab_ptr = val_memory_alloc(l1_tbl_size * 2); + if (!cdcfg->cdtab_ptr) { + val_print(AVS_PRINT_ERR, "\n smmu_cdtab_alloc: alloc failed ", 0); + return 0; + } + + cdcfg->cdtab_phys = align_to_size((uint64_t)val_memory_virt_to_phys(cdcfg->cdtab_ptr), l1_tbl_size); + cdcfg->cdtab64 = (uint64_t*)align_to_size((uint64_t)cdcfg->cdtab_ptr, l1_tbl_size); + val_memory_set(cdcfg->cdtab64, l1_tbl_size, 0); + + return 1; +} + +smmu_master_t *smmu_master_at(uint32_t sid) +{ + struct smmu_master_node *node = g_smmu_master_list_head; + + while (node != NULL) + { + if (node->master->sid == sid) + return node->master; + node = node->next; + } + node = val_memory_alloc(sizeof(struct smmu_master_node)); + if (node == NULL) + return NULL; + node->master = val_memory_alloc(sizeof(smmu_master_t)); + if (node->master == NULL) + { + val_memory_free(node); + return NULL; + } + val_memory_set(node->master, sizeof(smmu_master_t), 0); + node->next = g_smmu_master_list_head; + g_smmu_master_list_head = node; + + return node->master; +} + +/** + @brief - 1. Determine if stage 1 or stage 2 translation is needed. + 2. Populate stage1 or stage2 configuration data structures. Create and populate + context desciptor tables as well in case of stage 1 transalation. + 3. Get pointer to stream table entry corresponding to master stream id + 4. Populate the stream table entry, with stage1/2 configuration. + 5. Invalidate all SMMU config and tlb entries, so that stream table is accessed, + at the next memory access from a master. + @param master_attr - structured data about the master (like streamid, smmu index). + @param pgt_desc - page table base and translation attributes + @return status +**/ +uint32_t val_smmu_map(smmu_master_attributes_t master_attr, pgt_descriptor_t pgt_desc) +{ + smmu_master_t *master; + smmu_dev_t *smmu; + uint64_t *ste; + + if (g_smmu == NULL) + return 1; + + if (master_attr.smmu_index >= g_num_smmus) + { + val_print(AVS_PRINT_ERR, "\n val_smmu_map: invalid smmu index ", 0); + return 1; + } + + smmu = &g_smmu[master_attr.smmu_index]; + if (smmu->base == 0) + { + val_print(AVS_PRINT_ERR, "\n val_smmu_map: smmu unsupported ", 0); + return 1; + } + + if ((master = smmu_master_at(master_attr.streamid)) == NULL) + return 1; + + if (master->smmu == NULL) + { + master->smmu = smmu; + master->sid = master_attr.streamid; + master->ssid_bits = master_attr.ssid_bits; + } + + /* TODO: Support for stage 1 and stage 2 translations in one stream table entry(STE) + * This implementation only supports either stage 1 or stage 2 in one STE + */ + if (master_attr.stage2) + { + if (!smmu->supported.s2p) + return 1; + master->stage = SMMU_STAGE_S2; + } + else + { + if (!smmu->supported.s1p) + return 1; + master->stage = SMMU_STAGE_S1; + master->ssid = master_attr.substreamid; + } + + if (master_attr.streamid >= (0x1ul << smmu->sid_bits)) + { + val_print(AVS_PRINT_ERR, "\n val_smmu_map: sid %d out of range ", master_attr.streamid); + return 1; + } + + if (smmu->supported.st_level_2lvl) { + if(!smmu_strtab_init_level2(smmu, master->sid)) + { + val_print(AVS_PRINT_ERR, "\n val_smmu_map: l2 stream table init failed ", 0); + return 1; + } + } + + if (master->stage == SMMU_STAGE_S2) + { + smmu_stage2_config_t *cfg = &master->stage2_config; + cfg->vmid = 0; + cfg->vttbr = pgt_desc.pgt_base; + cfg->vtcr = BITFIELD_SET(STRTAB_STE_2_VTCR_S2T0SZ, pgt_desc.tcr.tsz) | + BITFIELD_SET(STRTAB_STE_2_VTCR_S2SL0, pgt_desc.tcr.sl) | + BITFIELD_SET(STRTAB_STE_2_VTCR_S2IR0, pgt_desc.tcr.irgn) | + BITFIELD_SET(STRTAB_STE_2_VTCR_S2OR0, pgt_desc.tcr.orgn) | + BITFIELD_SET(STRTAB_STE_2_VTCR_S2SH0, pgt_desc.tcr.sh) | + BITFIELD_SET(STRTAB_STE_2_VTCR_S2TG, pgt_desc.tcr.tg) | + BITFIELD_SET(STRTAB_STE_2_VTCR_S2PS, pgt_desc.tcr.ps); + } else + { + smmu_stage1_config_t *cfg = &master->stage1_config; + + cfg->s1cdmax = master->ssid_bits; + if (cfg->cdcfg.cdtab_ptr == NULL) { + if (!smmu_cdtab_alloc(master)) + return 1; + } + + cfg->cd.asid = 0; + cfg->cd.ttbr = pgt_desc.pgt_base; + cfg->cd.tcr = BITFIELD_SET(CDTAB_CD_0_TCR_T0SZ, pgt_desc.tcr.tsz) | + BITFIELD_SET(CDTAB_CD_0_TCR_TG0, pgt_desc.tcr.tg) | + BITFIELD_SET(CDTAB_CD_0_TCR_IRGN0, pgt_desc.tcr.irgn) | + BITFIELD_SET(CDTAB_CD_0_TCR_ORGN0, pgt_desc.tcr.orgn) | + BITFIELD_SET(CDTAB_CD_0_TCR_SH0, pgt_desc.tcr.sh) | + BITFIELD_SET(CDTAB_CD_0_TCR_IPS, pgt_desc.tcr.ps) | + CDTAB_CD_0_TCR_EPD1 | CDTAB_CD_0_AA64; + + cfg->cd.mair = pgt_desc.mair; + + if (!smmu_cdtab_write_ctx_desc(master, master->ssid, &cfg->cd)) + return 1; + } + + ste = smmu_strtab_get_ste_for_sid(smmu, master->sid); + smmu_strtab_write_ste(master, ste); + dump_strtab(ste); + + smmu_tlbi_cfgi(smmu); + + return 0; +} + +/** + @brief Clear stream table entry, free any context descriptor tables and + page tables corresponding to given master device + @param master_attr - structured data about the master (like streamid, smmu index) + @return void +**/ +void val_smmu_unmap(smmu_master_attributes_t master_attr) +{ + smmu_master_t *master; + uint64_t *strtab; + + if ((master = smmu_master_at(master_attr.streamid)) == NULL) + return; + + if (master->smmu == NULL) + return; + + if (master_attr.streamid >= (0x1ul << master->smmu->sid_bits)) + return; + + strtab = master->smmu->strtab_cfg.strtab64 + master_attr.streamid * STRTAB_STE_DWORDS; + smmu_strtab_write_ste(NULL, strtab); + + smmu_cdtab_free(master); + smmu_tlbi_cfgi(master->smmu); + val_memory_set(master, sizeof(smmu_master_t), 0); +} + +uint32_t smmu_init(smmu_dev_t *smmu) +{ + if (smmu->base == 0) + return AVS_STATUS_ERR; + + if (!smmu_probe(smmu)) { + return AVS_STATUS_ERR; + } + + if (!smmu_cmd_queue_init(smmu)) { + return AVS_STATUS_ERR; + } + + if (!smmu_strtab_init(smmu)) { + return AVS_STATUS_ERR; + } + + if (!smmu_reset(smmu)) { + return AVS_STATUS_ERR; + } + + return 0; +} + +/** + @brief Disable all SMMUs and free all associated memory + @return void +**/ +void val_smmu_stop(void) +{ + int i; + smmu_dev_t *smmu; + + for (i = 0; i < g_num_smmus; i++) + { + smmu = &g_smmu[i]; + if (smmu->base == 0) + continue; + smmu_dev_disable(smmu); + if (smmu->cmdq.base_ptr) + val_memory_free(smmu->cmdq.base_ptr); + smmu_free_strtab(smmu); + } + val_memory_free(g_smmu); +} + +/** + @brief Scan all available SMMUs in the system and initialize all v3.x SMMUs + @return Initialzation status +**/ +uint32_t val_smmu_init(void) +{ + int i; + g_num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0); + if (g_num_smmus == 0) + return AVS_STATUS_ERR; + + g_smmu = val_memory_alloc(sizeof(smmu_dev_t) * g_num_smmus); + if (!g_smmu) + { + val_print(AVS_PRINT_ERR, "\n val_smmu_init: memory allocation failure ", 0); + return AVS_STATUS_ERR; + } + + val_memory_set(g_smmu, sizeof(smmu_dev_t) * g_num_smmus, 0); + + for (i = 0; i < g_num_smmus; ++i) { + if (val_iovirt_get_smmu_info(SMMU_CTRL_ARCH_MAJOR_REV, i) != 3) { + val_print(AVS_PRINT_ERR, "\n val_smmu_init: only SMMUv3.x supported, skipping smmu %d ", i); + continue; + } + g_smmu[i].base = val_iovirt_get_smmu_info(SMMU_CTRL_BASE, i); + if (smmu_init(&g_smmu[i])) + { + val_print(AVS_PRINT_ERR, "\n val_smmu_init: smmu %d init failed ", i); + g_smmu[i].base = 0; + return AVS_STATUS_ERR; + } + } + return 0; +} + +/** + @brief Get info about SMMU features. + @param type - ID of the info requested. + @param smmu_index - Index of SMMU in global SMMU table. + @return info value in 64-bit unsigned int. +**/ +uint64_t +val_smmu_get_info(SMMU_INFO_e type, uint32_t smmu_index) +{ + smmu_dev_t *smmu; + if (smmu_index >= g_num_smmus) + { + val_print(AVS_PRINT_ERR, "\n val_smmu_get_info: invalid smmu index(%d) ", smmu_index); + return 0; + } + smmu = &g_smmu[smmu_index]; + switch(type) + { + case SMMU_SSID_BITS: + return smmu->ssid_bits; + case SMMU_IN_ADDR_SIZE: + return smmu->ias; + case SMMU_OUT_ADDR_SIZE: + return smmu->oas; + default: + return val_iovirt_get_smmu_info(type, smmu_index); + } +} diff --git a/val/sys_arch_src/smmu_v3/smmu_v3.h b/val/sys_arch_src/smmu_v3/smmu_v3.h new file mode 100644 index 00000000..08e08b8a --- /dev/null +++ b/val/sys_arch_src/smmu_v3/smmu_v3.h @@ -0,0 +1,140 @@ +/* + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * https://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SMMU_V3_H__ +#define __SMMU_V3_H__ + +#include "../include/sbsa_avs_val.h" +#include "../include/sbsa_avs_memory.h" +#include "../include/sbsa_avs_iovirt.h" +#include "../include/sbsa_avs_pgt.h" +#include "smmu_reg.h" + +static uint64_t inline get_max(uint64_t x, uint64_t y) +{ + return x > y ? x : y; +} + +#define CMDQ_OP_CFGI_STE 0x3 +#define CMDQ_OP_CFGI_ALL 0x4 +#define CMDQ_OP_TLBI_EL2_ALL 0x20 +#define CMDQ_OP_TLBI_NSNH_ALL 0x30 +#define CMDQ_OP_CMD_SYNC 0x46 + +typedef struct { + uint32_t prod; + uint32_t cons; + uint32_t log2nent; +} smmu_queue_t; + +typedef struct { + smmu_queue_t queue; + void *base_ptr; + uint8_t *base; + uint64_t base_phys; + uint64_t queue_base; + uint64_t entry_size; + uint32_t *prod_reg; + uint32_t *cons_reg; +} smmu_cmd_queue_t; + +typedef struct { + uint8_t span; + void *l2ptr; + uint64_t *l2desc64; + uint64_t l2desc_phys; +} smmu_strtab_l1_desc_t; + +typedef struct { + uint16_t vmid; + uint64_t vttbr; + uint64_t vtcr; +} smmu_stage2_config_t; + +typedef struct { + uint16_t asid; + uint64_t ttbr; + uint64_t tcr; + uint64_t mair; +} smmu_cdtab_ctx_desc_t; + +typedef struct { + void *l2ptr; + uint64_t *l2desc64; + uint64_t l2desc_phys; +} smmu_cdtab_l1_ctx_desc_t; + +typedef struct { + void *cdtab_ptr; + uint64_t *cdtab64; + uint64_t cdtab_phys; + smmu_cdtab_l1_ctx_desc_t *l1_desc; + unsigned int l1_ent_count; +} smmu_cdtab_config_t; + +typedef struct { + smmu_cdtab_config_t cdcfg; + smmu_cdtab_ctx_desc_t cd; + uint8_t s1fmt; + uint8_t s1cdmax; +} smmu_stage1_config_t; + +typedef struct { + void *strtab_ptr; + uint64_t *strtab64; + uint64_t strtab_phys; + smmu_strtab_l1_desc_t *l1_desc; + uint32_t l1_ent_count; + uint64_t strtab_base; + uint32_t strtab_base_cfg; +} smmu_strtab_config_t; + +typedef struct { + uint64_t base; + uint64_t ias; + uint64_t oas; + uint32_t ssid_bits; + uint32_t sid_bits; + smmu_cmd_queue_t cmdq; + smmu_strtab_config_t strtab_cfg; + union { + struct { + uint32_t st_level_2lvl:1; + uint32_t cd2l:1; + uint32_t hyp:1; + uint32_t s1p:1; + uint32_t s2p:1; + }; + uint32_t bitmap; + } supported; +} smmu_dev_t; + +typedef enum { + SMMU_STAGE_S1 = 0, + SMMU_STAGE_S2, + SMMU_STAGE_BYPASS +} smmu_stage_t; + +typedef struct { +#define MAX_PAGE_TABLES_PER_MASTER 8 + smmu_dev_t *smmu; + smmu_stage_t stage; + smmu_stage1_config_t stage1_config; + smmu_stage2_config_t stage2_config; + uint32_t sid; + uint32_t ssid; + uint32_t ssid_bits; +} smmu_master_t; + +#endif /*__SMMU_V3_H__ */ From 1b4a906af45bc16ab17b54bfb5efb2d6149414dd Mon Sep 17 00:00:00 2001 From: Gowtham Siddarth Date: Wed, 16 Sep 2020 15:44:03 +0530 Subject: [PATCH 2/3] EDKII: Migration to edk2-stable202008 SBSA changes required to build ACS on the latest EDK II firmware tagged edk2-stable202008. Signed-off-by: Gowtham Siddarth --- README.md | 40 +++++++++++++++++++--------- docs/Arm_SBSA_NIST_User_Guide.md | 18 ++++++------- platform/pal_uefi/SbsaPalLib.inf | 1 - platform/pal_uefi/SbsaPalNistLib.inf | 1 - platform/pal_uefi/src/pal_acpi.c | 4 +-- test_pool/nist_sts/SbsaNistLib.inf | 1 - tools/scripts/avsbuild.sh | 10 +++---- tools/scripts/avssetup.sh | 2 +- uefi_app/SbsaAvs.inf | 1 - uefi_app/SbsaAvsNist.inf | 1 - 10 files changed, 44 insertions(+), 35 deletions(-) diff --git a/README.md b/README.md index b21e4e5e..c3957e23 100644 --- a/README.md +++ b/README.md @@ -17,8 +17,8 @@ A few tests are executed by running the SBSA ACS Linux application which in turn ## Release details - - Code Quality: REL v2.5 - - The tests are written for version 5.0 of the SBSA specification. + - Code Quality: REL v3.0 + - The tests are written for version 6.0 of the SBSA specification. - PCIe RCiEP tests for Appendix E of SBSA 6.0 specification are also included. - The compliance suite is not a substitute for design verification. - To review the SBSA ACS logs, Arm licensees can contact Arm directly through their partner managers. @@ -50,7 +50,8 @@ Prebuilt images for each release are available in the prebuilt_images folder of Before starting the ACS build, ensure that the following requirements are met. - Any mainstream Linux based OS distribution running on a x86 or aarch64 machine. -- git clone the UDK2018 branch of [EDK2 tree](https://github.com/tianocore/edk2). +- git clone the edk2-stable202008 tag of [EDK2 tree](https://github.com/tianocore/edk2). +- git clone the [EDK2 port of libc](https://github.com/tianocore/edk2-libc) SHA: 61687168fe02ac4d933a36c9145fdd242ac424d1. - Install GCC 5.3 or later toolchain for Linux from [here](https://releases.linaro.org/components/toolchain/binaries/). - Install the build prerequisite packages to build EDK2. Note: The details of the packages are beyond the scope of this document. @@ -58,27 +59,30 @@ Note: The details of the packages are beyond the scope of this document. To start the ACS build, perform the following steps: 1. cd local_edk2_path -2. git clone https://github.com/ARM-software/sbsa-acs AppPkg/Applications/sbsa-acs -3. Add the following to the [LibraryClasses.common] section in ShellPkg/ShellPkg.dsc - - Add SbsaValLib|AppPkg/Applications/sbsa-acs/val/SbsaValLib.inf - - Add SbsaPalLib|AppPkg/Applications/sbsa-acs/platform/pal_uefi/SbsaPalLib.inf -4. Add AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf in the [components] section of ShellPkg/ShellPkg.dsc +2. git clone https://github.com/tianocore/edk2-libc +3. git clone https://github.com/ARM-software/sbsa-acs ShellPkg/Application/sbsa-acs +4. Add the following to the [LibraryClasses.common] section in ShellPkg/ShellPkg.dsc + - Add SbsaValLib|ShellPkg/Application/sbsa-acs/val/SbsaValLib.inf + - Add SbsaPalLib|ShellPkg/Application/sbsa-acs/platform/pal_uefi/SbsaPalLib.inf +5. Add ShellPkg/Application/sbsa-acs/uefi_app/SbsaAvs.inf in the [components] section of ShellPkg/ShellPkg.dsc ### Linux build environment If the build environment is Linux, perform the following steps: 1. export GCC49_AARCH64_PREFIX= GCC5.3 toolchain path pointing to /bin/aarch64-linux-gnu- in case of x86 machine. For aarch64 build it should point to /usr/bin/ -2. source edksetup.sh -3. make -C BaseTools/Source/C -4. source AppPkg/Applications/sbsa-acs/tools/scripts/avsbuild.sh +2. export PACKAGES_PATH= path pointing to edk2-libc +3. source edksetup.sh +4. make -C BaseTools/Source/C +5. source ShellPkg/Application/sbsa-acs/tools/scripts/avsbuild.sh ### Windows build environment If the build environment is Windows, perform the following steps: 1. Set the toolchain path to GCC53 or above. 2. Setup the environment for AARCH64 EDK2 build. -3. Build the SBSA shell application. +3. Setup the environment for PACKAGES_PATH. +4. Build the SBSA shell application. For example, build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m - AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf + ShellPkg/Application/sbsa-acs/uefi_app/SbsaAvs.inf **Note:** To build the ACS with NIST Statistical Test Suite, see [SBSA_NIST_User_Guide](docs/Arm_SBSA_NIST_User_Guide.md) @@ -93,6 +97,16 @@ The execution of the compliance suite varies depending on the test environment. For details about the SBSA ACS UEFI Shell application, see [SBSA ACS USER Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf) +### Prerequisites +- If the system supports LPI’s (Interrupt ID > 8192) then Firmware should have support for installing handler for LPI interrupts. + - If you are using edk2, please change the ArmGic driver in the ArmPkg to have support for installing handler for LPI’s. + - Add the following in edk2/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +> - After [#define ARM_GIC_DEFAULT_PRIORITY 0x80] +> +#define ARM_GIC_MAX_NUM_INTERRUPT 16384 +> - Change this in GicV3DxeInitialize Function. +> -mGicNumInterrupts = ArmGicGetMaxNumInterrupts (mGicDistributorBase); +> +mGicNumInterrupts = ARM_GIC_MAX_NUM_INTERRUPT; + ### Post-Silicon On a system where a USB port is available and functional, perform the following steps: diff --git a/docs/Arm_SBSA_NIST_User_Guide.md b/docs/Arm_SBSA_NIST_User_Guide.md index da285eae..2fe0a7d2 100644 --- a/docs/Arm_SBSA_NIST_User_Guide.md +++ b/docs/Arm_SBSA_NIST_User_Guide.md @@ -32,20 +32,20 @@ To start the ACS build with NIST STS, perform the following steps: ``` UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf !ifdef $(ENABLE_NIST) - SbsaNistLib|AppPkg/Applications/sbsa-acs/test_pool/nist_sts/SbsaNistLib.inf - SbsaValNistLib|AppPkg/Applications/sbsa-acs/val/SbsaValNistLib.inf - SbsaPalNistLib|AppPkg/Applications/sbsa-acs/platform/pal_uefi/SbsaPalNistLib.inf + SbsaNistLib|ShellPkg/Application/sbsa-acs/test_pool/nist_sts/SbsaNistLib.inf + SbsaValNistLib|ShellPkg/Application/sbsa-acs/val/SbsaValNistLib.inf + SbsaPalNistLib|ShellPkg/Application/sbsa-acs/platform/pal_uefi/SbsaPalNistLib.inf !else - SbsaValLib|AppPkg/Applications/sbsa-acs/val/SbsaValLib.inf - SbsaPalLib|AppPkg/Applications/sbsa-acs/platform/pal_uefi/SbsaPalLib.inf + SbsaValLib|ShellPkg/Application/sbsa-acs/val/SbsaValLib.inf + SbsaPalLib|ShellPkg/Application/sbsa-acs/platform/pal_uefi/SbsaPalLib.inf !endif ``` 2. Add the following in the [components] section of ShellPkg/ShellPkg.dsc ``` !ifdef $(ENABLE_NIST) - AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvsNist.inf + ShellPkg/Application/sbsa-acs/uefi_app/SbsaAvsNist.inf !else - AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf + ShellPkg/Application/sbsa-acs/uefi_app/SbsaAvs.inf !endif ``` 3. Modify CC Flags in the [BuildOptions] section of ShellPkg/ShellPkg.dsc @@ -84,12 +84,12 @@ To start the ACS build with NIST STS, perform the following steps: To build the SBSA test suite with NIST STS, execute the following commands: ***Linux build environment*** ``` -source AppPkg/Applications/sbsa-acs/tools/scripts/avsbuild.sh NIST +source ShellPkg/Application/sbsa-acs/tools/scripts/avsbuild.sh NIST ``` ***Windows build environment*** ``` -build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf -D ENABLE_NIST +build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m ShellPkg/Application/sbsa-acs/uefi_app/SbsaAvs.inf -D ENABLE_NIST ``` **Directory structure of SBSA ACS** diff --git a/platform/pal_uefi/SbsaPalLib.inf b/platform/pal_uefi/SbsaPalLib.inf index 3d53b27e..bc539d99 100644 --- a/platform/pal_uefi/SbsaPalLib.inf +++ b/platform/pal_uefi/SbsaPalLib.inf @@ -48,7 +48,6 @@ ShellPkg/ShellPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec - EdkCompatibilityPkg/EdkCompatibilityPkg.dec [LibraryClasses] IoLib diff --git a/platform/pal_uefi/SbsaPalNistLib.inf b/platform/pal_uefi/SbsaPalNistLib.inf index 9ba9342b..d2f54bcd 100644 --- a/platform/pal_uefi/SbsaPalNistLib.inf +++ b/platform/pal_uefi/SbsaPalNistLib.inf @@ -50,7 +50,6 @@ ShellPkg/ShellPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec - EdkCompatibilityPkg/EdkCompatibilityPkg.dec [LibraryClasses] LibC diff --git a/platform/pal_uefi/src/pal_acpi.c b/platform/pal_uefi/src/pal_acpi.c index ec9764e9..f118f542 100644 --- a/platform/pal_uefi/src/pal_acpi.c +++ b/platform/pal_uefi/src/pal_acpi.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020 Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -21,7 +21,7 @@ #include #include -#include "Foundation/Efi/Guid/Acpi/Acpi.h" +#include "Include/Guid/Acpi.h" #include #include "Include/IndustryStandard/Acpi61.h" diff --git a/test_pool/nist_sts/SbsaNistLib.inf b/test_pool/nist_sts/SbsaNistLib.inf index bda9ebab..9d239565 100644 --- a/test_pool/nist_sts/SbsaNistLib.inf +++ b/test_pool/nist_sts/SbsaNistLib.inf @@ -53,7 +53,6 @@ ShellPkg/ShellPkg.dec EmbeddedPkg/EmbeddedPkg.dec MdeModulePkg/MdeModulePkg.dec - EdkCompatibilityPkg/EdkCompatibilityPkg.dec SecurityPkg/SecurityPkg.dec [LibraryClasses] diff --git a/tools/scripts/avsbuild.sh b/tools/scripts/avsbuild.sh index b789e471..520e4d5b 100644 --- a/tools/scripts/avsbuild.sh +++ b/tools/scripts/avsbuild.sh @@ -18,8 +18,8 @@ function build_with_NIST() fi fi - if [ ! -d "AppPkg/Applications/sbsa-acs/test_pool/nist_sts/sts-2.1.2/" ]; then - /usr/bin/unzip sts-2_1_2.zip -d AppPkg/Applications/sbsa-acs/test_pool/nist_sts/. + if [ ! -d "ShellPkg/Application/sbsa-acs/test_pool/nist_sts/sts-2.1.2/" ]; then + /usr/bin/unzip sts-2_1_2.zip -d ShellPkg/Application/sbsa-acs/test_pool/nist_sts/. status=$? if [ $status -ne 0 ]; then echo "unzip failed for NIST. Building sbsa without NIST" @@ -27,7 +27,7 @@ function build_with_NIST() fi fi - cd AppPkg/Applications/sbsa-acs/test_pool/nist_sts/sts-2.1.2/ + cd ShellPkg/Application/sbsa-acs/test_pool/nist_sts/sts-2.1.2/ if ! patch -R -p1 -s -f --dry-run < ../../../patches/nist_sbsa_sts.diff; then patch -p1 < ../../../patches/nist_sbsa_sts.diff status=$? @@ -38,7 +38,7 @@ function build_with_NIST() fi cd - - build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvsNist.inf -D ENABLE_NIST + build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m ShellPkg/Application/sbsa-acs/uefi_app/SbsaAvsNist.inf -D ENABLE_NIST status=$? if [ $status -ne 0 ]; then echo "Build failed for NIST. Building sbsa without NIST" @@ -55,6 +55,6 @@ if [ "$1" == "NIST" ]; then fi if [ $NISTStatus -ne 0 ]; then - build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf + build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m ShellPkg/Application/sbsa-acs/uefi_app/SbsaAvs.inf fi diff --git a/tools/scripts/avssetup.sh b/tools/scripts/avssetup.sh index f08fe5c3..7429821f 100755 --- a/tools/scripts/avssetup.sh +++ b/tools/scripts/avssetup.sh @@ -10,5 +10,5 @@ echo -e "AVS_PATH is set to -> \e[93m $AVS_PATH\e[0m" export EDK2_PATH=$2 echo -e "EDK2_PATH is set to -> \e[93m$EDK2_PATH\e[0m" -ln -s $AVS_PATH/ $EDK2_PATH/AppPkg/Applications/sbsa-acs +ln -s $AVS_PATH/ $EDK2_PATH/ShellPkg/Application/sbsa-acs diff --git a/uefi_app/SbsaAvs.inf b/uefi_app/SbsaAvs.inf index f8b24866..46ce0b0c 100644 --- a/uefi_app/SbsaAvs.inf +++ b/uefi_app/SbsaAvs.inf @@ -173,7 +173,6 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec ShellPkg/ShellPkg.dec - EdkCompatibilityPkg/EdkCompatibilityPkg.dec [LibraryClasses] SbsaValLib diff --git a/uefi_app/SbsaAvsNist.inf b/uefi_app/SbsaAvsNist.inf index c33d5190..9058c112 100644 --- a/uefi_app/SbsaAvsNist.inf +++ b/uefi_app/SbsaAvsNist.inf @@ -174,7 +174,6 @@ MdePkg/MdePkg.dec MdeModulePkg/MdeModulePkg.dec ShellPkg/ShellPkg.dec - EdkCompatibilityPkg/EdkCompatibilityPkg.dec [LibraryClasses] SbsaNistLib From bd27a4ccbe8e10f1f4f28f64f4a57eb6fb9cc231 Mon Sep 17 00:00:00 2001 From: Rajat Goyal Date: Wed, 23 Sep 2020 12:28:23 +0530 Subject: [PATCH 3/3] Fix & Updates - Log Alignment - Print RCiEP/iEP Information - PCIe: Modified memcpy in test_p035, test_p051 for copying PCIe config space - Document Updates for ACSv3.0 Signed-off-by: Rajat Goyal Co-authored-by: Chetan Rathore Co-authored-by: Sakar Arora Co-authored-by: Gowtham Siddarth Co-authored-by: Sujana M Co-authored-by: Rajat Goyal Co-authored-by: Ashwinth M --- ..._Architecture_Compliance_Test_Scenario.pdf | Bin 666680 -> 801849 bytes ...BSA_Architecture_Compliance_User_Guide.pdf | Bin 381743 -> 377879 bytes ...ture_Compliance_Validation_Methodology.pdf | Bin 497927 -> 524146 bytes test_pool/exerciser/test_e012.c | 9 +- test_pool/exerciser/test_e013.c | 15 ++- test_pool/exerciser/test_e014.c | 12 +- test_pool/exerciser/test_e015.c | 6 +- test_pool/io_virt/test_i005.c | 2 +- test_pool/io_virt/test_i006.c | 6 +- test_pool/io_virt/test_i007.c | 8 +- test_pool/pcie/test_p035.c | 12 +- test_pool/pcie/test_p048.c | 8 ++ test_pool/pcie/test_p051.c | 10 +- test_pool/pcie/test_p057.c | 5 +- val/include/val_interface.h | 1 + val/src/avs_exerciser.c | 8 +- val/src/avs_iovirt.c | 7 +- val/src/avs_pcie.c | 124 ++++++++++++++---- val/src/avs_smmu.c | 7 + val/sys_arch_src/smmu_v3/smmu_reg.h | 13 +- val/sys_arch_src/smmu_v3/smmu_v3.c | 16 ++- val/sys_arch_src/smmu_v3/smmu_v3.h | 10 +- 22 files changed, 201 insertions(+), 78 deletions(-) diff --git a/docs/Arm_SBSA_Architecture_Compliance_Test_Scenario.pdf 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