diff --git a/test_pool/exerciser/operating_system/test_e001.c b/test_pool/exerciser/operating_system/test_e001.c
index d160ac73..04c93a76 100644
--- a/test_pool/exerciser/operating_system/test_e001.c
+++ b/test_pool/exerciser/operating_system/test_e001.c
@@ -39,7 +39,7 @@ payload(void)
   exerciser_data_t e_data;
 
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
 
   while (instance-- != 0) {
diff --git a/test_pool/exerciser/operating_system/test_e002.c b/test_pool/exerciser/operating_system/test_e002.c
index 13dcdf5d..139df44b 100644
--- a/test_pool/exerciser/operating_system/test_e002.c
+++ b/test_pool/exerciser/operating_system/test_e002.c
@@ -94,7 +94,7 @@ payload(void)
   mem_desc = &mem_desc_array[0];
   dram_buf_in_phys = 0;
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   /* Allocate an array to store base addresses of page tables allocated for
    * all exercisers
diff --git a/test_pool/exerciser/operating_system/test_e003.c b/test_pool/exerciser/operating_system/test_e003.c
index feb18a5c..941dd2a5 100644
--- a/test_pool/exerciser/operating_system/test_e003.c
+++ b/test_pool/exerciser/operating_system/test_e003.c
@@ -100,7 +100,7 @@ payload(void)
   dram_buf_in_phys = 0;
 
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS);
   num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0);
 
   /* Allocate an array to store base addresses of page tables allocated for
diff --git a/test_pool/exerciser/operating_system/test_e004.c b/test_pool/exerciser/operating_system/test_e004.c
index 01b77c6c..54424a9e 100644
--- a/test_pool/exerciser/operating_system/test_e004.c
+++ b/test_pool/exerciser/operating_system/test_e004.c
@@ -279,7 +279,7 @@ cfgspace_transactions_order_check(void)
   uint64_t bdf_addr;
 
   /* Read the number of excerciser cards */
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0) {
 
@@ -335,7 +335,7 @@ barspace_transactions_order_check(void)
   uint32_t status;
 
   /* Read the number of excerciser cards */
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0) {
 
diff --git a/test_pool/exerciser/operating_system/test_e005.c b/test_pool/exerciser/operating_system/test_e005.c
index 0190b022..e0eb8a12 100644
--- a/test_pool/exerciser/operating_system/test_e005.c
+++ b/test_pool/exerciser/operating_system/test_e005.c
@@ -152,7 +152,7 @@ barspace_transactions_order_check(void)
   uint32_t status;
 
   /* Read the number of excerciser cards */
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0) {
 
diff --git a/test_pool/exerciser/operating_system/test_e006.c b/test_pool/exerciser/operating_system/test_e006.c
index 09789289..1c92674c 100644
--- a/test_pool/exerciser/operating_system/test_e006.c
+++ b/test_pool/exerciser/operating_system/test_e006.c
@@ -288,7 +288,7 @@ payload(void)
   uint32_t dpc_cap_base = 0;
 
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0) {
 
diff --git a/test_pool/exerciser/operating_system/test_e007.c b/test_pool/exerciser/operating_system/test_e007.c
index 9a00363b..bce86372 100644
--- a/test_pool/exerciser/operating_system/test_e007.c
+++ b/test_pool/exerciser/operating_system/test_e007.c
@@ -123,7 +123,7 @@ save_config_space(uint32_t rp_bdf)
          performed, all the devices connected below the RP is reset. This needs to be restored
          after SBR*/
       cfg_space_buf[tbl_index] = val_aligned_alloc(MEM_ALIGN_4K, PCIE_CFG_SIZE);
-      if (cfg_space_buf == NULL)
+      if (cfg_space_buf[tbl_index] == NULL)
       {
           val_print(AVS_PRINT_ERR, "\n       Memory allocation failed.", 0);
           val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02));
@@ -169,7 +169,7 @@ payload(void)
 
   fail_cnt = 0;
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0)
   {
diff --git a/test_pool/exerciser/operating_system/test_e008.c b/test_pool/exerciser/operating_system/test_e008.c
index 05a17b4c..e41552b6 100644
--- a/test_pool/exerciser/operating_system/test_e008.c
+++ b/test_pool/exerciser/operating_system/test_e008.c
@@ -44,7 +44,7 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf,
   uint32_t erp_ecam_index;
   uint32_t status;
 
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0)
   {
@@ -172,7 +172,7 @@ payload(void)
   fail_cnt = 0;
   test_skip = 1;
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  req_instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  req_instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   status = val_pcie_p2p_support();
   /* Check If PCIe Hierarchy supports P2P. */
diff --git a/test_pool/mpam/operating_system/test_mpam002.c b/test_pool/mpam/operating_system/test_mpam002.c
index 159959e7..952a059f 100644
--- a/test_pool/mpam/operating_system/test_mpam002.c
+++ b/test_pool/mpam/operating_system/test_mpam002.c
@@ -28,7 +28,7 @@
 static void payload(void)
 {
     uint32_t llc_index;
-    uint32_t cache_identifier;
+    uint64_t cache_identifier;
     uint32_t msc_node_cnt;
     uint32_t rsrc_node_cnt;
     uint32_t msc_index, rsrc_index;
diff --git a/test_pool/mpam/operating_system/test_mpam006.c b/test_pool/mpam/operating_system/test_mpam006.c
index 981292d1..1c9128f6 100644
--- a/test_pool/mpam/operating_system/test_mpam006.c
+++ b/test_pool/mpam/operating_system/test_mpam006.c
@@ -37,7 +37,7 @@ static void payload(void)
     uint32_t msc_index;
     uint32_t rsrc_index;
     uint32_t llc_index;
-    uint32_t cache_identifier;
+    uint64_t cache_identifier;
     uint32_t cache_size;
     uint32_t max_pmg;
     uint32_t max_partid;
diff --git a/test_pool/pcie/operating_system/test_p033.c b/test_pool/pcie/operating_system/test_p033.c
index b17f780c..0678baaf 100644
--- a/test_pool/pcie/operating_system/test_p033.c
+++ b/test_pool/pcie/operating_system/test_p033.c
@@ -34,7 +34,7 @@ payload(void)
   uint32_t pe_index;
   uint32_t tbl_index;
   uint32_t reg_value;
-  uint32_t max_payload_value;
+  int32_t max_payload_value;
   uint32_t dp_type;
   uint32_t test_fails;
   uint32_t test_skip = 1;
diff --git a/test_pool/smmu/operating_system/test_i012.c b/test_pool/smmu/operating_system/test_i012.c
index eccb2d8a..082c0256 100644
--- a/test_pool/smmu/operating_system/test_i012.c
+++ b/test_pool/smmu/operating_system/test_i012.c
@@ -32,7 +32,7 @@ payload()
 {
 
   uint64_t data;
-  uint64_t data_pe_endian;
+  uint64_t data_pe_endian = 0;
   uint32_t num_smmu;
   uint32_t index;
 
diff --git a/val/include/sbsa_avs_exerciser.h b/val/include/sbsa_avs_exerciser.h
index 7c0e3d0f..f91d50d8 100644
--- a/val/include/sbsa_avs_exerciser.h
+++ b/val/include/sbsa_avs_exerciser.h
@@ -109,7 +109,7 @@ typedef struct {
 
 void val_exerciser_create_info_table(void);
 uint32_t val_exerciser_init(uint32_t instance);
-uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance);
+uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type);
 uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance);
 uint32_t val_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, uint32_t instance);
 uint32_t val_exerciser_set_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance);
diff --git a/val/include/sbsa_avs_smmu.h b/val/include/sbsa_avs_smmu.h
index 7b0b9c4d..b69d4c78 100644
--- a/val/include/sbsa_avs_smmu.h
+++ b/val/include/sbsa_avs_smmu.h
@@ -44,7 +44,7 @@ uint32_t
 val_smmu_read_cfg(uint32_t offset, uint32_t index);
 
 uint64_t
-val_smmu_ops(SMMU_OPS_e ops, uint32_t index, void *param1, void *param2);
+val_smmu_ops(SMMU_OPS_e ops, void *param1, void *param2);
 
 uint32_t
 val_smmu_max_pasids(uint32_t smmu_index);
diff --git a/val/include/val_interface.h b/val/include/val_interface.h
index a2d0cdcd..e88305e0 100644
--- a/val/include/val_interface.h
+++ b/val/include/val_interface.h
@@ -54,6 +54,7 @@
 #define SINGLE_TEST_SENTINEL   10000
 #define SINGLE_MODULE_SENTINEL 10001
 
+typedef char char8_t;
 /* GENERIC VAL APIs */
 void val_allocate_shared_mem(void);
 void val_free_shared_mem(void);
diff --git a/val/src/avs_exerciser.c b/val/src/avs_exerciser.c
index 2093f968..70220cf6 100644
--- a/val/src/avs_exerciser.c
+++ b/val/src/avs_exerciser.c
@@ -138,8 +138,9 @@ uint32_t val_get_exerciser_err_info(EXERCISER_ERROR_CODE type)
   @param   instance     - Stimulus hadrware instance number
   @return  value        - Information value for input type
 **/
-uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance)
+uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type)
 {
+
     switch (type) {
     case EXERCISER_NUM_CARDS:
          return g_exerciser_info_table.num_exerciser;
@@ -312,7 +313,7 @@ val_exerciser_execute_tests(uint32_t level)
   val_print(AVS_PRINT_INFO, "\n      Starting Exerciser Setup\n", 0);
 
   val_exerciser_create_info_table();
-  num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   if (num_instances == 0) {
       val_print(AVS_PRINT_WARN, "\n     No Exerciser Devices Found, Skipping Exerciser tests...\n", 0);
diff --git a/val/src/avs_gic.c b/val/src/avs_gic.c
index 7f063440..68fa4e64 100644
--- a/val/src/avs_gic.c
+++ b/val/src/avs_gic.c
@@ -37,6 +37,7 @@ val_gic_execute_tests(uint32_t level, uint32_t num_pe)
 
   uint32_t status, i;
   uint32_t module_skip;
+  status = 0;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_GIC_TEST_NUM_BASE) {
diff --git a/val/src/avs_memory.c b/val/src/avs_memory.c
index 7b742328..5f7552a3 100644
--- a/val/src/avs_memory.c
+++ b/val/src/avs_memory.c
@@ -106,6 +106,7 @@ val_memory_execute_tests(uint32_t level, uint32_t num_pe)
 
   uint32_t status = 0;
   uint32_t i;
+  (void) level;
 
   for (i = 0 ; i < g_num_skip ; i++) {
       if (g_skip_test_num[i] == AVS_MEM_MAP_TEST_NUM_BASE) {
diff --git a/val/src/avs_mmu.c b/val/src/avs_mmu.c
index ade1faaf..03c05b9f 100644
--- a/val/src/avs_mmu.c
+++ b/val/src/avs_mmu.c
@@ -228,7 +228,7 @@ uint32_t val_mmu_update_entry(uint64_t address, uint32_t size)
 **/
 static uint32_t log2_func(uint64_t value)
 {
-    int bit = 0;
+    uint32_t bit = 0;
 
     while (value != 0)
     {
diff --git a/val/src/avs_mpam.c b/val/src/avs_mpam.c
index 91de082f..dab87b4b 100644
--- a/val/src/avs_mpam.c
+++ b/val/src/avs_mpam.c
@@ -38,6 +38,7 @@ val_mpam_execute_tests(uint32_t level, uint32_t num_pe)
   uint32_t status = AVS_STATUS_FAIL, i;
   uint32_t skip_module;
   uint32_t msc_node_cnt;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_MPAM_TEST_NUM_BASE) {
diff --git a/val/src/avs_nist.c b/val/src/avs_nist.c
index c9ce9778..7d8ada05 100644
--- a/val/src/avs_nist.c
+++ b/val/src/avs_nist.c
@@ -31,6 +31,7 @@ uint32_t
 val_nist_execute_tests(uint32_t level, uint32_t num_pe)
 {
   uint32_t status, i;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_NIST_TEST_NUM_BASE) {
diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c
index 64efb7b5..4caef4d7 100644
--- a/val/src/avs_pcie.c
+++ b/val/src/avs_pcie.c
@@ -1242,6 +1242,8 @@ val_pcie_get_atomicop_requester_capable(uint32_t bdf)
 {
   /* TO DO */
   //return pal_pcie_get_atomicop_requester_capable(bdf);
+  (void) bdf;
+
   return 0;
 }
 
diff --git a/val/src/avs_pe.c b/val/src/avs_pe.c
index a1a8069f..3995f8ce 100644
--- a/val/src/avs_pe.c
+++ b/val/src/avs_pe.c
@@ -42,6 +42,7 @@ extern ARM_SMC_ARGS g_smc_args;
 uint32_t
 val_pe_execute_tests(uint32_t level, uint32_t num_pe)
 {
+
   uint32_t status = AVS_STATUS_PASS, i;
 
   for (i = 0; i < g_num_skip; i++) {
@@ -242,11 +243,13 @@ val_pe_reg_read(uint32_t reg_id)
             return AA64ReadMair1();
           if (AA64ReadCurrentEL() == AARCH64_EL2)
             return AA64ReadMair2();
+          break;
       case TCR_ELx:
           if (AA64ReadCurrentEL() == AARCH64_EL1)
             return AA64ReadTcr1();
           if (AA64ReadCurrentEL() == AARCH64_EL2)
             return AA64ReadTcr2();
+          break;
       case ID_AA64ZFR0_EL1:
           return AA64ReadZfr0();
       default:
diff --git a/val/src/avs_pe_infra.c b/val/src/avs_pe_infra.c
index 0f91c4ae..009f227a 100644
--- a/val/src/avs_pe_infra.c
+++ b/val/src/avs_pe_infra.c
@@ -378,6 +378,7 @@ val_pe_context_save(uint64_t sp, uint64_t elr)
 void
 val_pe_context_restore(uint64_t sp)
 {
+    (void) sp;
     sp = 0;
     *(uint64_t *)(g_stack_pointer+8) = g_ret_addr;
 }
@@ -408,7 +409,7 @@ void
 val_pe_default_esr(uint64_t interrupt_type, void *context)
 {
     uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-    val_print(AVS_PRINT_WARN, "\n        Unexpected exception occured", 0);
+    val_print(AVS_PRINT_WARN, "\n        Unexpected exception occured of type %d", interrupt_type);
 
 #ifndef TARGET_LINUX
     if (pal_target_is_bm()) {
diff --git a/val/src/avs_peripherals.c b/val/src/avs_peripherals.c
index ece5b5d5..9ee84291 100644
--- a/val/src/avs_peripherals.c
+++ b/val/src/avs_peripherals.c
@@ -38,6 +38,8 @@ val_peripheral_execute_tests(uint32_t level, uint32_t num_pe)
 
   uint32_t status = AVS_STATUS_SKIP, i;
   uint32_t skip_module;
+  (void) level;
+  (void) num_pe;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_PER_TEST_NUM_BASE) {
@@ -54,7 +56,6 @@ val_peripheral_execute_tests(uint32_t level, uint32_t num_pe)
   }
 
   val_print_test_start("Peripheral");
-
   return status;
 }
 #endif
diff --git a/val/src/avs_pmu.c b/val/src/avs_pmu.c
index dff8ba4b..0e4af0f7 100644
--- a/val/src/avs_pmu.c
+++ b/val/src/avs_pmu.c
@@ -37,6 +37,7 @@ val_pmu_execute_tests(uint32_t level, uint32_t num_pe)
   uint32_t status = AVS_STATUS_FAIL;
   uint32_t skip_module;
   uint32_t i, pmu_node_count;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_PMU_TEST_NUM_BASE) {
diff --git a/val/src/avs_ras.c b/val/src/avs_ras.c
index 37c0009d..f01fff5e 100644
--- a/val/src/avs_ras.c
+++ b/val/src/avs_ras.c
@@ -34,9 +34,11 @@ static RAS2_INFO_TABLE *g_ras2_info_table;
 uint32_t
 val_ras_execute_tests(uint32_t level, uint32_t num_pe)
 {
+
   uint32_t status, i;
   uint32_t skip_module;
   uint64_t num_ras_nodes = 0;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_RAS_TEST_NUM_BASE) {
@@ -417,7 +419,7 @@ uint64_t
 val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx)
 {
   uint64_t base, value = INVALID_RAS_REG_VAL;
-  uint32_t start_rec_index, offset;
+  uint32_t start_rec_index, offset = 0;
   uint64_t num_err_recs, err_rec_impl_bitmap;
 
   start_rec_index = g_ras_info_table->node[node_index].intf_info.start_rec_index;
@@ -568,7 +570,7 @@ void
 val_ras_reg_write(uint32_t node_index, uint32_t reg, uint64_t write_data)
 {
   uint64_t base;
-  uint32_t rec_index, offset;
+  uint32_t rec_index, offset = 0;
 
   rec_index = g_ras_info_table->node[node_index].intf_info.start_rec_index;
 
@@ -768,7 +770,7 @@ uint32_t val_ras_check_err_record(uint32_t node_index, uint32_t error_type)
 {
   uint32_t status = AVS_STATUS_PASS;
   uint64_t err_status;
-  uint32_t err_type_mask;
+  uint32_t err_type_mask = 0;
 
   /* Loop for Wait */
   val_ras_wait_timeout(1);
diff --git a/val/src/avs_smmu.c b/val/src/avs_smmu.c
index 7413fad6..2280a246 100644
--- a/val/src/avs_smmu.c
+++ b/val/src/avs_smmu.c
@@ -176,7 +176,7 @@ val_smmu_check_device_iova(uint32_t ctrl_index, addr_t dma_addr)
 
 
 uint64_t
-val_smmu_ops(SMMU_OPS_e ops, uint32_t smmu_index, void *param1, void *param2)
+val_smmu_ops(SMMU_OPS_e ops, void *param1, void *param2)
 {
 
   switch(ops)
diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c
index cc267d91..f4a6efc7 100644
--- a/val/src/avs_test_infra.c
+++ b/val/src/avs_test_infra.c
@@ -538,6 +538,7 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid)
   uint32_t status = 0;
   uint32_t error_flag = 0;
   uint32_t my_index = val_pe_get_index_mpid(val_pe_get_mpid());
+  (void) test_num;
 
   /* this special case is needed when the Main PE is not the first entry
      of pe_info_table but num_pe is 1 for SOC tests */
diff --git a/val/src/avs_timer.c b/val/src/avs_timer.c
index f7fd5faa..84bda436 100644
--- a/val/src/avs_timer.c
+++ b/val/src/avs_timer.c
@@ -37,6 +37,8 @@ val_timer_execute_tests(uint32_t level, uint32_t num_pe)
 {
   uint32_t status = AVS_STATUS_SKIP, i;
   uint32_t skip_module;
+  (void) level;
+  (void) num_pe;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_TIMER_TEST_NUM_BASE) {
@@ -53,7 +55,6 @@ val_timer_execute_tests(uint32_t level, uint32_t num_pe)
   }
 
   val_print_test_start("Timer");
-
   return status;
 }
 
@@ -92,22 +93,27 @@ val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance)
           val_platform_timer_get_entry_index (instance, &block_num, &block_index);
           if (block_num != 0xFFFF)
               return ((g_timer_info_table->gt_info[block_num].flags[block_index] >> 16) & 1);
+      break;
       case TIMER_INFO_SYS_CNTL_BASE:
           val_platform_timer_get_entry_index (instance, &block_num, &block_index);
           if (block_num != 0xFFFF)
               return g_timer_info_table->gt_info[block_num].block_cntl_base;
+      break;
       case TIMER_INFO_SYS_CNT_BASE_N:
           val_platform_timer_get_entry_index (instance, &block_num, &block_index);
           if (block_num != 0xFFFF)
               return g_timer_info_table->gt_info[block_num].GtCntBase[block_index];
+      break;
       case TIMER_INFO_FRAME_NUM:
           val_platform_timer_get_entry_index (instance, &block_num, &block_index);
           if (block_num != 0xFFFF)
               return g_timer_info_table->gt_info[block_num].frame_num[block_index];
+      break;
       case TIMER_INFO_SYS_INTID:
           val_platform_timer_get_entry_index (instance, &block_num, &block_index);
           if (block_num != 0xFFFF)
             return g_timer_info_table->gt_info[block_num].gsiv[block_index];
+      break;
       case TIMER_INFO_PHY_EL1_FLAGS:
           return g_timer_info_table->header.ns_el1_timer_flag;
       case TIMER_INFO_VIR_EL1_FLAGS:
@@ -119,6 +125,7 @@ val_timer_get_info(TIMER_INFO_e info_type, uint64_t instance)
     default:
       return 0;
   }
+  return 0;
 }
 
 void
diff --git a/val/src/avs_wakeup.c b/val/src/avs_wakeup.c
index 9e957c7d..7e4abe7e 100644
--- a/val/src/avs_wakeup.c
+++ b/val/src/avs_wakeup.c
@@ -35,9 +35,11 @@ extern int32_t gPsciConduit;
 uint32_t
 val_wakeup_execute_tests(uint32_t level, uint32_t num_pe)
 {
+
   uint32_t status = AVS_STATUS_SKIP, i;
   uint32_t skip_module;
-
+  (void) level;
+  (void) num_pe;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_WAKEUP_TEST_NUM_BASE) {
diff --git a/val/src/avs_wd.c b/val/src/avs_wd.c
index 497f135c..5f2d9565 100644
--- a/val/src/avs_wd.c
+++ b/val/src/avs_wd.c
@@ -35,6 +35,7 @@ uint32_t
 val_wd_execute_tests(uint32_t level, uint32_t num_pe)
 {
   uint32_t status = AVS_STATUS_PASS, i;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_WD_TEST_NUM_BASE) {
diff --git a/val/sys_arch_src/gic/its/sbsa_gic_its.c b/val/sys_arch_src/gic/its/sbsa_gic_its.c
index 00bc6d79..e3e6fa17 100644
--- a/val/sys_arch_src/gic/its/sbsa_gic_its.c
+++ b/val/sys_arch_src/gic/its/sbsa_gic_its.c
@@ -128,13 +128,13 @@ uint32_t ArmGicSetItsTables(uint32_t its_index)
   uint32_t                DevBits, CIDBits;
   uint64_t                Address;
   uint64_t                ItsBase;
-
+  uint64_t                offset;
   ItsBase = g_gic_its_info->GicIts[its_index].Base;
 
   /* Allocate Memory for Table Depending on the Type of the table in GITS_BASER<n>. */
   for (it = 0; it < ARM_NUM_GITS_BASER; it++) {
-
-    its_baser = val_mmio_read64(ItsBase + ARM_GITS_BASER(it));
+    offset = (uint64_t) ARM_GITS_BASER(it);
+    its_baser = val_mmio_read64(ItsBase + offset);
     table_type = ARM_GITS_BASER_GET_TYPE(its_baser);
     entry_size = ARM_GITS_BASER_GET_ENTRY_SIZE(its_baser);
 
@@ -162,13 +162,12 @@ uint32_t ArmGicSetItsTables(uint32_t its_index)
   }
 
   val_memory_set((void *)Address,  PAGES_TO_SIZE(Pages), 0);
-
-  write_value = val_mmio_read64(ItsBase + ARM_GITS_BASER(it));
+  write_value = val_mmio_read64(ItsBase + offset);
   write_value = write_value & (~ARM_GITS_BASER_PA_MASK);
   write_value = write_value | (Address & ARM_GITS_BASER_PA_MASK);
   write_value = write_value | ARM_GITS_BASER_VALID;
   write_value = write_value | (Pages-1);
-  val_mmio_write64(ItsBase + ARM_GITS_BASER(it), write_value);
+  val_mmio_write64(ItsBase + offset, write_value);
 
   }
 
@@ -220,7 +219,6 @@ void
 WriteCmdQMAPC(
    uint32_t     its_index,
    uint64_t     *CMDQ_BASE,
-   uint32_t     device_id,
    uint32_t     Clctn_ID,
    uint32_t     RDBase,
    uint64_t     Valid
@@ -431,7 +429,7 @@ void val_its_create_lpi_map(uint32_t its_index, uint32_t device_id,
                 g_gic_its_info->GicIts[its_index].ITTBase,
                 g_gic_its_info->GicIts[its_index].IDBits, 0x1 /*Valid*/);
   /* Map Collection using MAPC */
-  WriteCmdQMAPC(its_index, (uint64_t *)(ItsCommandBase), device_id,
+  WriteCmdQMAPC(its_index, (uint64_t *)(ItsCommandBase),
                 0x1 /*Clctn_ID*/, RDBase, 0x1 /*Valid*/);
   /* Map Interrupt using MAPI */
   WriteCmdQMAPI(its_index, (uint64_t *)(ItsCommandBase), device_id, int_id, 0x1 /*Clctn_ID*/);
@@ -539,8 +537,7 @@ uint32_t val_its_init(void)
   }
 
   /* Configure Redistributor For LPIs */
-  Status = ArmGicRedistributorConfigurationForLPI(g_gic_its_info->GicDBase,
-                                                  g_gic_its_info->GicRdBase);
+  Status = ArmGicRedistributorConfigurationForLPI(g_gic_its_info->GicRdBase);
   if (Status)
     return Status;
 
diff --git a/val/sys_arch_src/gic/its/sbsa_gic_its.h b/val/sys_arch_src/gic/its/sbsa_gic_its.h
index eeb8a5cb..d865751d 100644
--- a/val/sys_arch_src/gic/its/sbsa_gic_its.h
+++ b/val/sys_arch_src/gic/its/sbsa_gic_its.h
@@ -170,7 +170,7 @@
 #define ITS_NEXT_CMD_PTR    4
 #define NUM_BYTES_IN_DW     8
 
-uint32_t ArmGicRedistributorConfigurationForLPI(uint64_t gicd_base, uint64_t rd_base);
+uint32_t ArmGicRedistributorConfigurationForLPI(uint64_t rd_base);
 
 void ClearConfigTable(uint32_t int_id);
 void SetConfigTable(uint32_t int_id, uint32_t Priority);
diff --git a/val/sys_arch_src/gic/its/sbsa_gic_redistributor.c b/val/sys_arch_src/gic/its/sbsa_gic_redistributor.c
index c34afacf..329fc056 100644
--- a/val/sys_arch_src/gic/its/sbsa_gic_redistributor.c
+++ b/val/sys_arch_src/gic/its/sbsa_gic_redistributor.c
@@ -22,7 +22,6 @@ static uint64_t ConfigBase;
 
 uint32_t
 ArmGicSetItsConfigTableBase(
-    uint64_t    GicDistributorBase,
     uint64_t    GicRedistributorBase
   )
 {
@@ -65,7 +64,6 @@ ArmGicSetItsConfigTableBase(
 
 uint32_t
 ArmGicSetItsPendingTableBase(
-    uint64_t    GicDistributorBase,
     uint64_t    GicRedistributorBase
   )
 {
@@ -78,7 +76,6 @@ ArmGicSetItsPendingTableBase(
   uint32_t                gicr_propbaser_idbits;
   uint64_t                Address;
 
-
   /* Get Memory size by reading the GICD_TYPER.IDBits, GICR_PROPBASER.IDBits field */
   gicr_propbaser_idbits = ARM_GICR_PROPBASER_IDbits(
                           val_mmio_read64(GicRedistributorBase + ARM_GICR_PROPBASER));
@@ -133,20 +130,19 @@ void EnableLPIsRD(uint64_t GicRedistributorBase)
 
 uint32_t
 ArmGicRedistributorConfigurationForLPI(
-    uint64_t    GicDistributorBase,
     uint64_t    GicRedistributorBase
   )
 {
   uint32_t    Status;
   /* Set Configuration Table Base */
 
-  Status = ArmGicSetItsConfigTableBase(GicDistributorBase, GicRedistributorBase);
+  Status = ArmGicSetItsConfigTableBase(GicRedistributorBase);
   if ((Status)) {
     return Status;
   }
 
   /* Set Pending Table Base For Each Redistributor */
-  Status = ArmGicSetItsPendingTableBase(GicDistributorBase, GicRedistributorBase);
+  Status = ArmGicSetItsPendingTableBase(GicRedistributorBase);
   if ((Status)) {
     return Status;
   }
diff --git a/val/sys_arch_src/gic/sbsa_exception.c b/val/sys_arch_src/gic/sbsa_exception.c
index f4620fe3..0f8d718b 100644
--- a/val/sys_arch_src/gic/sbsa_exception.c
+++ b/val/sys_arch_src/gic/sbsa_exception.c
@@ -29,8 +29,11 @@ irq_handler g_intr_handler[NUM_ARM_MAX_INTERRUPT];
 
 void default_irq_handler(uint64_t exception_type, void *context)
 {
+
   uint32_t ack_interrupt;
   uint32_t iar_ack_val;
+  (void) exception_type;
+  (void) context;
 
   iar_ack_val = val_sbsa_gic_acknowledgeInterrupt();
   ack_interrupt = iar_ack_val & 0xFFFFFF;
diff --git a/val/sys_arch_src/smmu_v3/smmu_v3.c b/val/sys_arch_src/smmu_v3/smmu_v3.c
index 2cc418a5..e2ddf390 100644
--- a/val/sys_arch_src/smmu_v3/smmu_v3.c
+++ b/val/sys_arch_src/smmu_v3/smmu_v3.c
@@ -466,7 +466,7 @@ smmu_master_t *smmu_master_at(uint32_t sid)
 }
 
 // Event handler. Gives the info of the kind of event error generated.
-static int smmu_handle_evt(smmu_dev_t *smmu, uint64_t *event)
+static int smmu_handle_evt(uint64_t *event)
 {
         switch (BITFIELD_GET(EVTQ_0_ID, event[0])) {
         case EVT_ID_UUT:
@@ -610,9 +610,9 @@ void smmu_evtq_thread(void)
     do {
         while (!smmu_queue_remove_raw(evntq, event)) {
             uint8_t id = BITFIELD_GET(EVTQ_0_ID, event[0]);
-            ret = smmu_handle_evt(smmu, event);
+            ret = smmu_handle_evt(event);
             val_print(AVS_PRINT_TEST, "\n  event 0x%02x received: %d     ", id);
-            for (int i = 0; i < ARRAY_SIZE(event); ++i)
+            for (int i = 0; i < EVNTQ_DWORDS_PER_ENT; ++i)
             {
                 val_print(AVS_PRINT_TEST, "\n  0x%016llx     ", (unsigned long long)event[i]);
             }
diff --git a/val/sys_arch_src/smmu_v3/smmu_v3.h b/val/sys_arch_src/smmu_v3/smmu_v3.h
index dbd12236..a6db5fcc 100644
--- a/val/sys_arch_src/smmu_v3/smmu_v3.h
+++ b/val/sys_arch_src/smmu_v3/smmu_v3.h
@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2020, 2022-2023 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2020, 2022-2023, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -24,7 +24,7 @@
 #include "smmu_reg.h"
 #include "../include/sbsa_avs_pe.h"
 
-static uint64_t inline get_max(uint64_t x, uint64_t y)
+static inline uint64_t get_max(uint64_t x, uint64_t y)
 {
     return x > y ? x : y;
 }