From 6202f6f69398cc6fe1330f0cbea724029baa2e6d Mon Sep 17 00:00:00 2001 From: Alexander Fedotov Date: Fri, 19 Jun 2020 17:43:20 +0300 Subject: [PATCH 1/2] Initial Cortex-A AArch64 support. --- CMSIS/Core_AArch64/Include/cmsis_compiler.h | 245 ++++++++ CMSIS/Core_AArch64/Include/cmsis_cp15.h | 37 ++ CMSIS/Core_AArch64/Include/cmsis_gcc.h | 438 +++++++++++++ CMSIS/Core_AArch64/Include/cmsis_version.h | 39 ++ CMSIS/Core_AArch64/Include/core_ca53.h | 574 ++++++++++++++++++ Device/ARM/ARMCA53/Include/ARMCA53.h | 102 ++++ .../ARM/ARMCA53/Include/ARMCA53_DSP_DP_FP.h | 102 ++++ Device/ARM/ARMCA53/Include/ARMCA53_FP.h | 102 ++++ Device/ARM/ARMCA53/Include/system_ARMCA53.h | 58 ++ Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld | 315 ++++++++++ .../ARM/ARMCA53/Source/GCC/startup_ARMCA53.c | 229 +++++++ Device/ARM/ARMCA53/Source/system_ARMCA53.c | 106 ++++ 12 files changed, 2347 insertions(+) create mode 100644 CMSIS/Core_AArch64/Include/cmsis_compiler.h create mode 100644 CMSIS/Core_AArch64/Include/cmsis_cp15.h create mode 100644 CMSIS/Core_AArch64/Include/cmsis_gcc.h create mode 100644 CMSIS/Core_AArch64/Include/cmsis_version.h create mode 100644 CMSIS/Core_AArch64/Include/core_ca53.h create mode 100644 Device/ARM/ARMCA53/Include/ARMCA53.h create mode 100644 Device/ARM/ARMCA53/Include/ARMCA53_DSP_DP_FP.h create mode 100644 Device/ARM/ARMCA53/Include/ARMCA53_FP.h create mode 100644 Device/ARM/ARMCA53/Include/system_ARMCA53.h create mode 100644 Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld create mode 100644 Device/ARM/ARMCA53/Source/GCC/startup_ARMCA53.c create mode 100644 Device/ARM/ARMCA53/Source/system_ARMCA53.c diff --git a/CMSIS/Core_AArch64/Include/cmsis_compiler.h b/CMSIS/Core_AArch64/Include/cmsis_compiler.h new file mode 100644 index 0000000000..134f4e159e --- /dev/null +++ b/CMSIS/Core_AArch64/Include/cmsis_compiler.h @@ -0,0 +1,245 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef CMSIS_DEPRECATED + #define CMSIS_DEPRECATED __attribute__((deprecated)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef CMSIS_DEPRECATED + #warning No compiler specific solution for CMSIS_DEPRECATED. CMSIS_DEPRECATED is ignored. + #define CMSIS_DEPRECATED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/CMSIS/Core_AArch64/Include/cmsis_cp15.h b/CMSIS/Core_AArch64/Include/cmsis_cp15.h new file mode 100644 index 0000000000..0373c3b8b7 --- /dev/null +++ b/CMSIS/Core_AArch64/Include/cmsis_cp15.h @@ -0,0 +1,37 @@ +/**************************************************************************//** + * @file cmsis_cp15.h + * @brief CMSIS compiler specific macros, functions, instructions + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_CP15_H +#define __CMSIS_CP15_H + + + + +#endif diff --git a/CMSIS/Core_AArch64/Include/cmsis_gcc.h b/CMSIS/Core_AArch64/Include/cmsis_gcc.h new file mode 100644 index 0000000000..b1c0d7e7c5 --- /dev/null +++ b/CMSIS/Core_AArch64/Include/cmsis_gcc.h @@ -0,0 +1,438 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __NAKED + #define __NAKED __attribute__((naked)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __EARLY_INIT + /** + \brief Early system init: some useful things to be done on early stage. + \details This default implementation. + + */ +__STATIC_FORCEINLINE void __cmsis_cpu_init(void) +{ + +} + +#define __EARLY_INIT __cmsis_cpu_init +#endif + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __EL3StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __EL3StackLimit +#endif + +#ifndef __VECTOR_TABLE_EL3 +#define __VECTOR_TABLE_EL3 __EL3_Vectors +#endif + +#ifndef __VECTOR_TABLE_EL2 +#define __VECTOR_TABLE_EL2 __EL2_Vectors +#endif + +#ifndef __VECTOR_TABLE_EL1 +#define __VECTOR_TABLE_EL1 __EL1_Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute__((aligned(4096), used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi":::"memory") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe":::"memory") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/* ########################### Core Function Access ########################### */ + +/** \brief Get MPIDR EL1 + \return Multiprocessor Affinity Register value + */ +__STATIC_FORCEINLINE uint64_t __get_MPIDR_EL1(void) +{ + uint64_t result; + __ASM volatile("MRS %0, MPIDR_EL1" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Get MAIR EL3 + \return MAIR value + */ +__STATIC_FORCEINLINE uint64_t __get_MAIR_EL3(void) +{ + uint64_t result; + __ASM volatile("MRS %0, mair_el3" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set MAIR EL3 + \param [in] mair MAIR value to set + */ +__STATIC_FORCEINLINE void __set_MAIR_EL3(uint64_t mair) +{ + __ASM volatile("MSR mair_el3, %0" : : "r" (mair) : "memory"); +} + +/** \brief Get TCR EL3 + \return TCR value + */ +__STATIC_FORCEINLINE uint64_t __get_TCR_EL3(void) +{ + uint64_t result; + __ASM volatile("MRS %0, tcr_el3" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set TCR EL3 + \param [in] tcr TCR value to set + */ +__STATIC_FORCEINLINE void __set_TCR_EL3(uint64_t tcr) +{ + __ASM volatile("MSR tcr_el3, %0" : : "r" (tcr) : "memory"); +} + +/** \brief Get TTBR0 EL3 + \return Translation Table Base Register 0 value + */ +__STATIC_FORCEINLINE uint64_t __get_TTBR0_EL3(void) +{ + uint64_t result; + __ASM volatile("MRS %0, ttbr0_el3" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set TTBR0 EL3 + \param [in] ttbr0 Translation Table Base Register 0 value to set + */ +__STATIC_FORCEINLINE void __set_TTBR0_EL3(uint64_t ttbr0) +{ + __ASM volatile("MSR ttbr0_el3, %0" : : "r" (ttbr0) : "memory"); +} + +/** \brief Get SCTLR EL3 + \return STRLR EL3 value + */ +__STATIC_FORCEINLINE uint64_t __get_SCTLR_EL3(void) +{ + uint64_t result; + __ASM volatile("MRS %0, sctlr_el3" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set SCTLR EL3 + \param [in] vbar SCTLR value to set + */ +__STATIC_FORCEINLINE void __set_SCTLR_EL3(uint64_t sctlr) +{ + __ASM volatile("MSR sctlr_el3, %0" : : "r" (sctlr) : "memory"); +} + +/** \brief Set VBAR EL3 + \param [in] vbar VBAR value to set + */ +__STATIC_FORCEINLINE void __set_VBAR_EL3(uint64_t vbar) +{ + __ASM volatile("MSR vbar_el3, %0" : : "r" (vbar) : "memory"); +} + +/** \brief Set VBAR EL2 + \param [in] vbar VBAR value to set + */ +__STATIC_FORCEINLINE void __set_VBAR_EL2(uint64_t vbar) +{ + __ASM volatile("MSR vbar_el2, %0" : : "r" (vbar) : "memory"); +} + +/** \brief Set VBAR EL1 + \param [in] vbar VBAR value to set + */ +__STATIC_FORCEINLINE void __set_VBAR_EL1(uint64_t vbar) +{ + __ASM volatile("MSR vbar_el1, %0" : : "r" (vbar) : "memory"); +} + +/** \brief Get Stack Pointer + \return Stack Pointer value + */ +__STATIC_FORCEINLINE uint64_t __get_SP(void) +{ + uint64_t result; + __ASM volatile("MOV %0, sp" : "=r" (result) : : "memory"); + return result; +} + +/** \brief Set Stack Pointer + \param [in] stack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_SP(uint64_t stack) +{ + __ASM volatile("MOV sp, %0" : : "r" (stack) : "memory"); +} + + +/* + * Include common core functions to access Coprocessor 15 registers + */ + +#define __get_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) +#define __set_CP(cp, op1, Rt, CRn, CRm, op2) __ASM volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) +#define __get_CP64(cp, op1, Rt, CRm) __ASM volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) +#define __set_CP64(cp, op1, Rt, CRm) __ASM volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) + +#include "cmsis_cp15.h" + +/** \brief Enable Floating Point Unit + + Critical section, called from undef handler, so systick is disabled + */ +__STATIC_INLINE void __FPU_Enable(void) +{ + __ASM volatile( + //In AArch64, you do not need to enable access to the NEON and FP registers. + //However, access to the NEON and FP registers can still be trapped. + + // Disable trapping of accessing in EL3 and EL2. + " MSR CPTR_EL3, XZR \n" + " MSR CPTR_EL2, XZR \n" + + // Disable access trapping in EL1 and EL0. + " MOV X1, #(0x3 << 20) \n" + + // FPEN disables trapping to EL1. + " MSR CPACR_EL1, X1 \n" + + //Ensure that subsequent instructions occur in the context of VFP/NEON access permitted + " ISB " + + : : : "cc", "x1" + ); +} + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/CMSIS/Core_AArch64/Include/cmsis_version.h b/CMSIS/Core_AArch64/Include/cmsis_version.h new file mode 100644 index 0000000000..f25c4fa1e4 --- /dev/null +++ b/CMSIS/Core_AArch64/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(A) Version definitions + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 1U) /*!< [31:16] CMSIS Core(A) main version */ +#define __CM_CMSIS_VERSION_SUB ( 0U) /*!< [15:0] CMSIS Core(A) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(A) version number */ +#endif diff --git a/CMSIS/Core_AArch64/Include/core_ca53.h b/CMSIS/Core_AArch64/Include/core_ca53.h new file mode 100644 index 0000000000..f313b4df1b --- /dev/null +++ b/CMSIS/Core_AArch64/Include/core_ca53.h @@ -0,0 +1,574 @@ +/**************************************************************************//** + * @file core_ca53.h + * @brief CMSIS Cortex-A53 Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#elif defined ( __GNUC__ ) + #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ +#endif + +#ifndef __CORE_CA53_H_GENERIC +#define __CORE_CA53_H_GENERIC + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_A53 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CA53 definitions */ +#define __CA53_CMSIS_VERSION_MAIN (1U) /*!< \brief [31:16] CMSIS-Core(A) main version */ +#define __CA53_CMSIS_VERSION_SUB (0U) /*!< \brief [15:0] CMSIS-Core(A) sub version */ +#define __CA53_CMSIS_VERSION ((__CA53_CMSIS_VERSION_MAIN << 16U) | \ + __CA53_CMSIS_VERSION_SUB ) /*!< \brief CMSIS-Core(A) version number */ + +#define __CORTEX_A (53U) /*!< Cortex-A Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__ARM_FP) && (__ARM_FP==0xE) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA53_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CA53_H_DEPENDANT +#define __CORE_CA53_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + + /* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CA53_REV + #define __CA53_REV 0x0000U + #warning "__CA53_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __GIC_PRESENT + #define __GIC_PRESENT 1U + #warning "__GIC_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __TIM_PRESENT + #define __TIM_PRESENT 1U + #warning "__TIM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L2C_PRESENT + #define __L2C_PRESENT 0U + #warning "__L2C_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __L3C_PRESENT + #define __L3C_PRESENT 0U + #warning "__L3C_PRESENT not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ +#define RESERVED(N, T) T RESERVED##N; // placeholder struct members used for "reserved" areas + +/*@} end of group Cortex_A53 */ + + + + /******************************************************************************* + * Register Abstraction + Core Register contain: + - CPSR + - CP15 Registers + - L2C-310 Cache Controller + - Generic Interrupt Controller Distributor + - Generic Interrupt Controller Interface + ******************************************************************************/ + +/* Core Register CPSR */ +typedef union +{ + struct + { + uint32_t M:5; /*!< \brief bit: 0.. 4 Mode field */ + uint32_t T:1; /*!< \brief bit: 5 Thumb execution state bit */ + uint32_t F:1; /*!< \brief bit: 6 FIQ mask bit */ + uint32_t I:1; /*!< \brief bit: 7 IRQ mask bit */ + uint32_t A:1; /*!< \brief bit: 8 Asynchronous abort mask bit */ + uint32_t E:1; /*!< \brief bit: 9 Endianness execution state bit */ + RESERVED(0:6, uint32_t) + uint32_t GE:4; /*!< \brief bit: 16..19 Greater than or Equal flags */ + RESERVED(1:1, uint32_t) + uint32_t DIT:1; /*!< \brief bit: 21 Data Independent Timing */ + uint32_t PAN:1; /*!< \brief bit: 22 Privileged Access Never */ + RESERVED(2:4, uint32_t) + uint32_t Q:1; /*!< \brief bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< \brief bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< \brief bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< \brief bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< \brief bit: 31 Negative condition code flag */ + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} CPSR_Type; + + + +/* CPSR Register Definitions */ +#define CPSR_N_Pos 31U /*!< \brief CPSR: N Position */ +#define CPSR_N_Msk (1UL << CPSR_N_Pos) /*!< \brief CPSR: N Mask */ + +#define CPSR_Z_Pos 30U /*!< \brief CPSR: Z Position */ +#define CPSR_Z_Msk (1UL << CPSR_Z_Pos) /*!< \brief CPSR: Z Mask */ + +#define CPSR_C_Pos 29U /*!< \brief CPSR: C Position */ +#define CPSR_C_Msk (1UL << CPSR_C_Pos) /*!< \brief CPSR: C Mask */ + +#define CPSR_V_Pos 28U /*!< \brief CPSR: V Position */ +#define CPSR_V_Msk (1UL << CPSR_V_Pos) /*!< \brief CPSR: V Mask */ + +#define CPSR_Q_Pos 27U /*!< \brief CPSR: Q Position */ +#define CPSR_Q_Msk (1UL << CPSR_Q_Pos) /*!< \brief CPSR: Q Mask */ + +#define CPSR_PAN_Pos 22U /*!< \brief CPSR: PAN Position */ +#define CPSR_PAN_Msk (0x1UL << CPSR_PAN_Pos) /*!< \brief CPSR: PAN Mask */ + +#define CPSR_DIT_Pos 21U /*!< \brief CPSR: DIT Position */ +#define CPSR_DIT_Msk (0x1UL << CPSR_PAN_Pos) /*!< \brief CPSR: DIT Mask */ + +#define CPSR_GE_Pos 16U /*!< \brief CPSR: GE Position */ +#define CPSR_GE_Msk (0xFUL << CPSR_GE_Pos) /*!< \brief CPSR: GE Mask */ + +#define CPSR_E_Pos 9U /*!< \brief CPSR: E Position */ +#define CPSR_E_Msk (1UL << CPSR_E_Pos) /*!< \brief CPSR: E Mask */ + +#define CPSR_A_Pos 8U /*!< \brief CPSR: A Position */ +#define CPSR_A_Msk (1UL << CPSR_A_Pos) /*!< \brief CPSR: A Mask */ + +#define CPSR_I_Pos 7U /*!< \brief CPSR: I Position */ +#define CPSR_I_Msk (1UL << CPSR_I_Pos) /*!< \brief CPSR: I Mask */ + +#define CPSR_F_Pos 6U /*!< \brief CPSR: F Position */ +#define CPSR_F_Msk (1UL << CPSR_F_Pos) /*!< \brief CPSR: F Mask */ + +#define CPSR_T_Pos 5U /*!< \brief CPSR: T Position */ +#define CPSR_T_Msk (1UL << CPSR_T_Pos) /*!< \brief CPSR: T Mask */ + +#define CPSR_M_Pos 0U /*!< \brief CPSR: M Position */ +#define CPSR_M_Msk (0x1FUL << CPSR_M_Pos) /*!< \brief CPSR: M Mask */ + +#define CPSR_M_USR 0x10U /*!< \brief CPSR: M User mode (PL0) */ +#define CPSR_M_FIQ 0x11U /*!< \brief CPSR: M Fast Interrupt mode (PL1) */ +#define CPSR_M_IRQ 0x12U /*!< \brief CPSR: M Interrupt mode (PL1) */ +#define CPSR_M_SVC 0x13U /*!< \brief CPSR: M Supervisor mode (PL1) */ +#define CPSR_M_MON 0x16U /*!< \brief CPSR: M Monitor mode (PL1) */ +#define CPSR_M_ABT 0x17U /*!< \brief CPSR: M Abort mode (PL1) */ +#define CPSR_M_HYP 0x1AU /*!< \brief CPSR: M Hypervisor mode (PL2) */ +#define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ +#define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ + +/* CP15 Register SCTLR */ +typedef union +{ + struct + { + uint32_t M:1; /*!< \brief bit: 0 MMU enable */ + uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint32_t C:1; /*!< \brief bit: 2 Cache enable */ + RESERVED(0:2, uint32_t) + uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ + uint32_t THEE:1; /*!< \brief bit: 6 */ + uint32_t ITD:1; /*!< \brief bit: 7 IT disable */ + uint32_t SED:1; /*!< \brief bit: 8 SETEBD disable */ + RESERVED(1:3, uint32_t) + uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ + RESERVED(2:2, uint32_t) + uint32_t nTWI:1; /*!< \brief bit: 16 Not trap WFI */ + RESERVED(3:1, uint32_t) + uint32_t nTWE:1; /*!< \brief bit: 18 Not trap WFE */ + uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ + RESERVED(4:4, uint32_t) + uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(5:2, uint32_t) + uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ + uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ + uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ + RESERVED(6:1, uint32_t) + } b; /*!< \brief Structure used for bit access */ + uint32_t w; /*!< \brief Type used for word access */ +} SCTLR_Type; + +#define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ +#define SCTLR_TE_Msk (1UL << SCTLR_TE_Pos) /*!< \brief SCTLR: TE Mask */ + +#define SCTLR_AFE_Pos 29U /*!< \brief SCTLR: AFE Position */ +#define SCTLR_AFE_Msk (1UL << SCTLR_AFE_Pos) /*!< \brief SCTLR: AFE Mask */ + +#define SCTLR_TRE_Pos 28U /*!< \brief SCTLR: TRE Position */ +#define SCTLR_TRE_Msk (1UL << SCTLR_TRE_Pos) /*!< \brief SCTLR: TRE Mask */ + +#define SCTLR_EE_Pos 25U /*!< \brief SCTLR: EE Position */ +#define SCTLR_EE_Msk (1UL << SCTLR_EE_Pos) /*!< \brief SCTLR: EE Mask */ + +#define SCTLR_UWXN_Pos 20U /*!< \brief SCTLR: UWXN Position */ +#define SCTLR_UWXN_Msk (1UL << SCTLR_UWXN_Pos) /*!< \brief SCTLR: UWXN Mask */ + +#define SCTLR_WXN_Pos 19U /*!< \brief SCTLR: WXN Position */ +#define SCTLR_WXN_Msk (1UL << SCTLR_WXN_Pos) /*!< \brief SCTLR: WXN Mask */ + +#define SCTLR_nTWE_Pos 18U /*!< \brief SCTLR: nTWE Position */ +#define SCTLR_nTWE_Msk (1UL << SCTLR_nTWE_Pos) /*!< \brief SCTLR: nTWE Mask */ + +#define SCTLR_nTWI_Pos 16U /*!< \brief SCTLR: nTWI Position */ +#define SCTLR_nTWI_Msk (1UL << SCTLR_nTWI_Pos) /*!< \brief SCTLR: nTWI Mask */ + +#define SCTLR_V_Pos 13U /*!< \brief SCTLR: V Position */ +#define SCTLR_V_Msk (1UL << SCTLR_V_Pos) /*!< \brief SCTLR: V Mask */ + +#define SCTLR_I_Pos 12U /*!< \brief SCTLR: I Position */ +#define SCTLR_I_Msk (1UL << SCTLR_I_Pos) /*!< \brief SCTLR: I Mask */ + +#define SCTLR_SED_Pos 8U /*!< \brief SCTLR: SED Position */ +#define SCTLR_SED_Msk (1UL << SCTLR_SED_Pos) /*!< \brief SCTLR: SED Mask */ + +#define SCTLR_ITD_Pos 7U /*!< \brief SCTLR: ITD Position */ +#define SCTLR_ITD_Msk (1UL << SCTLR_ITD_Pos) /*!< \brief SCTLR: ITD Mask */ + +#define SCTLR_THEE_Pos 6U /*!< \brief SCTLR: THEE Position */ +#define SCTLR_THEE_Msk (1UL << SCTLR_THEE_Pos) /*!< \brief SCTLR: THEE Mask */ + +#define SCTLR_CP15BEN_Pos 5U /*!< \brief SCTLR: CP15BEN Position */ +#define SCTLR_CP15BEN_Msk (1UL << SCTLR_CP15BEN_Pos) /*!< \brief SCTLR: CP15BEN Mask */ + +#define SCTLR_C_Pos 2U /*!< \brief SCTLR: C Position */ +#define SCTLR_C_Msk (1UL << SCTLR_C_Pos) /*!< \brief SCTLR: C Mask */ + +#define SCTLR_A_Pos 1U /*!< \brief SCTLR: A Position */ +#define SCTLR_A_Msk (1UL << SCTLR_A_Pos) /*!< \brief SCTLR: A Mask */ + +#define SCTLR_M_Pos 0U /*!< \brief SCTLR: M Position */ +#define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ + + + + /******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - L1 Cache Functions + - L2C-310 Cache Controller Functions + - PL1 Timer Functions + - GIC Functions + - MMU Functions + ******************************************************************************/ + +/* ########################## L1 Cache functions ################################# */ + +/** \brief Enable Caches by setting I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableCaches(void) { + __set_SCTLR_EL3( __get_SCTLR_EL3() | SCTLR_I_Msk | SCTLR_C_Msk); + __ISB(); +} + +/** \brief Disable Caches by clearing I and C bits in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableCaches(void) { + __set_SCTLR_EL3( __get_SCTLR_EL3() & (~SCTLR_I_Msk) & (~SCTLR_C_Msk)); + __ISB(); +} + +/** \brief Enable Branch Prediction by setting Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_EnableBTAC(void) { + +} + +/** \brief Disable Branch Prediction by clearing Z bit in SCTLR register. +*/ +__STATIC_FORCEINLINE void L1C_DisableBTAC(void) { + +} + +/** \brief Invalidate entire branch predictor array +*/ +__STATIC_FORCEINLINE void L1C_InvalidateBTAC(void) { + +} + +/** \brief Invalidate the whole instruction cache +*/ +__STATIC_FORCEINLINE void L1C_InvalidateICacheAll(void) { + +} + +/** \brief Invalidate the whole data cache. +*/ +__STATIC_FORCEINLINE void L1C_InvalidateDCacheAll(void) { + +} + + +/* ########################## L2 Cache functions ################################# */ +#if (__L2C_PRESENT == 1U) || defined(DOXYGEN) + +/** \brief Enable Level 2 Cache +*/ +__STATIC_INLINE void L2C_Enable(void) +{ + +} +#endif + +/* ########################## L3 Cache functions ################################# */ +#if (__L3C_PRESENT == 1U) || defined(DOXYGEN) + +#endif + +/* ########################## GIC functions ###################################### */ +#if (__GIC_PRESENT == 1U) || defined(DOXYGEN) + +#endif + +/* ########################## Generic Timer functions ############################ */ +#if (__TIM_PRESENT == 1U) || defined(DOXYGEN) + +#endif + +/* ########################## MMU functions ###################################### */ + +/** \brief Enable MMU +*/ +__STATIC_INLINE void MMU_Enable(void) +{ + +} + +/** \brief Disable MMU +*/ +__STATIC_INLINE void MMU_Disable(void) +{ + +} + +/** \brief Invalidate entire unified TLB +*/ + +__STATIC_INLINE void MMU_InvalidateTLB(void) +{ + +} + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CA53_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/Device/ARM/ARMCA53/Include/ARMCA53.h b/Device/ARM/ARMCA53/Include/ARMCA53.h new file mode 100644 index 0000000000..3c065aa227 --- /dev/null +++ b/Device/ARM/ARMCA53/Include/ARMCA53.h @@ -0,0 +1,102 @@ +/**************************************************************************//** + * @file ARMCA53.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCA53 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARMCA53_H__ +#define __ARMCA53_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CA53_REV 0x0004U /* Core revision r0p4 */ +#define __FPU_PRESENT 0U /* no FPU present */ +#define __FPU_DP 0U /* no double precision FPU */ +#define __DSP_PRESENT 0U /* no DSP extension present */ +#define __ICACHE_PRESENT 1U /* Instruction cache present */ +#define __DCACHE_PRESENT 1U /* Data cache present */ +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 0U /* no TIM present */ +#define __L2C_PRESENT 1U /* L2C present */ + +#include "core_ca53.h" /* Processor and core peripherals */ +#include "system_ARMCA53.h" /* System Header */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // __ARMCA53_H__ diff --git a/Device/ARM/ARMCA53/Include/ARMCA53_DSP_DP_FP.h b/Device/ARM/ARMCA53/Include/ARMCA53_DSP_DP_FP.h new file mode 100644 index 0000000000..31b0b94926 --- /dev/null +++ b/Device/ARM/ARMCA53/Include/ARMCA53_DSP_DP_FP.h @@ -0,0 +1,102 @@ +/**************************************************************************//** + * @file ARMCA53_DSP_DP_FP.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCA53 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARMCA53_DSP_DP_FP_H__ +#define __ARMCA53_DSP_DP_FP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CA53_REV 0x0004U /* Core revision r0p4 */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __FPU_DP 1U /* double precision FPU */ +#define __DSP_PRESENT 1U /* DSP extension present */ +#define __ICACHE_PRESENT 1U /* Instruction cache present */ +#define __DCACHE_PRESENT 1U /* Data cache present */ +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 0U /* no TIM present */ +#define __L2C_PRESENT 1U /* L2C present */ + +#include "core_ca53.h" /* Processor and core peripherals */ +#include "system_ARMCA53.h" /* System Header */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // __ARMCA53_DSP_DP_FP_H__ diff --git a/Device/ARM/ARMCA53/Include/ARMCA53_FP.h b/Device/ARM/ARMCA53/Include/ARMCA53_FP.h new file mode 100644 index 0000000000..2bbcbdf477 --- /dev/null +++ b/Device/ARM/ARMCA53/Include/ARMCA53_FP.h @@ -0,0 +1,102 @@ +/**************************************************************************//** + * @file ARMCA53_FP.h + * @brief CMSIS Core Peripheral Access Layer Header File for + * ARMCA53 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARMCA53_FP_H__ +#define __ARMCA53_FP_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* ------------------------- Interrupt Number Definition ------------------------ */ + + +/* ================================================================================ */ +/* ================ Processor and Core Peripheral Section ================ */ +/* ================================================================================ */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of Core Peripherals ----------------------------------- */ +#define __CA53_REV 0x0004U /* Core revision r0p4 */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __FPU_DP 0U /* no double precision FPU */ +#define __DSP_PRESENT 0U /* no DSP extension present */ +#define __ICACHE_PRESENT 1U /* Instruction cache present */ +#define __DCACHE_PRESENT 1U /* Data cache present */ +#define __GIC_PRESENT 1U /* GIC present */ +#define __TIM_PRESENT 0U /* no TIM present */ +#define __L2C_PRESENT 1U /* L2C present */ + +#include "core_ca53.h" /* Processor and core peripherals */ +#include "system_ARMCA53.h" /* System Header */ + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +#ifdef __cplusplus +} +#endif + +#endif // __ARMCA53_FP_H__ diff --git a/Device/ARM/ARMCA53/Include/system_ARMCA53.h b/Device/ARM/ARMCA53/Include/system_ARMCA53.h new file mode 100644 index 0000000000..aa6a416a8f --- /dev/null +++ b/Device/ARM/ARMCA53/Include/system_ARMCA53.h @@ -0,0 +1,58 @@ +/**************************************************************************//** + * @file system_ARMCA53.h + * @brief CMSIS Device System Header File for + * ARMA53 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __SYSTEM_ARMCA53_H +#define __SYSTEM_ARMCA53_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** + \brief System Clock Frequency (Core Clock) +*/ +extern uint32_t SystemCoreClock; + +/** + \brief Setup the microcontroller system. + + Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + \brief Update SystemCoreClock variable. + + Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_ARMCA53_H */ diff --git a/Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld new file mode 100644 index 0000000000..a0c23795a8 --- /dev/null +++ b/Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld @@ -0,0 +1,315 @@ +/****************************************************************************** + * @file gcc_arm.ld + * @brief GNU Linker Script for Cortex-A based device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/* + *-------- <<< Use Configuration Wizard in Context Menu >>> ------------------- + */ + +/*---------------------- Flash Configuration ---------------------------------- + Flash Configuration + Flash Base Address <0x0-0xFFFFFFFF:8> + Flash Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__ROM_BASE = 0x00000000; +__ROM_SIZE = 0x00040000; + +/*--------------------- Embedded RAM Configuration ---------------------------- + RAM Configuration + RAM Base Address <0x0-0xFFFFFFFF:8> + RAM Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__RAM_BASE = 0x20000000; +__RAM_SIZE = 0x00020000; + +/*--------------------- Stack / Heap Configuration ---------------------------- + Stack / Heap Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__STACK_SIZE = 0x00000400; +__HEAP_SIZE = 0x00000C00; + +/* + *-------------------- <<< end of configuration section >>> ------------------- + */ + +MEMORY +{ + FLASH (rx) : ORIGIN = __ROM_BASE, LENGTH = __ROM_SIZE + RAM (rwx) : ORIGIN = __RAM_BASE, LENGTH = __RAM_SIZE +} + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + KEEP(*(.vectors)) + *(.text*) + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + *(.gcc_except_table*) + + KEEP(*(.eh_frame*)) + } > FLASH + + /* + * SG veneers: + * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address + * must be set, either with the command line option �--section-start� or in a linker script, + * to indicate where to place these veneers in memory. + */ +/* + .gnu.sgstubs : + { + . = ALIGN(32); + } > FLASH +*/ + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + .copy.table : + { + . = ALIGN(8); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG ((__data_end__ - __data_start__) / 4) + /* Add each additional data section here */ +/* + LONG (__etext2) + LONG (__data2_start__) + LONG ((__data2_end__ - __data2_start__) / 4) +*/ + __copy_table_end__ = .; + } > FLASH + + .zero.table : + { + . = ALIGN(8); + __zero_table_start__ = .; + /* Add each additional bss section here */ +/* + LONG (__bss2_start__) + LONG ((__bss2_end__ - __bss2_start__) / 4) +*/ + __zero_table_end__ = .; + } > FLASH + + __etext = ALIGN (8); + + .data : AT (__etext) + { + __data_start__ = .; + *(vtable) + *(.data) + *(.data.*) + + . = ALIGN(8); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(8); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(8); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(8); + /* All data end */ + __data_end__ = .; + + } > RAM + + /* + * Secondary data section, optional + * + * Remember to add each additional data section + * to the .copy.table and .ecc.table above to asure proper + * initialization during startup. + */ +/* + __etext2 = ALIGN (8); + + .data2 : AT (__etext2) + { + . = ALIGN(8); + __data2_start__ = .; + *(.data2) + *(.data2.*) + . = ALIGN(8); + __data2_end__ = .; + + } > RAM2 +*/ + + /* ECC initialization is done by 64-bit writes thus __bss_start__ + * and __bss_end__ must be 8byte aligned */ + .bss : + { + . = ALIGN(8); + __bss_start__ = .; + *(.bss) + *(.bss.*) + *(COMMON) + . = ALIGN(8); + __bss_end__ = .; + } > RAM AT > RAM + + /* + * Secondary bss section, optional + * + * Remember to add each additional bss section + * to the .zero.table and .ecc.table above to asure proper + * initialization during startup. + */ +/* + .bss2 : + { + . = ALIGN(8); + __bss2_start__ = .; + *(.bss2) + *(.bss2.*) + . = ALIGN(8); + __bss2_end__ = .; + } > RAM2 AT > RAM2 +*/ + + .heap (COPY) : + { + . = ALIGN(8); + __end__ = .; + __HeapTop = .; + PROVIDE(end = .); + . = . + __HEAP_SIZE; + . = ALIGN(8); + __HeapLimit = .; + } > RAM + + .stack (ORIGIN(RAM) + LENGTH(RAM) - __STACK_SIZE - __EL2_STACK_SIZE - __EL3_STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __StackLimit = .; + . = . + __STACK_SIZE; + . = ALIGN(8); + __StackTop = .; + } > RAM + + /* Set EL2 stack. */ + .el2_stack (ORIGIN(RAM) + LENGTH(RAM) - __EL2_STACK_SIZE - __EL3_STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __EL2StackLimit = .; + . = . + __EL2_STACK_SIZE; + . = ALIGN(8); + __EL2StackTop = .; + } > RAM + + /* Set EL3 stack. */ + .el3_stack (ORIGIN(RAM) + LENGTH(RAM) - __EL3_STACK_SIZE) (COPY) : + { + . = ALIGN(8); + __EL3StackLimit = .; + . = . + __EL3_STACK_SIZE; + . = ALIGN(8); + __EL3StackTop = .; + } > RAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") +} diff --git a/Device/ARM/ARMCA53/Source/GCC/startup_ARMCA53.c b/Device/ARM/ARMCA53/Source/GCC/startup_ARMCA53.c new file mode 100644 index 0000000000..816d258700 --- /dev/null +++ b/Device/ARM/ARMCA53/Source/GCC/startup_ARMCA53.c @@ -0,0 +1,229 @@ +/****************************************************************************** + * @file startup_ARMCA53.c + * @brief CMSIS Core Device Startup File for Cortex-A53 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCA53) + #include "ARMCA53.h" +#elif defined (ARMCA53_FP) + #include "ARMCA53_FP.h" +#elif defined (ARMCA53_DSP_DP_FP) + #include "ARMCA53_DSP_DP_FP.h" +#else + #error device not specified! +#endif + +/*---------------------------------------------------------------------------- + Internal References + *----------------------------------------------------------------------------*/ +void __NO_RETURN EL3_Default_Handler(void); +void __NO_RETURN EL2_Default_Handler(void); +void __NO_RETURN EL1_Default_Handler(void); +void __NO_RETURN EL3_Reset_Handler(void); +void __NO_RETURN EL3_Reset_Handler_C(void); + + +/*---------------------------------------------------------------------------- + Exception / Interrupt Handler + *----------------------------------------------------------------------------*/ +void __NO_RETURN Current_EL3_SP0_Sync_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Current_EL3_SP0_IRQ_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Current_EL3_SP0_FIQ_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Current_EL3_SP0_SError_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Current_EL3_SPx_Sync_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Current_EL3_SPx_IRQ_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Current_EL3_SPx_FIQ_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Current_EL3_SPx_SError_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Lower_EL3_AArch64_Sync_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Lower_EL3_AArch64_IRQ_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Lower_EL3_AArch64_FIQ_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Lower_EL3_AArch64_SError_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Lower_EL3_AArch32_Sync_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Lower_EL3_AArch32_IRQ_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Lower_EL3_AArch32_FIQ_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); +void __NO_RETURN Lower_EL3_AArch32_SError_Handler (void) __attribute__ ((weak, alias("EL3_Default_Handler"))); + +void __NO_RETURN Current_EL2_SP0_Sync_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Current_EL2_SP0_IRQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Current_EL2_SP0_FIQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Current_EL2_SP0_SError_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Current_EL2_SPx_Sync_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Current_EL2_SPx_IRQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Current_EL2_SPx_FIQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Current_EL2_SPx_SError_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Lower_EL2_AArch64_Sync_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Lower_EL2_AArch64_IRQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Lower_EL2_AArch64_FIQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Lower_EL2_AArch64_SError_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Lower_EL2_AArch32_Sync_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Lower_EL2_AArch32_IRQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Lower_EL2_AArch32_FIQ_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); +void __NO_RETURN Lower_EL2_AArch32_SError_Handler (void) __attribute__ ((weak, alias("EL2_Default_Handler"))); + +void __NO_RETURN Current_EL1_SP0_Sync_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Current_EL1_SP0_IRQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Current_EL1_SP0_FIQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Current_EL1_SP0_SError_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Current_EL1_SPx_Sync_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Current_EL1_SPx_IRQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Current_EL1_SPx_FIQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Current_EL1_SPx_SError_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Lower_EL1_AArch64_Sync_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Lower_EL1_AArch64_IRQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Lower_EL1_AArch64_FIQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Lower_EL1_AArch64_SError_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Lower_EL1_AArch32_Sync_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Lower_EL1_AArch32_IRQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Lower_EL1_AArch32_FIQ_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); +void __NO_RETURN Lower_EL1_AArch32_SError_Handler (void) __attribute__ ((weak, alias("EL1_Default_Handler"))); + +__ASM("\n .macro ventry label \n .align 7 \n b \\label \n .endm"); + +/*---------------------------------------------------------------------------- + Exception / Interrupt Vector table + *----------------------------------------------------------------------------*/ + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wpedantic" +#endif + +void __VECTOR_TABLE_ATTRIBUTE __VECTOR_TABLE_EL3(void) +{ + __ASM volatile( + "ventry Current_EL3_SP0_Sync_Handler \n" + "ventry Current_EL3_SP0_IRQ_Handler \n" + "ventry Current_EL3_SP0_FIQ_Handler \n" + "ventry Current_EL3_SP0_SError_Handler \n" + "ventry Current_EL3_SPx_Sync_Handler \n" + "ventry Current_EL3_SPx_IRQ_Handler \n" + "ventry Current_EL3_SPx_FIQ_Handler \n" + "ventry Current_EL3_SPx_SError_Handler \n" + "ventry Lower_EL3_AArch64_Sync_Handler \n" + "ventry Lower_EL3_AArch64_IRQ_Handler \n" + "ventry Lower_EL3_AArch64_FIQ_Handler \n" + "ventry Lower_EL3_AArch64_SError_Handler \n" + "ventry Lower_EL3_AArch32_Sync_Handler \n" + "ventry Lower_EL3_AArch32_IRQ_Handler \n" + "ventry Lower_EL3_AArch32_FIQ_Handler \n" + "ventry Lower_EL3_AArch32_SError_Handler \n" + ); +} + +void __VECTOR_TABLE_ATTRIBUTE __VECTOR_TABLE_EL2(void) +{ + __ASM volatile( + "ventry Current_EL2_SP0_Sync_Handler \n" + "ventry Current_EL2_SP0_IRQ_Handler \n" + "ventry Current_EL2_SP0_FIQ_Handler \n" + "ventry Current_EL2_SP0_SError_Handler \n" + "ventry Current_EL2_SPx_Sync_Handler \n" + "ventry Current_EL2_SPx_IRQ_Handler \n" + "ventry Current_EL2_SPx_FIQ_Handler \n" + "ventry Current_EL2_SPx_SError_Handler \n" + "ventry Lower_EL2_AArch64_Sync_Handler \n" + "ventry Lower_EL2_AArch64_IRQ_Handler \n" + "ventry Lower_EL2_AArch64_FIQ_Handler \n" + "ventry Lower_EL2_AArch64_SError_Handler \n" + "ventry Lower_EL2_AArch32_Sync_Handler \n" + "ventry Lower_EL2_AArch32_IRQ_Handler \n" + "ventry Lower_EL2_AArch32_FIQ_Handler \n" + "ventry Lower_EL2_AArch32_SError_Handler \n" + ); +} + +void __VECTOR_TABLE_ATTRIBUTE __VECTOR_TABLE_EL1(void) +{ + __ASM volatile( + "ventry Current_EL1_SP0_Sync_Handler \n" + "ventry Current_EL1_SP0_IRQ_Handler \n" + "ventry Current_EL1_SP0_FIQ_Handler \n" + "ventry Current_EL1_SP0_SError_Handler \n" + "ventry Current_EL1_SPx_Sync_Handler \n" + "ventry Current_EL1_SPx_IRQ_Handler \n" + "ventry Current_EL1_SPx_FIQ_Handler \n" + "ventry Current_EL1_SPx_SError_Handler \n" + "ventry Lower_EL1_AArch64_Sync_Handler \n" + "ventry Lower_EL1_AArch64_IRQ_Handler \n" + "ventry Lower_EL1_AArch64_FIQ_Handler \n" + "ventry Lower_EL1_AArch64_SError_Handler \n" + "ventry Lower_EL1_AArch32_Sync_Handler \n" + "ventry Lower_EL1_AArch32_IRQ_Handler \n" + "ventry Lower_EL1_AArch32_FIQ_Handler \n" + "ventry Lower_EL1_AArch32_SError_Handler \n" + ); +} + +#if defined ( __GNUC__ ) +#pragma GCC diagnostic pop +#endif + +/*---------------------------------------------------------------------------- + __EARLY_INIT routine custom version + *----------------------------------------------------------------------------*/ +#undef __EARLY_INIT +#define __EARLY_INIT + +/*---------------------------------------------------------------------------- + Reset Handler called on controller reset + *----------------------------------------------------------------------------*/ +__ASM( + ".section .startup \n" + ".globl Reset_Handler \n" + ".type Reset_Handler, %function \n" + "Reset_Handler: \n" + + __EARLY_INIT + + "adrp x0, :pg_hi21:__EL3StackTop \n" + "add x0, x0, :lo12:__EL3StackTop \n" + "mov sp, x0 \n" + "b Reset_Handler_C \n" +); + +/*---------------------------------------------------------------------------- + Reset Handler C version called by "naked" Reset Handler + *----------------------------------------------------------------------------*/ +void __NO_RETURN Reset_Handler_C(void) +{ + SystemInit(); /* CMSIS System Initialization */ + + __PROGRAM_START(); /* Enter PreMain (C library entry point) */ +} + +/*---------------------------------------------------------------------------- + Default Handler for Exceptions / Interrupts + *----------------------------------------------------------------------------*/ +void EL3_Default_Handler(void) +{ + while(1); +} + +void EL2_Default_Handler(void) +{ + while(1); +} + +void EL1_Default_Handler(void) +{ + while(1); +} diff --git a/Device/ARM/ARMCA53/Source/system_ARMCA53.c b/Device/ARM/ARMCA53/Source/system_ARMCA53.c new file mode 100644 index 0000000000..dee9d1eae0 --- /dev/null +++ b/Device/ARM/ARMCA53/Source/system_ARMCA53.c @@ -0,0 +1,106 @@ +/**************************************************************************//** + * @file system_ARMCA53.c + * @brief CMSIS Device System Source File for + * ARMCA53 Device + * @version V1.0.0 + * @date 15. June 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCA53) + #include "ARMCA53.h" +#elif defined (ARMCA53_FP) + #include "ARMCA53_FP.h" +#elif defined (ARMCA53_DSP_DP_FP) + #include "ARMCA53_DSP_DP_FP.h" +#else + #error device not specified! +#endif + +extern void MMU_CreateTranslationTable(void); + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ +#define SYSTEM_CLOCK 12000000U + +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint64_t __VECTOR_TABLE_EL3; +extern uint64_t __VECTOR_TABLE_EL2; +extern uint64_t __VECTOR_TABLE_EL1; + +/*---------------------------------------------------------------------------- + System Core Clock Variable + *----------------------------------------------------------------------------*/ +uint32_t SystemCoreClock = SYSTEM_CLOCK; /* System Core Clock Frequency */ + +/*---------------------------------------------------------------------------- + System Core Clock update function + *----------------------------------------------------------------------------*/ +void SystemCoreClockUpdate (void) +{ + SystemCoreClock = SYSTEM_CLOCK; +} + +/*---------------------------------------------------------------------------- + System initialization function + *----------------------------------------------------------------------------*/ +void SystemInit (void) +{ + + __set_VBAR_EL3((uint64_t)&__VECTOR_TABLE_EL3); + __set_VBAR_EL2((uint64_t)&__VECTOR_TABLE_EL2); + __set_VBAR_EL1((uint64_t)&__VECTOR_TABLE_EL1); + + // Invalidate entire Unified TLB + MMU_InvalidateTLB(); + + // Invalidate entire branch predictor array + L1C_InvalidateBTAC(); + + // Invalidate instruction cache and flush branch target cache + L1C_InvalidateICacheAll(); + + // Invalidate data cache + L1C_InvalidateDCacheAll(); + +#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) + // Enable FPU + __FPU_Enable(); +#endif + + // Create Translation Table + //MMU_CreateTranslationTable(); + + // Enable MMU + //MMU_Enable(); + + // Enable Caches + L1C_EnableCaches(); + L1C_EnableBTAC(); + +#if (__L2C_PRESENT == 1) + // Enable GIC + L2C_Enable(); +#endif + + SystemCoreClock = SYSTEM_CLOCK; +} From fff37e97b686abdabc6038464b9b4ae43175b357 Mon Sep 17 00:00:00 2001 From: Alexander Fedotov Date: Thu, 20 Aug 2020 16:11:18 +0300 Subject: [PATCH 2/2] Added MMU initialization according to ARM application note "DAI0527A Bare-metal Boot Code for ARMv8-A Processors" --- CMSIS/Core_AArch64/Include/cmsis_gcc.h | 8 +- CMSIS/Core_AArch64/Include/core_ca53.h | 127 +++++++++++++----- Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld | 39 ++++-- .../ARM/ARMCA53/Source/GCC/startup_ARMCA53.c | 34 +++-- Device/ARM/ARMCA53/Source/mmu_ARMCA53.c | 108 +++++++++++++++ Device/ARM/ARMCA53/Source/system_ARMCA53.c | 8 +- 6 files changed, 263 insertions(+), 61 deletions(-) create mode 100644 Device/ARM/ARMCA53/Source/mmu_ARMCA53.c diff --git a/CMSIS/Core_AArch64/Include/cmsis_gcc.h b/CMSIS/Core_AArch64/Include/cmsis_gcc.h index b1c0d7e7c5..322704db86 100644 --- a/CMSIS/Core_AArch64/Include/cmsis_gcc.h +++ b/CMSIS/Core_AArch64/Include/cmsis_gcc.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file cmsis_gcc.h * @brief CMSIS compiler GCC header file - * @version V1.0.0 - * @date 15. June 2020 + * @version V1.0.1 + * @date 20. August 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. @@ -253,7 +253,7 @@ __STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) */ __STATIC_FORCEINLINE void __ISB(void) { - __ASM volatile ("isb 0xF":::"memory"); + __ASM volatile ("isb":::"memory"); } @@ -264,7 +264,7 @@ __STATIC_FORCEINLINE void __ISB(void) */ __STATIC_FORCEINLINE void __DSB(void) { - __ASM volatile ("dsb 0xF":::"memory"); + __ASM volatile ("dsb sy":::"memory"); } diff --git a/CMSIS/Core_AArch64/Include/core_ca53.h b/CMSIS/Core_AArch64/Include/core_ca53.h index f313b4df1b..ed1f935075 100644 --- a/CMSIS/Core_AArch64/Include/core_ca53.h +++ b/CMSIS/Core_AArch64/Include/core_ca53.h @@ -1,8 +1,8 @@ /**************************************************************************//** * @file core_ca53.h * @brief CMSIS Cortex-A53 Core Peripheral Access Layer Header File - * @version V1.0.0 - * @date 15. June 2020 + * @version V1.0.1 + * @date 20. August 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. @@ -371,37 +371,48 @@ typedef union #define CPSR_M_UND 0x1BU /*!< \brief CPSR: M Undefined mode (PL1) */ #define CPSR_M_SYS 0x1FU /*!< \brief CPSR: M System mode (PL1) */ -/* CP15 Register SCTLR */ +/* Register SCTLR */ typedef union { struct { - uint32_t M:1; /*!< \brief bit: 0 MMU enable */ - uint32_t A:1; /*!< \brief bit: 1 Alignment check enable */ - uint32_t C:1; /*!< \brief bit: 2 Cache enable */ - RESERVED(0:2, uint32_t) - uint32_t CP15BEN:1; /*!< \brief bit: 5 CP15 barrier enable */ - uint32_t THEE:1; /*!< \brief bit: 6 */ - uint32_t ITD:1; /*!< \brief bit: 7 IT disable */ - uint32_t SED:1; /*!< \brief bit: 8 SETEBD disable */ - RESERVED(1:3, uint32_t) - uint32_t I:1; /*!< \brief bit: 12 Instruction cache enable */ - uint32_t V:1; /*!< \brief bit: 13 Vectors bit */ - RESERVED(2:2, uint32_t) - uint32_t nTWI:1; /*!< \brief bit: 16 Not trap WFI */ - RESERVED(3:1, uint32_t) - uint32_t nTWE:1; /*!< \brief bit: 18 Not trap WFE */ - uint32_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ - uint32_t UWXN:1; /*!< \brief bit: 20 Unprivileged write permission implies PL1 XN */ - RESERVED(4:4, uint32_t) - uint32_t EE:1; /*!< \brief bit: 25 Exception Endianness */ - RESERVED(5:2, uint32_t) - uint32_t TRE:1; /*!< \brief bit: 28 TEX remap enable. */ - uint32_t AFE:1; /*!< \brief bit: 29 Access flag enable */ - uint32_t TE:1; /*!< \brief bit: 30 Thumb Exception enable */ - RESERVED(6:1, uint32_t) + uint64_t M:1; /*!< \brief bit: 0 MMU enable */ + uint64_t A:1; /*!< \brief bit: 1 Alignment check enable */ + uint64_t C:1; /*!< \brief bit: 2 Cache enable */ + uint64_t SA:1; /*!< \brief bit: 3 SP Alignment check enable */ + RESERVED(1:2, uint64_t) //[5:4] + uint64_t nAA:1; /*!< \brief bit: 6 Non-aligned access */ + RESERVED(2:4, uint64_t) //[10:7] + uint64_t EOS:1; /*!< \brief bit: 11 Exception Exit is Context Synchronizing */ + uint64_t I:1; /*!< \brief bit: 12 Instruction cache enable */ + uint64_t EnDB:1; //13 + RESERVED(3:2, uint64_t) //[15:14] + RESERVED(4:1, uint64_t) //[16] + RESERVED(5:1, uint64_t) //[17] + RESERVED(6:1, uint64_t) //[18] + uint64_t WXN:1; /*!< \brief bit: 19 Write permission implies XN */ + RESERVED(7:1, uint64_t) //[20] + uint64_t IESB:1; //21 + uint64_t EIS:1; //22 + RESERVED(8:1, uint64_t) //[23] + RESERVED(9:1, uint64_t) //[24] + uint64_t EE:1; /*!< \brief bit: 25 Exception Endianness */ + RESERVED(10:1, uint64_t) //[26] + uint64_t EnDA:1; //27 + RESERVED(11:2, uint64_t) //[29:28] + uint64_t EnIB:1; //30 + uint64_t EnIA:1; //31 + RESERVED(12:4, uint64_t) //[35:32] + uint64_t BT:1; //36 + uint64_t ITFSB:1; //37 + RESERVED(13:2, uint64_t) //[39:38] + uint64_t TCF:2; //[41:40] + RESERVED(14:1, uint64_t) //[42] + uint64_t ATA:1; //43 + uint64_t DSSBS:1; //44 + RESERVED(15:19, uint64_t) //[63:45] } b; /*!< \brief Structure used for bit access */ - uint32_t w; /*!< \brief Type used for word access */ + uint64_t w; /*!< \brief Type used for word access */ } SCTLR_Type; #define SCTLR_TE_Pos 30U /*!< \brief SCTLR: TE Position */ @@ -456,6 +467,55 @@ typedef union #define SCTLR_M_Msk (1UL << SCTLR_M_Pos) /*!< \brief SCTLR: M Mask */ +/* Register TCR_EL3 */ +typedef union +{ + struct + { + uint64_t T0SZ:6; //[5:0] + RESERVED(1:2, uint64_t) //[7:6] + uint64_t IRGN0:2; //[9:8] + uint64_t ORGN0:2; //[11:10] + uint64_t SH0:2; //[13:12] + uint64_t TG0:2; //[15:14] + uint64_t PS:3; //[18:16] + RESERVED(2:1, uint64_t) //[19] + uint64_t TBI:1; //[20] + uint64_t HA:1; //[21] + uint64_t HD:1; //[22] + RESERVED(3:1, uint64_t) //[23] + uint64_t HPD:1; //[24] + uint64_t HWU59:1; //[25] + uint64_t HWU60:1; //[26] + uint64_t HWU61:1; //[27] + uint64_t HWU62:1; //[28] + uint64_t TBID:1; //[29] + uint64_t TCMA:1; //[30] + RESERVED(4:1, uint64_t) //[31] + RESERVED(5:32, uint64_t) //[63:32] + } b; + uint64_t w; /*!< \brief Type used for word access */ +} TCR_EL3_Type; + + +/* Register MPIDR_EL1 */ +typedef union +{ + struct + { + uint64_t Aff0:8; + uint64_t Aff1:8; + uint64_t Aff2:8; + uint64_t MT:1; + RESERVED(0:5, uint64_t) + uint64_t U:1; + RESERVED(1:1, uint64_t) + uint64_t Aff3:8; + RESERVED(2:24, uint64_t) + } b; /*!< \brief Structure used for bit access */ + uint64_t w; /*!< \brief Type used for word access */ +} MPIDR_EL1_Type; + /******************************************************************************* * Hardware Abstraction Layer @@ -546,14 +606,16 @@ __STATIC_INLINE void L2C_Enable(void) */ __STATIC_INLINE void MMU_Enable(void) { - + __set_SCTLR_EL3( __get_SCTLR_EL3() | SCTLR_M_Msk); + __ISB(); } /** \brief Disable MMU */ __STATIC_INLINE void MMU_Disable(void) { - + __set_SCTLR_EL3( __get_SCTLR_EL3() & (~SCTLR_M_Msk)); + __ISB(); } /** \brief Invalidate entire unified TLB @@ -561,7 +623,10 @@ __STATIC_INLINE void MMU_Disable(void) __STATIC_INLINE void MMU_InvalidateTLB(void) { - + __DSB(); + __ASM volatile("tlbi vmalle1is"); + __DSB(); + __ISB(); } diff --git a/Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld b/Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld index a0c23795a8..9b0ce21b4d 100644 --- a/Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld +++ b/Device/ARM/ARMCA53/Source/GCC/gcc_arm.ld @@ -1,8 +1,8 @@ /****************************************************************************** * @file gcc_arm.ld * @brief GNU Linker Script for Cortex-A based device - * @version V1.0.0 - * @date 15. June 2020 + * @version V1.0.1 + * @date 20. August 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. @@ -50,8 +50,22 @@ __RAM_SIZE = 0x00020000; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -----------------------------------------------------------------------------*/ -__STACK_SIZE = 0x00000400; -__HEAP_SIZE = 0x00000C00; +__STACK_SIZE = 0x00004000; +__HEAP_SIZE = 0x0000C000; + +/*--------------------- EL2 Stack Configuration ------------------------------- + EL2 Stack Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__EL2_STACK_SIZE = 0x00004000; + +/*--------------------- EL3 Stack Configuration ------------------------------- + EL3 Stack Configuration + Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + + -----------------------------------------------------------------------------*/ +__EL3_STACK_SIZE = 0x00004000; /* *-------------------- <<< end of configuration section >>> ------------------- @@ -99,6 +113,8 @@ SECTIONS { .text : { + KEEP(*(.startup)) + KEEP(*(.vectors)) *(.text*) @@ -128,7 +144,7 @@ SECTIONS /* * SG veneers: * All SG veneers are placed in the special output section .gnu.sgstubs. Its start address - * must be set, either with the command line option �--section-start� or in a linker script, + * must be set, either with the command line option ?--section-start? or in a linker script, * to indicate where to place these veneers in memory. */ /* @@ -137,6 +153,7 @@ SECTIONS . = ALIGN(32); } > FLASH */ + .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) @@ -177,6 +194,12 @@ SECTIONS __zero_table_end__ = .; } > FLASH + .xlat_tables : + { + . = ALIGN(4096); + *(.xlat_tables) + } > RAM + __etext = ALIGN (8); .data : AT (__etext) @@ -199,7 +222,6 @@ SECTIONS KEEP(*(.init_array)) PROVIDE_HIDDEN (__init_array_end = .); - . = ALIGN(8); /* finit data */ PROVIDE_HIDDEN (__fini_array_start = .); @@ -232,12 +254,9 @@ SECTIONS *(.data2.*) . = ALIGN(8); __data2_end__ = .; - } > RAM2 */ - /* ECC initialization is done by 64-bit writes thus __bss_start__ - * and __bss_end__ must be 8byte aligned */ .bss : { . = ALIGN(8); @@ -271,8 +290,8 @@ SECTIONS .heap (COPY) : { . = ALIGN(8); - __end__ = .; __HeapTop = .; + __end__ = .; PROVIDE(end = .); . = . + __HEAP_SIZE; . = ALIGN(8); diff --git a/Device/ARM/ARMCA53/Source/GCC/startup_ARMCA53.c b/Device/ARM/ARMCA53/Source/GCC/startup_ARMCA53.c index 816d258700..b2ca0992ff 100644 --- a/Device/ARM/ARMCA53/Source/GCC/startup_ARMCA53.c +++ b/Device/ARM/ARMCA53/Source/GCC/startup_ARMCA53.c @@ -1,8 +1,8 @@ /****************************************************************************** * @file startup_ARMCA53.c * @brief CMSIS Core Device Startup File for Cortex-A53 Device - * @version V1.0.0 - * @date 15. June 2020 + * @version V1.0.1 + * @date 20. August 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. @@ -32,14 +32,21 @@ #error device not specified! #endif +/*---------------------------------------------------------------------------- + External References + *----------------------------------------------------------------------------*/ +extern uint32_t __INITIAL_SP; + +extern __NO_RETURN void __PROGRAM_START(void); + /*---------------------------------------------------------------------------- Internal References *----------------------------------------------------------------------------*/ void __NO_RETURN EL3_Default_Handler(void); void __NO_RETURN EL2_Default_Handler(void); void __NO_RETURN EL1_Default_Handler(void); -void __NO_RETURN EL3_Reset_Handler(void); -void __NO_RETURN EL3_Reset_Handler_C(void); +void __NO_RETURN Reset_Handler(void); +void __NO_RETURN Reset_Handler_C(void); /*---------------------------------------------------------------------------- @@ -187,23 +194,26 @@ void __VECTOR_TABLE_ATTRIBUTE __VECTOR_TABLE_EL1(void) Reset Handler called on controller reset *----------------------------------------------------------------------------*/ __ASM( - ".section .startup \n" - ".globl Reset_Handler \n" - ".type Reset_Handler, %function \n" + "\t.section .startup,\"ax\",@progbits \n" + "\t.align 2 \n" + "\t.globl Reset_Handler \n" + "\t.type Reset_Handler, %function \n" "Reset_Handler: \n" __EARLY_INIT - "adrp x0, :pg_hi21:__EL3StackTop \n" - "add x0, x0, :lo12:__EL3StackTop \n" - "mov sp, x0 \n" - "b Reset_Handler_C \n" + "#__set_SP((uint64)&__INITIAL_SP) \n" \ + "\tadrp x0, :pg_hi21:__EL3StackTop \n" + "\tadd x0, x0, :lo12:__EL3StackTop \n" + "\tmov sp, x0 \n" + "\tb Reset_Handler_C \n" + "\t.size Reset_Handler, .-Reset_Handler \n" ); /*---------------------------------------------------------------------------- Reset Handler C version called by "naked" Reset Handler *----------------------------------------------------------------------------*/ -void __NO_RETURN Reset_Handler_C(void) +void __NO_RETURN __attribute__((section(".startup"))) Reset_Handler_C(void) { SystemInit(); /* CMSIS System Initialization */ diff --git a/Device/ARM/ARMCA53/Source/mmu_ARMCA53.c b/Device/ARM/ARMCA53/Source/mmu_ARMCA53.c new file mode 100644 index 0000000000..e9782fe4e7 --- /dev/null +++ b/Device/ARM/ARMCA53/Source/mmu_ARMCA53.c @@ -0,0 +1,108 @@ +/**************************************************************************//** + * @file mmu_ARMCA53.c + * @brief CMSIS Device System Source File for + * ARMCA53 Device + * @version V1.0.0 + * @date 20. August 2020 + ******************************************************************************/ +/* + * Copyright (c) 2020 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined (ARMCA53) + #include "ARMCA53.h" +#elif defined (ARMCA53_FP) + #include "ARMCA53_FP.h" +#elif defined (ARMCA53_DSP_DP_FP) + #include "ARMCA53_DSP_DP_FP.h" +#else + #error device not specified! +#endif + +#define TTB_ENTRIES 512 +#define TTB_ENTRY_SIZE 64 + +#define TTB_SIZE (TTB_ENTRIES) + +static uint64_t __ALIGNED(4096) __attribute__((section(".xlat_tables"))) ttb0_base[TTB_SIZE] = {0}; +static uint64_t __ALIGNED(4096) __attribute__((section(".xlat_tables"))) level2_pagetable[TTB_SIZE] = {0}; + + +/*---------------------------------------------------------------------------- + MMU initialization + *----------------------------------------------------------------------------*/ +void MMU_CreateTranslationTable(void) +{ + uint64_t mair; + uint64_t ttb_entry; + TCR_EL3_Type tcr_el3; + + //According to ARM application note "DAI0527A Bare-metal Boot Code for ARMv8-A Processors" + + // Initialize translation table control registers + + tcr_el3.w = 0; + tcr_el3.b.T0SZ = 32; //The region size is 2^(64-T0SZ) bytes + tcr_el3.b.IRGN0 = 1; //Normal memory, Inner Write-Back Read-Allocate Write-Allocate Cacheable. + tcr_el3.b.ORGN0 = 1; //Normal memory, Outer Write-Back Read-Allocate Write-Allocate Cacheable. + tcr_el3.b.SH0 = 3; //Inner Shareable. + tcr_el3.b.TG0 = 0; //Granule size 4KB for the TTBR0_EL3 + tcr_el3.b.PS = 0; //Physical Address Size 32 bits, 4GB. + __set_TCR_EL3(tcr_el3.w); + + /* ATTR0 Device-nGnRnE, ATTR1 Device, ATTR2 Normal Non-Cacheable , ATTR3 Normal Cacheable. */ + mair = 0xFF440400; + __set_MAIR_EL3(mair); + + /* ttb0_base must be a 4KB-aligned address. */ + __set_TTBR0_EL3((uint64_t)&ttb0_base); + + + // Set up translation table entries in memory with looped store + // instructions. + // Set the level 1 translation table. + // The first entry points to level2_pagetable. + ttb_entry = (uint64_t)&level2_pagetable; // Must be a 4KB align address. + ttb_entry &= 0xFFFFF000; // NSTable=0 APTable=0 XNTable=0 PXNTable=0. + ttb_entry |= 0x3; + ttb0_base[0] = ttb_entry; + + // The second entry is 1GB block from 0x40000000 to 0x7FFFFFFF. + // Executable Inner and Outer Shareable. + // R/W at all ELs secure memory + // AttrIdx=000 Device-nGnRnE. + ttb_entry = 0x40000741; + ttb0_base[1] = ttb_entry; + + // The third entry is 1GB block from 0x80000000 to 0xBFFFFFFF. + ttb_entry = 0x80000741; + ttb0_base[2] = ttb_entry; + + // The fourth entry is 1GB block from 0xC0000000 to 0xFFFFFFFF. + ttb_entry = 0xC0000741; + ttb0_base[3] = ttb_entry; + + // Set level 2 translation table. + ttb_entry = 0x0000074D; + for(uint32_t l2_idx = 0; l2_idx < TTB_ENTRIES; l2_idx++ ) { + level2_pagetable[l2_idx] = ttb_entry; + ttb_entry += 0x00200000; // Increase 2MB address each time. + } + + __ISB(); + +} diff --git a/Device/ARM/ARMCA53/Source/system_ARMCA53.c b/Device/ARM/ARMCA53/Source/system_ARMCA53.c index dee9d1eae0..0a426fe7a1 100644 --- a/Device/ARM/ARMCA53/Source/system_ARMCA53.c +++ b/Device/ARM/ARMCA53/Source/system_ARMCA53.c @@ -2,8 +2,8 @@ * @file system_ARMCA53.c * @brief CMSIS Device System Source File for * ARMCA53 Device - * @version V1.0.0 - * @date 15. June 2020 + * @version V1.0.1 + * @date 20. August 2020 ******************************************************************************/ /* * Copyright (c) 2020 Arm Limited. All rights reserved. @@ -88,10 +88,10 @@ void SystemInit (void) #endif // Create Translation Table - //MMU_CreateTranslationTable(); + MMU_CreateTranslationTable(); // Enable MMU - //MMU_Enable(); + MMU_Enable(); // Enable Caches L1C_EnableCaches();