RISC-V and AARCH64 compatibility for cmsis-dsp library

[ua1arn]

Only two lines.,.. Same problem and similar for aarch64 processors
`From 909ee3f39a3c5f6cc2d99fcab48ae6fc4e09371a Mon Sep 17 00:00:00 2001
From: ua1arn [email protected]
Date: Wed, 15 Mar 2023 18:09:59 +0300
Subject: [PATCH] risc-v compatibility

---

CMSIS/Core_A/Include/cmsis_gcc.h | 2 ++
1 file changed, 2 insertions(+)

diff --git a/CMSIS/Core_A/Include/cmsis_gcc.h b/CMSIS/Core_A/Include/cmsis_gcc.h
index f468844c9..36393a7b2 100644
--- a/CMSIS/Core_A/Include/cmsis_gcc.h
+++ b/CMSIS/Core_A/Include/cmsis_gcc.h
@@ -113,6 +113,7 @@
#endif

+#if ! defined __riscv
/* ########################## Core Instruction Access ######################### /
/*
\brief No Operation
@@ -966,6 +967,7 @@ __STATIC_INLINE void __FPU_Enable(void)

/*@} end of group CMSIS_Core_intrinsics */

+#endif /* ! defined __riscv */
#pragma GCC diagnostic pop

#endif /* __CMSIS_GCC_H */

2.32.0.windows.2

`