Multiple Packages not possible

[DarkLuk42]

It would be nice if there would be a possibility to add more than just the DIP pintable.
Some chips have different packages and currently only one is possible.

Examples:
http://datasheets.maximintegrated.com/en/ds/DS32kHz.pdf
http://www.atmel.com/dyn/resources/prod_documents/doc2586.pdf

Furthermore the pins have additional data in the sym field, it would be more structured and really nice if it would be moved to a new field extra_syms.

And here how the ATTINY85.yaml could look with multiple packages:

name:        ATtiny85
description: "8-bit AVR® microcontroller"
aliases:     [ATtiny25, ATtiny45]
pincount:    8
family:      "Atmel"
datasheet:   "http://www.atmel.com/dyn/resources/prod_documents/doc2586.pdf"
packages:
  PDIP: &DIP [PB5, PB3, PB4, GND, PB0, PB1, PB2, Vcc]
  SOIC: *DIP
  TSSOP: *DIP
  QFN:
    1: PB5
    2: PB3
    5: PB4
    8: GND
    11: PB0
    12: PB1
    14: PB2
    15: Vcc
    BOTTOM: GND
pins:
  PB5:
    extra_syms: [PCINT5, ~RESET, ADC0, dW]
    desc: reset (active low); port B
  PB3:
    extra_syms: [PCINT3, XTAL1, CLKI, ~OC1B, ADC3]
    desc: crystal connection; external clock input; port B
  PB4:
    extra_syms: [PCINT4, XTAL2, CLKO, OC1B, ADC2]
    desc: crystal connection; clock output; port B
  GND:
    desc: ground
  PB0:
    extra_syms: [MOSI, DI, SDA, AIN0, OC0A, ~OC1A, AREF, PCINT0]
    desc: SPI master output/slave input; 2-wire data; ADC reference; port B
  PB1:
    extra_syms: [MISO, DO, AIN1, OC0B, OC1A, PCINT1]
    desc: SPI master input/slave output; port B
  PB2:
    extra_syms: [SCK, USCK, SCL, ADC1, T0, INT0, PCINT2]
    desc: SPI master clock; 2-wire clock; external interrupt 0; port B
  Vcc:
    desc: supply voltage
specs:
  - param: Flash memory
    val:   [2K (ATtiny25), 4K (ATtiny45), 8K (ATtiny85)]
    unit:  bytes
  - param: Internal SRAM
    val:   [128 (ATtiny25), 256 (ATtiny45), 512 (ATtiny85)]
    unit:  bytes
  - param: EEPROM
    val:   [128 (ATtiny25), 256 (ATtiny45), 512 (ATtiny85)]
    unit:  bytes
  - param: Programmable I/O lines
    val:   6
  - param: Maximum clock frequency
    val:   20
    unit:  MHz
...```

[74hc595]

Agreed; this would indeed be useful. When I started this project I was only doing through-hole hobbyist stuff, so DIPs were all I needed. The backend code at msarnoff.org/chipdb has no support for quad packages, and I imagine some CSS magic would be required to rotate the top/bottom labels 90 degrees.

I'm not sure when I'd have the time to migrate the existing entries to a schema like the one described above. If you or someone else would like to start a fork, you have my blessing.

[DarkLuk42]

I created a Pull-Request: #6

PS: I didn't extract the extra_syms yet, I didn't were sure if you would like this or not.